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FEB_2314 11.12.24 08:39:28
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08:39:28:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:39:28:ST3_Shared:INFO: FEB-Sensor
08:39:28:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:39:31:ST3_Shared:INFO: STS mode selected
08:39:35:ST3_ModuleSelector:DEBUG: M3DR4B2000132A2
08:39:35:ST3_ModuleSelector:DEBUG: L3DR400013
08:39:35:ST3_ModuleSelector:DEBUG: 22373
08:39:35:ST3_ModuleSelector:DEBUG: 62x62
08:39:35:ST3_ModuleSelector:DEBUG: A
08:39:35:ST3_ModuleSelector:DEBUG: M3DR4B2000132A2
08:39:35:ST3_ModuleSelector:DEBUG: L3DR400013
08:39:35:ST3_ModuleSelector:DEBUG: 22373
08:39:35:ST3_ModuleSelector:DEBUG: 62x62
08:39:35:ST3_ModuleSelector:DEBUG: A
08:39:41:ST3_ModuleSelector:INFO: M3DR4B2000132A2
08:39:41:ST3_ModuleSelector:INFO: 22373
08:39:41:febtest:INFO: Testing FEB with SN 2314
08:39:43:smx_tester:INFO: Scanning setup
08:39:43:elinks:INFO: Disabling clock on downlink 0
08:39:43:elinks:INFO: Disabling clock on downlink 1
08:39:43:elinks:INFO: Disabling clock on downlink 2
08:39:43:elinks:INFO: Disabling clock on downlink 3
08:39:43:elinks:INFO: Disabling clock on downlink 4
08:39:43:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:39:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
08:39:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:39:43:elinks:INFO: Disabling clock on downlink 0
08:39:43:elinks:INFO: Disabling clock on downlink 1
08:39:43:elinks:INFO: Disabling clock on downlink 2
08:39:43:elinks:INFO: Disabling clock on downlink 3
08:39:43:elinks:INFO: Disabling clock on downlink 4
08:39:43:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:39:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
08:39:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:39:43:elinks:INFO: Disabling clock on downlink 0
08:39:43:elinks:INFO: Disabling clock on downlink 1
08:39:43:elinks:INFO: Disabling clock on downlink 2
08:39:43:elinks:INFO: Disabling clock on downlink 3
08:39:43:elinks:INFO: Disabling clock on downlink 4
08:39:43:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:39:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:39:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
08:39:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
08:39:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
08:39:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
08:39:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
08:39:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
08:39:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
08:39:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
08:39:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
08:39:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
08:39:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
08:39:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
08:39:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
08:39:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
08:39:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
08:39:43:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
08:39:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:39:43:elinks:INFO: Disabling clock on downlink 0
08:39:43:elinks:INFO: Disabling clock on downlink 1
08:39:43:elinks:INFO: Disabling clock on downlink 2
08:39:43:elinks:INFO: Disabling clock on downlink 3
08:39:43:elinks:INFO: Disabling clock on downlink 4
08:39:43:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:39:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
08:39:43:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
08:39:44:elinks:INFO: Disabling clock on downlink 0
08:39:44:elinks:INFO: Disabling clock on downlink 1
08:39:44:elinks:INFO: Disabling clock on downlink 2
08:39:44:elinks:INFO: Disabling clock on downlink 3
08:39:44:elinks:INFO: Disabling clock on downlink 4
08:39:44:setup_element:INFO: Checking SOS, encoding_mode: SOS
08:39:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
08:39:44:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
08:39:44:setup_element:INFO: Scanning clock phase
08:39:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:39:44:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:39:44:setup_element:INFO: Clock phase scan results for group 0, downlink 2
08:39:44:setup_element:INFO: Eye window for uplink 16: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
08:39:44:setup_element:INFO: Eye window for uplink 17: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
08:39:44:setup_element:INFO: Eye window for uplink 18: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
08:39:44:setup_element:INFO: Eye window for uplink 19: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
08:39:44:setup_element:INFO: Eye window for uplink 20: ________________________________________________________________________________
Clock Delay: 40
08:39:44:setup_element:INFO: Eye window for uplink 21: ________________________________________________________________________________
Clock Delay: 40
08:39:44:setup_element:INFO: Eye window for uplink 22: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:39:44:setup_element:INFO: Eye window for uplink 23: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
08:39:44:setup_element:INFO: Eye window for uplink 24: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
08:39:44:setup_element:INFO: Eye window for uplink 25: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
08:39:44:setup_element:INFO: Eye window for uplink 26: ________________________________________________________________________________
Clock Delay: 40
08:39:44:setup_element:INFO: Eye window for uplink 27: ________________________________________________________________________________
Clock Delay: 40
08:39:44:setup_element:INFO: Eye window for uplink 28: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
08:39:44:setup_element:INFO: Eye window for uplink 29: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
08:39:44:setup_element:INFO: Eye window for uplink 30: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
08:39:44:setup_element:INFO: Eye window for uplink 31: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
08:39:44:setup_element:INFO: Setting the clock phase to 32 for group 0, downlink 2
==============================================OOO==============================================
08:39:44:setup_element:INFO: Scanning data phases
08:39:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:39:44:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:39:50:setup_element:INFO: Data phase scan results for group 0, downlink 2
08:39:50:setup_element:INFO: Eye window for uplink 16: X___________________________________XXXX
Data delay found: 18
08:39:50:setup_element:INFO: Eye window for uplink 17: __________________________________XXXXX_
Data delay found: 16
08:39:50:setup_element:INFO: Eye window for uplink 18: XXXX_________________________________XXX
Data delay found: 20
08:39:50:setup_element:INFO: Eye window for uplink 19: XX_________________________________XXXXX
Data delay found: 18
08:39:50:setup_element:INFO: Eye window for uplink 20: XXXX___________________________________X
Data delay found: 21
08:39:50:setup_element:INFO: Eye window for uplink 21: XXXX_________________________________XXX
Data delay found: 20
08:39:50:setup_element:INFO: Eye window for uplink 22: XXX_________________________________XXXX
Data delay found: 19
08:39:50:setup_element:INFO: Eye window for uplink 23: XXXXXX_____________________________XXXXX
Data delay found: 20
08:39:50:setup_element:INFO: Eye window for uplink 24: ________XXXXXX__________________________
Data delay found: 30
08:39:50:setup_element:INFO: Eye window for uplink 25: __________XXXXXX________________________
Data delay found: 32
08:39:50:setup_element:INFO: Eye window for uplink 26: _______XXXXX____________________________
Data delay found: 29
08:39:50:setup_element:INFO: Eye window for uplink 27: __________XXXXX_________________________
Data delay found: 32
08:39:50:setup_element:INFO: Eye window for uplink 28: ___________XXXXX________________________
Data delay found: 33
08:39:50:setup_element:INFO: Eye window for uplink 29: ______________XXXXX_____________________
Data delay found: 36
08:39:50:setup_element:INFO: Eye window for uplink 30: _________________XXXXXX_________________
Data delay found: 39
08:39:50:setup_element:INFO: Eye window for uplink 31: _________________XXXXXX_________________
Data delay found: 39
08:39:50:setup_element:INFO: Setting the data phase to 18 for uplink 16
08:39:50:setup_element:INFO: Setting the data phase to 16 for uplink 17
08:39:50:setup_element:INFO: Setting the data phase to 20 for uplink 18
08:39:50:setup_element:INFO: Setting the data phase to 18 for uplink 19
08:39:50:setup_element:INFO: Setting the data phase to 21 for uplink 20
08:39:50:setup_element:INFO: Setting the data phase to 20 for uplink 21
08:39:50:setup_element:INFO: Setting the data phase to 19 for uplink 22
08:39:50:setup_element:INFO: Setting the data phase to 20 for uplink 23
08:39:50:setup_element:INFO: Setting the data phase to 30 for uplink 24
08:39:50:setup_element:INFO: Setting the data phase to 32 for uplink 25
08:39:50:setup_element:INFO: Setting the data phase to 29 for uplink 26
08:39:50:setup_element:INFO: Setting the data phase to 32 for uplink 27
08:39:50:setup_element:INFO: Setting the data phase to 33 for uplink 28
08:39:50:setup_element:INFO: Setting the data phase to 36 for uplink 29
08:39:50:setup_element:INFO: Setting the data phase to 39 for uplink 30
08:39:50:setup_element:INFO: Setting the data phase to 39 for uplink 31
==============================================OOO==============================================
08:39:50:setup_element:INFO: Beginning SMX ASICs map scan
08:39:50:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:39:50:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:39:50:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
08:39:50:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
08:39:50:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
08:39:50:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
08:39:50:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
08:39:50:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
08:39:50:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
08:39:50:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
08:39:50:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
08:39:50:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
08:39:50:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
08:39:51:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
08:39:51:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
08:39:51:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
08:39:51:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
08:39:51:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
08:39:51:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
08:39:51:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
08:39:51:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
08:39:52:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 32
Window Length: 70
Eye Windows:
Uplink 16: _____________________________________________________________________XXXXXXX____
Uplink 17: _____________________________________________________________________XXXXXXX____
Uplink 18: _____________________________________________________________________XXXXXXXXX__
Uplink 19: _____________________________________________________________________XXXXXXXXX__
Uplink 20: ________________________________________________________________________________
Uplink 21: ________________________________________________________________________________
Uplink 22: _____________________________________________________________________XXXXXXXX___
Uplink 23: _____________________________________________________________________XXXXXXXX___
Uplink 24: ____________________________________________________________________XXXXXXXXX___
Uplink 25: ____________________________________________________________________XXXXXXXXX___
Uplink 26: ________________________________________________________________________________
Uplink 27: ________________________________________________________________________________
Uplink 28: ____________________________________________________________________XXXXXXXXX___
Uplink 29: ____________________________________________________________________XXXXXXXXX___
Uplink 30: _____________________________________________________________________XXXXXXXXX__
Uplink 31: _____________________________________________________________________XXXXXXXXX__
Data phase characteristics:
Uplink 16:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 17:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 18:
Optimal Phase: 20
Window Length: 33
Eye Window: XXXX_________________________________XXX
Uplink 19:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 20:
Optimal Phase: 21
Window Length: 35
Eye Window: XXXX___________________________________X
Uplink 21:
Optimal Phase: 20
Window Length: 33
Eye Window: XXXX_________________________________XXX
Uplink 22:
Optimal Phase: 19
Window Length: 33
Eye Window: XXX_________________________________XXXX
Uplink 23:
Optimal Phase: 20
Window Length: 29
Eye Window: XXXXXX_____________________________XXXXX
Uplink 24:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 25:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 26:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 27:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 28:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 29:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 30:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
Uplink 31:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
==============================================OOO==============================================
08:39:52:setup_element:INFO: Performing Elink synchronization
08:39:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
08:39:53:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:39:53:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
08:39:53:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
08:39:53:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
08:39:53:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 2 | 0 | [23] | 2 | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | 2 | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | 2 | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | 2 | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)]
|_________________________________________________________________________|
08:39:53:febtest:INFO: Init all SMX (CSA): 30
08:40:08:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:40:08:febtest:INFO: 23-00 | XA-000-09-004-007-014-007-07 | 34.6 | 1171.5
08:40:08:febtest:INFO: 30-01 | XA-000-09-004-007-014-010-07 | 37.7 | 1165.6
08:40:09:febtest:INFO: 21-02 | XA-000-09-004-007-016-023-05 | 40.9 | 1141.9
08:40:09:febtest:INFO: 28-03 | XA-000-09-004-007-013-012-09 | 37.7 | 1159.7
08:40:09:febtest:INFO: 19-04 | XA-000-09-004-007-013-005-09 | 28.2 | 1183.3
08:40:09:febtest:INFO: 26-05 | XA-000-09-004-007-014-012-07 | 34.6 | 1165.6
08:40:09:febtest:INFO: 17-06 | XA-000-09-004-007-013-006-09 | 34.6 | 1165.6
08:40:10:febtest:INFO: 24-07 | XA-000-09-004-007-015-011-10 | 34.6 | 1165.6
08:40:11:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
08:40:13:ST3_smx:INFO: chip: 23-0 37.726682 C 1183.292940 mV
08:40:13:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:40:13:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:40:13:ST3_smx:INFO: Electrons
08:40:13:ST3_smx:INFO: # loops 0
08:40:14:ST3_smx:INFO: # loops 1
08:40:16:ST3_smx:INFO: # loops 2
08:40:18:ST3_smx:INFO: # loops 3
08:40:19:ST3_smx:INFO: # loops 4
08:40:21:ST3_smx:INFO: Total # of broken channels: 0
08:40:21:ST3_smx:INFO: List of broken channels: []
08:40:21:ST3_smx:INFO: Total # of broken channels: 0
08:40:21:ST3_smx:INFO: List of broken channels: []
08:40:23:ST3_smx:INFO: chip: 30-1 37.726682 C 1183.292940 mV
08:40:23:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:40:23:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:40:23:ST3_smx:INFO: Electrons
08:40:23:ST3_smx:INFO: # loops 0
08:40:24:ST3_smx:INFO: # loops 1
08:40:26:ST3_smx:INFO: # loops 2
08:40:28:ST3_smx:INFO: # loops 3
08:40:29:ST3_smx:INFO: # loops 4
08:40:31:ST3_smx:INFO: Total # of broken channels: 2
08:40:31:ST3_smx:INFO: List of broken channels: [1, 3]
08:40:31:ST3_smx:INFO: Total # of broken channels: 4
08:40:31:ST3_smx:INFO: List of broken channels: [1, 3, 11, 25]
08:40:33:ST3_smx:INFO: chip: 21-2 40.898880 C 1153.732915 mV
08:40:33:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:40:33:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:40:33:ST3_smx:INFO: Electrons
08:40:33:ST3_smx:INFO: # loops 0
08:40:34:ST3_smx:INFO: # loops 1
08:40:36:ST3_smx:INFO: # loops 2
08:40:37:ST3_smx:INFO: # loops 3
08:40:39:ST3_smx:INFO: # loops 4
08:40:41:ST3_smx:INFO: Total # of broken channels: 0
08:40:41:ST3_smx:INFO: List of broken channels: []
08:40:41:ST3_smx:INFO: Total # of broken channels: 0
08:40:41:ST3_smx:INFO: List of broken channels: []
08:40:42:ST3_smx:INFO: chip: 28-3 37.726682 C 1171.483840 mV
08:40:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:40:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:40:42:ST3_smx:INFO: Electrons
08:40:42:ST3_smx:INFO: # loops 0
08:40:44:ST3_smx:INFO: # loops 1
08:40:46:ST3_smx:INFO: # loops 2
08:40:47:ST3_smx:INFO: # loops 3
08:40:49:ST3_smx:INFO: # loops 4
08:40:50:ST3_smx:INFO: Total # of broken channels: 0
08:40:50:ST3_smx:INFO: List of broken channels: []
08:40:50:ST3_smx:INFO: Total # of broken channels: 2
08:40:50:ST3_smx:INFO: List of broken channels: [31, 54]
08:40:52:ST3_smx:INFO: chip: 19-4 28.225000 C 1195.082160 mV
08:40:52:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:40:52:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:40:52:ST3_smx:INFO: Electrons
08:40:52:ST3_smx:INFO: # loops 0
08:40:54:ST3_smx:INFO: # loops 1
08:40:56:ST3_smx:INFO: # loops 2
08:40:57:ST3_smx:INFO: # loops 3
08:40:59:ST3_smx:INFO: # loops 4
08:41:01:ST3_smx:INFO: Total # of broken channels: 0
08:41:01:ST3_smx:INFO: List of broken channels: []
08:41:01:ST3_smx:INFO: Total # of broken channels: 0
08:41:01:ST3_smx:INFO: List of broken channels: []
08:41:02:ST3_smx:INFO: chip: 26-5 37.726682 C 1177.390875 mV
08:41:02:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:41:02:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:41:02:ST3_smx:INFO: Electrons
08:41:02:ST3_smx:INFO: # loops 0
08:41:04:ST3_smx:INFO: # loops 1
08:41:06:ST3_smx:INFO: # loops 2
08:41:07:ST3_smx:INFO: # loops 3
08:41:09:ST3_smx:INFO: # loops 4
08:41:10:ST3_smx:INFO: Total # of broken channels: 0
08:41:10:ST3_smx:INFO: List of broken channels: []
08:41:10:ST3_smx:INFO: Total # of broken channels: 0
08:41:10:ST3_smx:INFO: List of broken channels: []
08:41:12:ST3_smx:INFO: chip: 17-6 37.726682 C 1171.483840 mV
08:41:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:41:12:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:41:12:ST3_smx:INFO: Electrons
08:41:12:ST3_smx:INFO: # loops 0
08:41:14:ST3_smx:INFO: # loops 1
08:41:15:ST3_smx:INFO: # loops 2
08:41:17:ST3_smx:INFO: # loops 3
08:41:19:ST3_smx:INFO: # loops 4
08:41:20:ST3_smx:INFO: Total # of broken channels: 0
08:41:20:ST3_smx:INFO: List of broken channels: []
08:41:20:ST3_smx:INFO: Total # of broken channels: 0
08:41:20:ST3_smx:INFO: List of broken channels: []
08:41:22:ST3_smx:INFO: chip: 24-7 34.556970 C 1171.483840 mV
08:41:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:41:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
08:41:22:ST3_smx:INFO: Electrons
08:41:22:ST3_smx:INFO: # loops 0
08:41:24:ST3_smx:INFO: # loops 1
08:41:25:ST3_smx:INFO: # loops 2
08:41:27:ST3_smx:INFO: # loops 3
08:41:28:ST3_smx:INFO: # loops 4
08:41:30:ST3_smx:INFO: Total # of broken channels: 0
08:41:30:ST3_smx:INFO: List of broken channels: []
08:41:30:ST3_smx:INFO: Total # of broken channels: 0
08:41:30:ST3_smx:INFO: List of broken channels: []
08:41:30:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:41:31:febtest:INFO: 23-00 | XA-000-09-004-007-014-007-07 | 40.9 | 1201.0
08:41:31:febtest:INFO: 30-01 | XA-000-09-004-007-014-010-07 | 40.9 | 1201.0
08:41:31:febtest:INFO: 21-02 | XA-000-09-004-007-016-023-05 | 44.1 | 1171.5
08:41:31:febtest:INFO: 28-03 | XA-000-09-004-007-013-012-09 | 40.9 | 1195.1
08:41:31:febtest:INFO: 19-04 | XA-000-09-004-007-013-005-09 | 31.4 | 1212.7
08:41:32:febtest:INFO: 26-05 | XA-000-09-004-007-014-012-07 | 37.7 | 1195.1
08:41:32:febtest:INFO: 17-06 | XA-000-09-004-007-013-006-09 | 37.7 | 1195.1
08:41:32:febtest:INFO: 24-07 | XA-000-09-004-007-015-011-10 | 37.7 | 1195.1
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_12_11-08_39_28
OPERATOR : Kerstin S.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2314| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
SENSOR_NAME: 22373 | SIZE: 62x62 | GRADE: A
MODULE_NAME: M3DR4B2000132A2
LADDER_NAME: L3DR400013
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.4870', '1.848', '2.1640']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0310', '1.850', '2.6210']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9850', '1.850', '0.5332']