14:17:57:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:17:57:ST3_Shared:INFO:	                       FEB-Microcable                       
14:17:57:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:17:59:ST3_Shared:INFO:	STS mode selected
14:17:59:febtest:INFO:	Testing FEB with SN 2317
14:18:01:smx_tester:INFO:	Scanning setup
14:18:01:elinks:INFO:	Disabling clock on downlink 0
14:18:01:elinks:INFO:	Disabling clock on downlink 1
14:18:01:elinks:INFO:	Disabling clock on downlink 2
14:18:01:elinks:INFO:	Disabling clock on downlink 3
14:18:01:elinks:INFO:	Disabling clock on downlink 4
14:18:01:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:18:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
14:18:01:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:18:01:elinks:INFO:	Disabling clock on downlink 0
14:18:01:elinks:INFO:	Disabling clock on downlink 1
14:18:01:elinks:INFO:	Disabling clock on downlink 2
14:18:01:elinks:INFO:	Disabling clock on downlink 3
14:18:01:elinks:INFO:	Disabling clock on downlink 4
14:18:01:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:18:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:18:01:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:18:01:elinks:INFO:	Disabling clock on downlink 0
14:18:01:elinks:INFO:	Disabling clock on downlink 1
14:18:01:elinks:INFO:	Disabling clock on downlink 2
14:18:01:elinks:INFO:	Disabling clock on downlink 3
14:18:01:elinks:INFO:	Disabling clock on downlink 4
14:18:01:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:18:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:18:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 16
14:18:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 17
14:18:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 18
14:18:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 19
14:18:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 20
14:18:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 21
14:18:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 22
14:18:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 23
14:18:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
14:18:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
14:18:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
14:18:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
14:18:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
14:18:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
14:18:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
14:18:01:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
14:18:01:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:18:01:elinks:INFO:	Disabling clock on downlink 0
14:18:01:elinks:INFO:	Disabling clock on downlink 1
14:18:01:elinks:INFO:	Disabling clock on downlink 2
14:18:01:elinks:INFO:	Disabling clock on downlink 3
14:18:01:elinks:INFO:	Disabling clock on downlink 4
14:18:01:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:18:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
14:18:01:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:18:01:elinks:INFO:	Disabling clock on downlink 0
14:18:01:elinks:INFO:	Disabling clock on downlink 1
14:18:01:elinks:INFO:	Disabling clock on downlink 2
14:18:01:elinks:INFO:	Disabling clock on downlink 3
14:18:01:elinks:INFO:	Disabling clock on downlink 4
14:18:01:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:18:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
14:18:02:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
14:18:02:setup_element:INFO:	Scanning clock phase
14:18:02:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:18:02:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:18:02:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
14:18:02:setup_element:INFO:	Eye window for uplink 16: __________________________________________________________________XXXXXXXXX_____
Clock Delay: 30
14:18:02:setup_element:INFO:	Eye window for uplink 17: __________________________________________________________________XXXXXXXXX_____
Clock Delay: 30
14:18:02:setup_element:INFO:	Eye window for uplink 18: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
14:18:02:setup_element:INFO:	Eye window for uplink 19: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
14:18:02:setup_element:INFO:	Eye window for uplink 20: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
14:18:02:setup_element:INFO:	Eye window for uplink 21: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
14:18:02:setup_element:INFO:	Eye window for uplink 22: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
14:18:02:setup_element:INFO:	Eye window for uplink 23: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
14:18:02:setup_element:INFO:	Eye window for uplink 24: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
14:18:02:setup_element:INFO:	Eye window for uplink 25: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
14:18:02:setup_element:INFO:	Eye window for uplink 26: __________________________________________________________________XXXXXXXXX_____
Clock Delay: 30
14:18:02:setup_element:INFO:	Eye window for uplink 27: __________________________________________________________________XXXXXXXXX_____
Clock Delay: 30
14:18:02:setup_element:INFO:	Eye window for uplink 28: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
14:18:02:setup_element:INFO:	Eye window for uplink 29: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
14:18:02:setup_element:INFO:	Eye window for uplink 30: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
14:18:02:setup_element:INFO:	Eye window for uplink 31: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
14:18:02:setup_element:INFO:	Setting the clock phase to 30 for group 0, downlink 2
==============================================OOO==============================================
14:18:02:setup_element:INFO:	Scanning data phases
14:18:02:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:18:02:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:18:08:setup_element:INFO:	Data phase scan results for group 0, downlink 2
14:18:08:setup_element:INFO:	Eye window for uplink 16: XXXXX________________________________XXX
Data delay found: 20
14:18:08:setup_element:INFO:	Eye window for uplink 17: XXX______________________________X_XXXXX
Data delay found: 17
14:18:08:setup_element:INFO:	Eye window for uplink 18: XXXXX________________________________XXX
Data delay found: 20
14:18:08:setup_element:INFO:	Eye window for uplink 19: XXXX_______________________________XXXXX
Data delay found: 19
14:18:08:setup_element:INFO:	Eye window for uplink 20: _________________________________XXXXXXX
Data delay found: 16
14:18:08:setup_element:INFO:	Eye window for uplink 21: ________________________________XXXXXXXX
Data delay found: 15
14:18:08:setup_element:INFO:	Eye window for uplink 22: XXXXXX_______________________________XXX
Data delay found: 21
14:18:08:setup_element:INFO:	Eye window for uplink 23: XXXXXXXX_____________________________XXX
Data delay found: 22
14:18:08:setup_element:INFO:	Eye window for uplink 24: _____X_XXXXXXX__________________________
Data delay found: 29
14:18:08:setup_element:INFO:	Eye window for uplink 25: _______XXXXXXXXX________________________
Data delay found: 31
14:18:08:setup_element:INFO:	Eye window for uplink 26: _____XXXXXXXXXX_________________________
Data delay found: 29
14:18:08:setup_element:INFO:	Eye window for uplink 27: ________XXXXXXXXXXX_____________________
Data delay found: 33
14:18:08:setup_element:INFO:	Eye window for uplink 28: __________XXXXXXXXXX____________________
Data delay found: 34
14:18:08:setup_element:INFO:	Eye window for uplink 29: ____________XXXXXXXXXXXX________________
Data delay found: 37
14:18:08:setup_element:INFO:	Eye window for uplink 30: ____________XXXXXXXXXXXXX_______________
Data delay found: 38
14:18:08:setup_element:INFO:	Eye window for uplink 31: ____________XXXXXXXXXXXXX_______________
Data delay found: 38
14:18:08:setup_element:INFO:	Setting the data phase to 20 for uplink 16
14:18:08:setup_element:INFO:	Setting the data phase to 17 for uplink 17
14:18:08:setup_element:INFO:	Setting the data phase to 20 for uplink 18
14:18:08:setup_element:INFO:	Setting the data phase to 19 for uplink 19
14:18:08:setup_element:INFO:	Setting the data phase to 16 for uplink 20
14:18:08:setup_element:INFO:	Setting the data phase to 15 for uplink 21
14:18:08:setup_element:INFO:	Setting the data phase to 21 for uplink 22
14:18:08:setup_element:INFO:	Setting the data phase to 22 for uplink 23
14:18:08:setup_element:INFO:	Setting the data phase to 29 for uplink 24
14:18:08:setup_element:INFO:	Setting the data phase to 31 for uplink 25
14:18:08:setup_element:INFO:	Setting the data phase to 29 for uplink 26
14:18:08:setup_element:INFO:	Setting the data phase to 33 for uplink 27
14:18:08:setup_element:INFO:	Setting the data phase to 34 for uplink 28
14:18:08:setup_element:INFO:	Setting the data phase to 37 for uplink 29
14:18:08:setup_element:INFO:	Setting the data phase to 38 for uplink 30
14:18:08:setup_element:INFO:	Setting the data phase to 38 for uplink 31
==============================================OOO==============================================
14:18:08:setup_element:INFO:	Beginning SMX ASICs map scan
14:18:08:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:18:08:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:18:08:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
14:18:08:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
14:18:08:uplink:INFO:	Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
14:18:08:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 23
14:18:08:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 22
14:18:08:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
14:18:08:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
14:18:08:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 21
14:18:08:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 20
14:18:08:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
14:18:08:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
14:18:09:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 19
14:18:09:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 18
14:18:09:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
14:18:09:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
14:18:09:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 17
14:18:09:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 16
14:18:09:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
14:18:09:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
14:18:11:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 30
    Window Length: 69
    Eye Windows:
      Uplink 16: __________________________________________________________________XXXXXXXXX_____
      Uplink 17: __________________________________________________________________XXXXXXXXX_____
      Uplink 18: ___________________________________________________________________XXXXXXXXX____
      Uplink 19: ___________________________________________________________________XXXXXXXXX____
      Uplink 20: _________________________________________________________________XXXXXXXXX______
      Uplink 21: _________________________________________________________________XXXXXXXXX______
      Uplink 22: ___________________________________________________________________XXXXXXXXX____
      Uplink 23: ___________________________________________________________________XXXXXXXXX____
      Uplink 24: _________________________________________________________________XXXXXXXXX______
      Uplink 25: _________________________________________________________________XXXXXXXXX______
      Uplink 26: __________________________________________________________________XXXXXXXXX_____
      Uplink 27: __________________________________________________________________XXXXXXXXX_____
      Uplink 28: ___________________________________________________________________XXXXXXXX_____
      Uplink 29: ___________________________________________________________________XXXXXXXX_____
      Uplink 30: ____________________________________________________________________XXXXXXXX____
      Uplink 31: ____________________________________________________________________XXXXXXXX____
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 20
      Window Length: 32
      Eye Window: XXXXX________________________________XXX
    Uplink 17:
      Optimal Phase: 17
      Window Length: 30
      Eye Window: XXX______________________________X_XXXXX
    Uplink 18:
      Optimal Phase: 20
      Window Length: 32
      Eye Window: XXXXX________________________________XXX
    Uplink 19:
      Optimal Phase: 19
      Window Length: 31
      Eye Window: XXXX_______________________________XXXXX
    Uplink 20:
      Optimal Phase: 16
      Window Length: 33
      Eye Window: _________________________________XXXXXXX
    Uplink 21:
      Optimal Phase: 15
      Window Length: 32
      Eye Window: ________________________________XXXXXXXX
    Uplink 22:
      Optimal Phase: 21
      Window Length: 31
      Eye Window: XXXXXX_______________________________XXX
    Uplink 23:
      Optimal Phase: 22
      Window Length: 29
      Eye Window: XXXXXXXX_____________________________XXX
    Uplink 24:
      Optimal Phase: 29
      Window Length: 31
      Eye Window: _____X_XXXXXXX__________________________
    Uplink 25:
      Optimal Phase: 31
      Window Length: 31
      Eye Window: _______XXXXXXXXX________________________
    Uplink 26:
      Optimal Phase: 29
      Window Length: 30
      Eye Window: _____XXXXXXXXXX_________________________
    Uplink 27:
      Optimal Phase: 33
      Window Length: 29
      Eye Window: ________XXXXXXXXXXX_____________________
    Uplink 28:
      Optimal Phase: 34
      Window Length: 30
      Eye Window: __________XXXXXXXXXX____________________
    Uplink 29:
      Optimal Phase: 37
      Window Length: 28
      Eye Window: ____________XXXXXXXXXXXX________________
    Uplink 30:
      Optimal Phase: 38
      Window Length: 27
      Eye Window: ____________XXXXXXXXXXXXX_______________
    Uplink 31:
      Optimal Phase: 38
      Window Length: 27
      Eye Window: ____________XXXXXXXXXXXXX_______________

==============================================OOO==============================================
14:18:11:setup_element:INFO:	Performing Elink synchronization
14:18:11:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:18:11:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:18:11:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
14:18:11:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
14:18:11:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
14:18:11:uplink:INFO:	Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 0   | [0]  |   2   |  0  |  [23]   |    2    | [(0, 23), (1, 22)]
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 2   | [0]  |   2   |  0  |  [21]   |    2    | [(0, 21), (1, 20)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 4   | [0]  |   2   |  0  |  [19]   |    2    | [(0, 19), (1, 18)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 6   | [0]  |   2   |  0  |  [17]   |    2    | [(0, 17), (1, 16)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
14:18:11:febtest:INFO:	Init all SMX (CSA): 30
14:18:25:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:18:25:febtest:INFO:	23-00 | XA-000-09-004-012-004-023-01 |  44.1 | 1106.2
14:18:25:febtest:INFO:	30-01 | XA-000-09-004-012-006-019-02 |  31.4 | 1141.9
14:18:26:febtest:INFO:	21-02 | XA-000-09-004-012-006-021-02 |  28.2 | 1159.7
14:18:26:febtest:INFO:	28-03 | XA-000-09-004-012-004-021-01 |  21.9 | 1171.5
14:18:26:febtest:INFO:	19-04 | XA-000-09-004-012-004-022-01 |  34.6 | 1141.9
14:18:26:febtest:INFO:	26-05 | XA-000-09-004-012-005-021-12 |  28.2 | 1141.9
14:18:27:febtest:INFO:	17-06 | XA-000-09-004-012-006-023-02 |  28.2 | 1159.7
14:18:27:febtest:INFO:	24-07 | XA-000-09-004-012-006-020-02 |  37.7 | 1130.0
14:18:28:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
14:18:30:ST3_smx:INFO:	chip: 23-0 	 44.073563 C 	 1118.096875 mV
14:18:30:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:18:30:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:18:30:ST3_smx:INFO:		Electrons
14:18:30:ST3_smx:INFO:	# loops 0
14:18:31:ST3_smx:INFO:	# loops 1
14:18:33:ST3_smx:INFO:	# loops 2
14:18:34:ST3_smx:INFO:	Total # of broken channels: 0
14:18:34:ST3_smx:INFO:	List of broken channels: []
14:18:34:ST3_smx:INFO:	Total # of broken channels: 1
14:18:34:ST3_smx:INFO:	List of broken channels: [110]
14:18:36:ST3_smx:INFO:	chip: 30-1 	 31.389742 C 	 1153.732915 mV
14:18:36:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:18:36:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:18:36:ST3_smx:INFO:		Electrons
14:18:36:ST3_smx:INFO:	# loops 0
14:18:38:ST3_smx:INFO:	# loops 1
14:18:40:ST3_smx:INFO:	# loops 2
14:18:41:ST3_smx:INFO:	Total # of broken channels: 1
14:18:41:ST3_smx:INFO:	List of broken channels: [90]
14:18:41:ST3_smx:INFO:	Total # of broken channels: 0
14:18:41:ST3_smx:INFO:	List of broken channels: []
14:18:43:ST3_smx:INFO:	chip: 21-2 	 28.225000 C 	 1171.483840 mV
14:18:43:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:18:43:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:18:43:ST3_smx:INFO:		Electrons
14:18:43:ST3_smx:INFO:	# loops 0
14:18:45:ST3_smx:INFO:	# loops 1
14:18:46:ST3_smx:INFO:	# loops 2
14:18:48:ST3_smx:INFO:	Total # of broken channels: 0
14:18:48:ST3_smx:INFO:	List of broken channels: []
14:18:48:ST3_smx:INFO:	Total # of broken channels: 1
14:18:48:ST3_smx:INFO:	List of broken channels: [103]
14:18:50:ST3_smx:INFO:	chip: 28-3 	 21.902970 C 	 1189.190035 mV
14:18:50:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:18:50:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:18:50:ST3_smx:INFO:		Electrons
14:18:50:ST3_smx:INFO:	# loops 0
14:18:51:ST3_smx:INFO:	# loops 1
14:18:53:ST3_smx:INFO:	# loops 2
14:18:54:ST3_smx:INFO:	Total # of broken channels: 0
14:18:54:ST3_smx:INFO:	List of broken channels: []
14:18:54:ST3_smx:INFO:	Total # of broken channels: 0
14:18:54:ST3_smx:INFO:	List of broken channels: []
14:18:56:ST3_smx:INFO:	chip: 19-4 	 31.389742 C 	 1153.732915 mV
14:18:56:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:18:56:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:18:56:ST3_smx:INFO:		Electrons
14:18:56:ST3_smx:INFO:	# loops 0
14:18:58:ST3_smx:INFO:	# loops 1
14:18:59:ST3_smx:INFO:	# loops 2
14:19:01:ST3_smx:INFO:	Total # of broken channels: 0
14:19:01:ST3_smx:INFO:	List of broken channels: []
14:19:01:ST3_smx:INFO:	Total # of broken channels: 0
14:19:01:ST3_smx:INFO:	List of broken channels: []
14:19:02:ST3_smx:INFO:	chip: 26-5 	 31.389742 C 	 1153.732915 mV
14:19:02:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:19:02:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:19:02:ST3_smx:INFO:		Electrons
14:19:02:ST3_smx:INFO:	# loops 0
14:19:04:ST3_smx:INFO:	# loops 1
14:19:06:ST3_smx:INFO:	# loops 2
14:19:07:ST3_smx:INFO:	Total # of broken channels: 0
14:19:07:ST3_smx:INFO:	List of broken channels: []
14:19:07:ST3_smx:INFO:	Total # of broken channels: 0
14:19:07:ST3_smx:INFO:	List of broken channels: []
14:19:09:ST3_smx:INFO:	chip: 17-6 	 28.225000 C 	 1165.571835 mV
14:19:09:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:19:09:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:19:09:ST3_smx:INFO:		Electrons
14:19:09:ST3_smx:INFO:	# loops 0
14:19:10:ST3_smx:INFO:	# loops 1
14:19:12:ST3_smx:INFO:	# loops 2
14:19:13:ST3_smx:INFO:	Total # of broken channels: 0
14:19:13:ST3_smx:INFO:	List of broken channels: []
14:19:13:ST3_smx:INFO:	Total # of broken channels: 2
14:19:13:ST3_smx:INFO:	List of broken channels: [125, 127]
14:19:15:ST3_smx:INFO:	chip: 24-7 	 37.726682 C 	 1135.937260 mV
14:19:15:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:19:15:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:19:15:ST3_smx:INFO:		Electrons
14:19:15:ST3_smx:INFO:	# loops 0
14:19:17:ST3_smx:INFO:	# loops 1
14:19:18:ST3_smx:INFO:	# loops 2
14:19:20:ST3_smx:INFO:	Total # of broken channels: 0
14:19:20:ST3_smx:INFO:	List of broken channels: []
14:19:20:ST3_smx:INFO:	Total # of broken channels: 0
14:19:20:ST3_smx:INFO:	List of broken channels: []
14:19:20:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:19:20:febtest:INFO:	23-00 | XA-000-09-004-012-004-023-01 |  44.1 | 1141.9
14:19:21:febtest:INFO:	30-01 | XA-000-09-004-012-006-019-02 |  31.4 | 1177.4
14:19:21:febtest:INFO:	21-02 | XA-000-09-004-012-006-021-02 |  28.2 | 1189.2
14:19:21:febtest:INFO:	28-03 | XA-000-09-004-012-004-021-01 |  21.9 | 1206.9
14:19:21:febtest:INFO:	19-04 | XA-000-09-004-012-004-022-01 |  34.6 | 1183.3
14:19:21:febtest:INFO:	26-05 | XA-000-09-004-012-005-021-12 |  31.4 | 1177.4
14:19:22:febtest:INFO:	17-06 | XA-000-09-004-012-006-023-02 |  28.2 | 1183.3
14:19:22:febtest:INFO:	24-07 | XA-000-09-004-012-006-020-02 |  37.7 | 1153.7
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_12_19-14_17_57
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2317| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.7070', '1.851', '2.5480']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0020', '1.850', '2.6000']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9660', '1.850', '0.5230']
14:19:23:ST3_Shared:INFO:	Listo of operators:Oleksandr S.; Robert V.; 
14:19:26:ST3_Shared:INFO:	Listo of operators:Robert V.;