14:13:06:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:13:06:ST3_Shared:INFO:	                       FEB-Microcable                       
14:13:06:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:13:06:febtest:INFO:	Testing FEB with SN 2334
14:13:08:smx_tester:INFO:	Scanning setup
14:13:08:elinks:INFO:	Disabling clock on downlink 0
14:13:08:elinks:INFO:	Disabling clock on downlink 1
14:13:08:elinks:INFO:	Disabling clock on downlink 2
14:13:08:elinks:INFO:	Disabling clock on downlink 3
14:13:08:elinks:INFO:	Disabling clock on downlink 4
14:13:08:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:13:08:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
14:13:08:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:13:08:elinks:INFO:	Disabling clock on downlink 0
14:13:08:elinks:INFO:	Disabling clock on downlink 1
14:13:08:elinks:INFO:	Disabling clock on downlink 2
14:13:08:elinks:INFO:	Disabling clock on downlink 3
14:13:08:elinks:INFO:	Disabling clock on downlink 4
14:13:08:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:13:08:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:13:08:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:13:08:elinks:INFO:	Disabling clock on downlink 0
14:13:08:elinks:INFO:	Disabling clock on downlink 1
14:13:08:elinks:INFO:	Disabling clock on downlink 2
14:13:08:elinks:INFO:	Disabling clock on downlink 3
14:13:08:elinks:INFO:	Disabling clock on downlink 4
14:13:08:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:13:08:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:13:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 16
14:13:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 17
14:13:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 18
14:13:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 19
14:13:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 20
14:13:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 21
14:13:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 22
14:13:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 23
14:13:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
14:13:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
14:13:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
14:13:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
14:13:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
14:13:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
14:13:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
14:13:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
14:13:09:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:13:09:elinks:INFO:	Disabling clock on downlink 0
14:13:09:elinks:INFO:	Disabling clock on downlink 1
14:13:09:elinks:INFO:	Disabling clock on downlink 2
14:13:09:elinks:INFO:	Disabling clock on downlink 3
14:13:09:elinks:INFO:	Disabling clock on downlink 4
14:13:09:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:13:09:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
14:13:09:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:13:09:elinks:INFO:	Disabling clock on downlink 0
14:13:09:elinks:INFO:	Disabling clock on downlink 1
14:13:09:elinks:INFO:	Disabling clock on downlink 2
14:13:09:elinks:INFO:	Disabling clock on downlink 3
14:13:09:elinks:INFO:	Disabling clock on downlink 4
14:13:09:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:13:09:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
14:13:09:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
14:13:09:setup_element:INFO:	Scanning clock phase
14:13:09:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:13:09:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:13:09:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
14:13:09:setup_element:INFO:	Eye window for uplink 16: X_________________________________________________________________________XXXXXX
Clock Delay: 37
14:13:09:setup_element:INFO:	Eye window for uplink 17: X_________________________________________________________________________XXXXXX
Clock Delay: 37
14:13:09:setup_element:INFO:	Eye window for uplink 18: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
14:13:09:setup_element:INFO:	Eye window for uplink 19: ________________________________________________________________________XXXXXXX_
Clock Delay: 35
14:13:09:setup_element:INFO:	Eye window for uplink 20: _________________________________________________________________________XXXXXXX
Clock Delay: 36
14:13:09:setup_element:INFO:	Eye window for uplink 21: _________________________________________________________________________XXXXXXX
Clock Delay: 36
14:13:09:setup_element:INFO:	Eye window for uplink 22: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
14:13:09:setup_element:INFO:	Eye window for uplink 23: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
14:13:09:setup_element:INFO:	Eye window for uplink 24: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
14:13:09:setup_element:INFO:	Eye window for uplink 25: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
14:13:09:setup_element:INFO:	Eye window for uplink 26: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
14:13:09:setup_element:INFO:	Eye window for uplink 27: ________________________________________________________________________XXXXXXXX
Clock Delay: 35
14:13:09:setup_element:INFO:	Eye window for uplink 28: __________________________________________________________________________XXXXXX
Clock Delay: 36
14:13:09:setup_element:INFO:	Eye window for uplink 29: __________________________________________________________________________XXXXXX
Clock Delay: 36
14:13:09:setup_element:INFO:	Eye window for uplink 30: X__________________________________________________________________________XXXXX
Clock Delay: 37
14:13:09:setup_element:INFO:	Eye window for uplink 31: X__________________________________________________________________________XXXXX
Clock Delay: 37
14:13:09:setup_element:INFO:	Setting the clock phase to 36 for group 0, downlink 2
==============================================OOO==============================================
14:13:09:setup_element:INFO:	Scanning data phases
14:13:09:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:13:09:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:13:14:setup_element:INFO:	Data phase scan results for group 0, downlink 2
14:13:14:setup_element:INFO:	Eye window for uplink 16: XXX________________________________XXXXX
Data delay found: 18
14:13:14:setup_element:INFO:	Eye window for uplink 17: _________________________________XXXXXX_
Data delay found: 15
14:13:14:setup_element:INFO:	Eye window for uplink 18: _________________________________XXXX___
Data delay found: 14
14:13:14:setup_element:INFO:	Eye window for uplink 19: ________________________________XXXXX___
Data delay found: 14
14:13:14:setup_element:INFO:	Eye window for uplink 20: _________________________________XXXXXXX
Data delay found: 16
14:13:14:setup_element:INFO:	Eye window for uplink 21: _________________________________XXXXXX_
Data delay found: 15
14:13:14:setup_element:INFO:	Eye window for uplink 22: __________________________________XXXXX_
Data delay found: 16
14:13:14:setup_element:INFO:	Eye window for uplink 23: ________________________________XXXXX___
Data delay found: 14
14:13:14:setup_element:INFO:	Eye window for uplink 24: _____XXXX_______________________________
Data delay found: 26
14:13:14:setup_element:INFO:	Eye window for uplink 25: ______XXXXX_____________________________
Data delay found: 28
14:13:14:setup_element:INFO:	Eye window for uplink 26: ___XXXXXX_______________________________
Data delay found: 25
14:13:14:setup_element:INFO:	Eye window for uplink 27: _______XXXX_____________________________
Data delay found: 28
14:13:14:setup_element:INFO:	Eye window for uplink 28: ____________XXXXX_______________________
Data delay found: 34
14:13:14:setup_element:INFO:	Eye window for uplink 29: _____________XXXXXX_____________________
Data delay found: 35
14:13:14:setup_element:INFO:	Eye window for uplink 30: _______________XXXXXX___________________
Data delay found: 37
14:13:14:setup_element:INFO:	Eye window for uplink 31: _____________XXXXX______________________
Data delay found: 35
14:13:14:setup_element:INFO:	Setting the data phase to 18 for uplink 16
14:13:14:setup_element:INFO:	Setting the data phase to 15 for uplink 17
14:13:14:setup_element:INFO:	Setting the data phase to 14 for uplink 18
14:13:14:setup_element:INFO:	Setting the data phase to 14 for uplink 19
14:13:14:setup_element:INFO:	Setting the data phase to 16 for uplink 20
14:13:14:setup_element:INFO:	Setting the data phase to 15 for uplink 21
14:13:14:setup_element:INFO:	Setting the data phase to 16 for uplink 22
14:13:14:setup_element:INFO:	Setting the data phase to 14 for uplink 23
14:13:14:setup_element:INFO:	Setting the data phase to 26 for uplink 24
14:13:14:setup_element:INFO:	Setting the data phase to 28 for uplink 25
14:13:14:setup_element:INFO:	Setting the data phase to 25 for uplink 26
14:13:14:setup_element:INFO:	Setting the data phase to 28 for uplink 27
14:13:14:setup_element:INFO:	Setting the data phase to 34 for uplink 28
14:13:14:setup_element:INFO:	Setting the data phase to 35 for uplink 29
14:13:14:setup_element:INFO:	Setting the data phase to 37 for uplink 30
14:13:14:setup_element:INFO:	Setting the data phase to 35 for uplink 31
==============================================OOO==============================================
14:13:14:setup_element:INFO:	Beginning SMX ASICs map scan
14:13:14:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:13:14:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:13:14:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
14:13:14:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
14:13:14:uplink:INFO:	Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
14:13:14:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 23
14:13:14:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 22
14:13:15:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
14:13:15:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
14:13:15:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 21
14:13:15:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 20
14:13:15:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
14:13:15:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
14:13:15:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 19
14:13:15:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 18
14:13:15:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
14:13:15:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
14:13:15:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 17
14:13:15:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 16
14:13:16:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
14:13:16:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
14:13:17:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 36
    Window Length: 71
    Eye Windows:
      Uplink 16: X_________________________________________________________________________XXXXXX
      Uplink 17: X_________________________________________________________________________XXXXXX
      Uplink 18: ________________________________________________________________________XXXXXXX_
      Uplink 19: ________________________________________________________________________XXXXXXX_
      Uplink 20: _________________________________________________________________________XXXXXXX
      Uplink 21: _________________________________________________________________________XXXXXXX
      Uplink 22: ________________________________________________________________________XXXXXXXX
      Uplink 23: ________________________________________________________________________XXXXXXXX
      Uplink 24: ________________________________________________________________________XXXXXXXX
      Uplink 25: ________________________________________________________________________XXXXXXXX
      Uplink 26: ________________________________________________________________________XXXXXXXX
      Uplink 27: ________________________________________________________________________XXXXXXXX
      Uplink 28: __________________________________________________________________________XXXXXX
      Uplink 29: __________________________________________________________________________XXXXXX
      Uplink 30: X__________________________________________________________________________XXXXX
      Uplink 31: X__________________________________________________________________________XXXXX
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 18
      Window Length: 32
      Eye Window: XXX________________________________XXXXX
    Uplink 17:
      Optimal Phase: 15
      Window Length: 34
      Eye Window: _________________________________XXXXXX_
    Uplink 18:
      Optimal Phase: 14
      Window Length: 36
      Eye Window: _________________________________XXXX___
    Uplink 19:
      Optimal Phase: 14
      Window Length: 35
      Eye Window: ________________________________XXXXX___
    Uplink 20:
      Optimal Phase: 16
      Window Length: 33
      Eye Window: _________________________________XXXXXXX
    Uplink 21:
      Optimal Phase: 15
      Window Length: 34
      Eye Window: _________________________________XXXXXX_
    Uplink 22:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 23:
      Optimal Phase: 14
      Window Length: 35
      Eye Window: ________________________________XXXXX___
    Uplink 24:
      Optimal Phase: 26
      Window Length: 36
      Eye Window: _____XXXX_______________________________
    Uplink 25:
      Optimal Phase: 28
      Window Length: 35
      Eye Window: ______XXXXX_____________________________
    Uplink 26:
      Optimal Phase: 25
      Window Length: 34
      Eye Window: ___XXXXXX_______________________________
    Uplink 27:
      Optimal Phase: 28
      Window Length: 36
      Eye Window: _______XXXX_____________________________
    Uplink 28:
      Optimal Phase: 34
      Window Length: 35
      Eye Window: ____________XXXXX_______________________
    Uplink 29:
      Optimal Phase: 35
      Window Length: 34
      Eye Window: _____________XXXXXX_____________________
    Uplink 30:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 31:
      Optimal Phase: 35
      Window Length: 35
      Eye Window: _____________XXXXX______________________

==============================================OOO==============================================
14:13:17:setup_element:INFO:	Performing Elink synchronization
14:13:17:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:13:17:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:13:17:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
14:13:17:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
14:13:17:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
14:13:17:uplink:INFO:	Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 0   | [0]  |   2   |  0  |  [23]   |    2    | [(0, 23), (1, 22)]
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 2   | [0]  |   2   |  0  |  [21]   |    2    | [(0, 21), (1, 20)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 4   | [0]  |   2   |  0  |  [19]   |    2    | [(0, 19), (1, 18)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 6   | [0]  |   2   |  0  |  [17]   |    2    | [(0, 17), (1, 16)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
14:13:18:febtest:INFO:	Init all SMX (CSA): 30
14:13:33:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:13:33:febtest:INFO:	23-00 | XA-000-09-004-007-010-011-01 |  40.9 | 1159.7
14:13:33:febtest:INFO:	30-01 | XA-000-09-004-007-011-005-12 |  28.2 | 1189.2
14:13:34:febtest:INFO:	21-02 | XA-000-09-004-007-011-010-12 |  40.9 | 1159.7
14:13:34:febtest:INFO:	28-03 | XA-000-09-004-007-012-005-04 |  37.7 | 1153.7
14:13:34:febtest:INFO:	19-04 | XA-000-09-004-007-010-012-01 |  56.8 | 1094.2
14:13:34:febtest:INFO:	26-05 | XA-000-09-004-007-010-006-01 |  31.4 | 1171.5
14:13:35:febtest:INFO:	17-06 | XA-000-09-004-007-012-011-04 |  40.9 | 1165.6
14:13:35:febtest:INFO:	24-07 | XA-000-09-004-007-012-010-04 |  37.7 | 1153.7
14:13:36:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
14:13:38:ST3_smx:INFO:	chip: 23-0 	 37.726682 C 	 1171.483840 mV
14:13:38:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:13:38:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:13:38:ST3_smx:INFO:		Electrons
14:13:38:ST3_smx:INFO:	# loops 0
14:13:40:ST3_smx:INFO:	# loops 1
14:13:41:ST3_smx:INFO:	# loops 2
14:13:43:ST3_smx:INFO:	Total # of broken channels: 0
14:13:43:ST3_smx:INFO:	List of broken channels: []
14:13:43:ST3_smx:INFO:	Total # of broken channels: 5
14:13:43:ST3_smx:INFO:	List of broken channels: [2, 22, 24, 43, 46]
14:13:45:ST3_smx:INFO:	chip: 30-1 	 28.225000 C 	 1200.969315 mV
14:13:45:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:13:45:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:13:45:ST3_smx:INFO:		Electrons
14:13:45:ST3_smx:INFO:	# loops 0
14:13:47:ST3_smx:INFO:	# loops 1
14:13:48:ST3_smx:INFO:	# loops 2
14:13:50:ST3_smx:INFO:	Total # of broken channels: 0
14:13:50:ST3_smx:INFO:	List of broken channels: []
14:13:50:ST3_smx:INFO:	Total # of broken channels: 0
14:13:50:ST3_smx:INFO:	List of broken channels: []
14:13:52:ST3_smx:INFO:	chip: 21-2 	 40.898880 C 	 1171.483840 mV
14:13:52:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:13:52:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:13:52:ST3_smx:INFO:		Electrons
14:13:52:ST3_smx:INFO:	# loops 0
14:13:54:ST3_smx:INFO:	# loops 1
14:13:56:ST3_smx:INFO:	# loops 2
14:13:57:ST3_smx:INFO:	Total # of broken channels: 0
14:13:57:ST3_smx:INFO:	List of broken channels: []
14:13:57:ST3_smx:INFO:	Total # of broken channels: 0
14:13:57:ST3_smx:INFO:	List of broken channels: []
14:13:59:ST3_smx:INFO:	chip: 28-3 	 37.726682 C 	 1165.571835 mV
14:13:59:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:13:59:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:13:59:ST3_smx:INFO:		Electrons
14:13:59:ST3_smx:INFO:	# loops 0
14:14:01:ST3_smx:INFO:	# loops 1
14:14:03:ST3_smx:INFO:	# loops 2
14:14:04:ST3_smx:INFO:	Total # of broken channels: 0
14:14:04:ST3_smx:INFO:	List of broken channels: []
14:14:04:ST3_smx:INFO:	Total # of broken channels: 4
14:14:04:ST3_smx:INFO:	List of broken channels: [65, 67, 69, 126]
14:14:06:ST3_smx:INFO:	chip: 19-4 	 56.797143 C 	 1106.178435 mV
14:14:06:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:14:06:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:14:06:ST3_smx:INFO:		Electrons
14:14:06:ST3_smx:INFO:	# loops 0
14:14:08:ST3_smx:INFO:	# loops 1
14:14:10:ST3_smx:INFO:	# loops 2
14:14:11:ST3_smx:INFO:	Total # of broken channels: 0
14:14:11:ST3_smx:INFO:	List of broken channels: []
14:14:11:ST3_smx:INFO:	Total # of broken channels: 0
14:14:12:ST3_smx:INFO:	List of broken channels: []
14:14:13:ST3_smx:INFO:	chip: 26-5 	 31.389742 C 	 1177.390875 mV
14:14:13:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:14:13:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:14:13:ST3_smx:INFO:		Electrons
14:14:13:ST3_smx:INFO:	# loops 0
14:14:15:ST3_smx:INFO:	# loops 1
14:14:17:ST3_smx:INFO:	# loops 2
14:14:18:ST3_smx:INFO:	Total # of broken channels: 0
14:14:18:ST3_smx:INFO:	List of broken channels: []
14:14:18:ST3_smx:INFO:	Total # of broken channels: 7
14:14:18:ST3_smx:INFO:	List of broken channels: [13, 17, 35, 39, 41, 45, 47]
14:14:20:ST3_smx:INFO:	chip: 17-6 	 40.898880 C 	 1171.483840 mV
14:14:20:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:14:20:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:14:20:ST3_smx:INFO:		Electrons
14:14:20:ST3_smx:INFO:	# loops 0
14:14:22:ST3_smx:INFO:	# loops 1
14:14:24:ST3_smx:INFO:	# loops 2
14:14:25:ST3_smx:INFO:	Total # of broken channels: 0
14:14:25:ST3_smx:INFO:	List of broken channels: []
14:14:25:ST3_smx:INFO:	Total # of broken channels: 1
14:14:25:ST3_smx:INFO:	List of broken channels: [115]
14:14:27:ST3_smx:INFO:	chip: 24-7 	 40.898880 C 	 1165.571835 mV
14:14:27:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:14:27:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:14:27:ST3_smx:INFO:		Electrons
14:14:27:ST3_smx:INFO:	# loops 0
14:14:29:ST3_smx:INFO:	# loops 1
14:14:30:ST3_smx:INFO:	# loops 2
14:14:32:ST3_smx:INFO:	Total # of broken channels: 1
14:14:32:ST3_smx:INFO:	List of broken channels: [35]
14:14:32:ST3_smx:INFO:	Total # of broken channels: 0
14:14:32:ST3_smx:INFO:	List of broken channels: []
14:14:33:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:14:33:febtest:INFO:	23-00 | XA-000-09-004-007-010-011-01 |  40.9 | 1189.2
14:14:33:febtest:INFO:	30-01 | XA-000-09-004-007-011-005-12 |  28.2 | 1224.5
14:14:33:febtest:INFO:	21-02 | XA-000-09-004-007-011-010-12 |  40.9 | 1195.1
14:14:33:febtest:INFO:	28-03 | XA-000-09-004-007-012-005-04 |  37.7 | 1189.2
14:14:34:febtest:INFO:	19-04 | XA-000-09-004-007-010-012-01 |  56.8 | 1124.0
14:14:34:febtest:INFO:	26-05 | XA-000-09-004-007-010-006-01 |  34.6 | 1201.0
14:14:34:febtest:INFO:	17-06 | XA-000-09-004-007-012-011-04 |  40.9 | 1189.2
14:14:34:febtest:INFO:	24-07 | XA-000-09-004-007-012-010-04 |  40.9 | 1183.3
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_02_05-14_13_06
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_2
------------------------------------------------------------
| FEB_SN : 2334| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.449', '1.5250', '1.849', '2.3140']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0080', '1.849', '2.5940']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9940', '1.850', '0.5338']