DTL-STS tests database

FEB_2373 21.03.25 10:40:26

link:
...SMX_0.root
link:
...SMX_2.root
link:
...SMX_4.root
link:
...SMX_6.root
link: XA-000-09-004-013-011-002-10
...SMX_1.root
link: XA-000-09-004-013-011-021-13
...SMX_3.root
link: XA-000-09-004-013-012-019-05
...SMX_5.root
link: XA-000-09-004-013-012-020-05
...SMX_7.root
link: XA-000-09-004-013-012-020-05
...VddmCSAstatus.root
Info
            10:40:26:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:40:26:ST3_Shared:INFO:	                       FEB-Microcable                       
10:40:26:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:40:26:febtest:INFO:	Testing FEB with SN 2373
==============================================OOO==============================================
10:40:27:smx_tester:INFO:	Scanning setup
10:40:27:elinks:INFO:	Disabling clock on downlink 0
10:40:27:elinks:INFO:	Disabling clock on downlink 1
10:40:27:elinks:INFO:	Disabling clock on downlink 2
10:40:27:elinks:INFO:	Disabling clock on downlink 3
10:40:27:elinks:INFO:	Disabling clock on downlink 4
10:40:27:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:40:27:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
10:40:27:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:40:27:elinks:INFO:	Disabling clock on downlink 0
10:40:27:elinks:INFO:	Disabling clock on downlink 1
10:40:27:elinks:INFO:	Disabling clock on downlink 2
10:40:27:elinks:INFO:	Disabling clock on downlink 3
10:40:27:elinks:INFO:	Disabling clock on downlink 4
10:40:27:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:40:27:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
10:40:27:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:40:27:elinks:INFO:	Disabling clock on downlink 0
10:40:27:elinks:INFO:	Disabling clock on downlink 1
10:40:27:elinks:INFO:	Disabling clock on downlink 2
10:40:27:elinks:INFO:	Disabling clock on downlink 3
10:40:27:elinks:INFO:	Disabling clock on downlink 4
10:40:27:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:40:27:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:40:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
10:40:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
10:40:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
10:40:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
10:40:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
10:40:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
10:40:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
10:40:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
10:40:28:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:40:28:elinks:INFO:	Disabling clock on downlink 0
10:40:28:elinks:INFO:	Disabling clock on downlink 1
10:40:28:elinks:INFO:	Disabling clock on downlink 2
10:40:28:elinks:INFO:	Disabling clock on downlink 3
10:40:28:elinks:INFO:	Disabling clock on downlink 4
10:40:28:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:40:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
10:40:28:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:40:28:elinks:INFO:	Disabling clock on downlink 0
10:40:28:elinks:INFO:	Disabling clock on downlink 1
10:40:28:elinks:INFO:	Disabling clock on downlink 2
10:40:28:elinks:INFO:	Disabling clock on downlink 3
10:40:28:elinks:INFO:	Disabling clock on downlink 4
10:40:28:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:40:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
10:40:28:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
10:40:28:setup_element:INFO:	Scanning clock phase
10:40:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:40:28:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:40:28:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
10:40:28:setup_element:INFO:	Eye window for uplink 24: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
10:40:28:setup_element:INFO:	Eye window for uplink 25: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
10:40:28:setup_element:INFO:	Eye window for uplink 26: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
10:40:28:setup_element:INFO:	Eye window for uplink 27: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
10:40:28:setup_element:INFO:	Eye window for uplink 28: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
10:40:28:setup_element:INFO:	Eye window for uplink 29: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
10:40:28:setup_element:INFO:	Eye window for uplink 30: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
10:40:28:setup_element:INFO:	Eye window for uplink 31: ______________________________________________________________________XXXXXXX___
Clock Delay: 33
10:40:28:setup_element:INFO:	Setting the clock phase to 32 for group 0, downlink 2
==============================================OOO==============================================
10:40:28:setup_element:INFO:	Scanning data phases
10:40:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:40:28:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:40:33:setup_element:INFO:	Data phase scan results for group 0, downlink 2
10:40:33:setup_element:INFO:	Eye window for uplink 24: ______________XXXXX_____________________
Data delay found: 36
10:40:34:setup_element:INFO:	Eye window for uplink 25: _______________XXXXX____________________
Data delay found: 37
10:40:34:setup_element:INFO:	Eye window for uplink 26: ________________XXXXXX__________________
Data delay found: 38
10:40:34:setup_element:INFO:	Eye window for uplink 27: _________________XXXXXX_________________
Data delay found: 39
10:40:34:setup_element:INFO:	Eye window for uplink 28: ________________XXXXXX__________________
Data delay found: 38
10:40:34:setup_element:INFO:	Eye window for uplink 29: _______________XXXXXX___________________
Data delay found: 37
10:40:34:setup_element:INFO:	Eye window for uplink 30: _____________________XXXXXX_____________
Data delay found: 3
10:40:34:setup_element:INFO:	Eye window for uplink 31: ___________________XXXXXXX______________
Data delay found: 2
10:40:34:setup_element:INFO:	Setting the data phase to 36 for uplink 24
10:40:34:setup_element:INFO:	Setting the data phase to 37 for uplink 25
10:40:34:setup_element:INFO:	Setting the data phase to 38 for uplink 26
10:40:34:setup_element:INFO:	Setting the data phase to 39 for uplink 27
10:40:34:setup_element:INFO:	Setting the data phase to 38 for uplink 28
10:40:34:setup_element:INFO:	Setting the data phase to 37 for uplink 29
10:40:34:setup_element:INFO:	Setting the data phase to 3 for uplink 30
10:40:34:setup_element:INFO:	Setting the data phase to 2 for uplink 31
==============================================OOO==============================================
10:40:34:setup_element:INFO:	Beginning SMX ASICs map scan
10:40:34:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:40:34:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:40:34:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
10:40:34:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
10:40:34:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
10:40:34:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
10:40:34:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
10:40:34:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
10:40:34:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
10:40:35:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
10:40:35:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
10:40:35:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
10:40:35:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
10:40:36:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 32
    Window Length: 71
    Eye Windows:
      Uplink 24: ____________________________________________________________________XXXXXXXX____
      Uplink 25: ____________________________________________________________________XXXXXXXX____
      Uplink 26: ____________________________________________________________________XXXXXXXX____
      Uplink 27: ____________________________________________________________________XXXXXXXX____
      Uplink 28: ____________________________________________________________________XXXXXXX_____
      Uplink 29: ____________________________________________________________________XXXXXXX_____
      Uplink 30: ______________________________________________________________________XXXXXXX___
      Uplink 31: ______________________________________________________________________XXXXXXX___
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 36
      Window Length: 35
      Eye Window: ______________XXXXX_____________________
    Uplink 25:
      Optimal Phase: 37
      Window Length: 35
      Eye Window: _______________XXXXX____________________
    Uplink 26:
      Optimal Phase: 38
      Window Length: 34
      Eye Window: ________________XXXXXX__________________
    Uplink 27:
      Optimal Phase: 39
      Window Length: 34
      Eye Window: _________________XXXXXX_________________
    Uplink 28:
      Optimal Phase: 38
      Window Length: 34
      Eye Window: ________________XXXXXX__________________
    Uplink 29:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 30:
      Optimal Phase: 3
      Window Length: 34
      Eye Window: _____________________XXXXXX_____________
    Uplink 31:
      Optimal Phase: 2
      Window Length: 33
      Eye Window: ___________________XXXXXXX______________

==============================================OOO==============================================
10:40:36:setup_element:INFO:	Performing Elink synchronization
10:40:36:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:40:36:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:40:36:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
10:40:36:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
10:40:36:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
10:40:36:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
10:40:37:febtest:INFO:	Init all SMX (CSA): 30
10:40:44:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:40:45:febtest:INFO:	30-01 | XA-000-09-004-013-011-002-10 |  44.1 | 1130.0
10:40:45:febtest:INFO:	28-03 | XA-000-09-004-013-011-021-13 |  25.1 | 1195.1
10:40:45:febtest:INFO:	26-05 | XA-000-09-004-013-012-019-05 |  44.1 | 1130.0
10:40:45:febtest:INFO:	24-07 | XA-000-09-004-013-012-020-05 |  44.1 | 1135.9
10:40:46:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
10:40:48:ST3_smx:INFO:	chip: 30-1 	 40.898880 C 	 1135.937260 mV
10:40:48:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:40:48:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:40:48:ST3_smx:INFO:		Electrons
10:40:48:ST3_smx:INFO:	# loops 0
10:40:50:ST3_smx:INFO:	# loops 1
10:40:52:ST3_smx:INFO:	# loops 2
10:40:53:ST3_smx:INFO:	Total # of broken channels: 0
10:40:53:ST3_smx:INFO:	List of broken channels: []
10:40:53:ST3_smx:INFO:	Total # of broken channels: 0
10:40:53:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
10:40:55:ST3_smx:INFO:	chip: 28-3 	 25.062742 C 	 1206.851500 mV
10:40:55:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:40:55:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:40:55:ST3_smx:INFO:		Electrons
10:40:55:ST3_smx:INFO:	# loops 0
10:40:57:ST3_smx:INFO:	# loops 1
10:40:58:ST3_smx:INFO:	# loops 2
10:41:00:ST3_smx:INFO:	Total # of broken channels: 0
10:41:00:ST3_smx:INFO:	List of broken channels: []
10:41:00:ST3_smx:INFO:	Total # of broken channels: 0
10:41:00:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
10:41:02:ST3_smx:INFO:	chip: 26-5 	 44.073563 C 	 1141.874115 mV
10:41:02:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:41:02:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:41:02:ST3_smx:INFO:		Electrons
10:41:02:ST3_smx:INFO:	# loops 0
10:41:04:ST3_smx:INFO:	# loops 1
10:41:05:ST3_smx:INFO:	# loops 2
10:41:07:ST3_smx:INFO:	Total # of broken channels: 0
10:41:07:ST3_smx:INFO:	List of broken channels: []
10:41:07:ST3_smx:INFO:	Total # of broken channels: 0
10:41:07:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
10:41:09:ST3_smx:INFO:	chip: 24-7 	 44.073563 C 	 1141.874115 mV
10:41:09:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:41:09:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:41:09:ST3_smx:INFO:		Electrons
10:41:09:ST3_smx:INFO:	# loops 0
10:41:11:ST3_smx:INFO:	# loops 1
10:41:12:ST3_smx:INFO:	# loops 2
10:41:14:ST3_smx:INFO:	Total # of broken channels: 0
10:41:14:ST3_smx:INFO:	List of broken channels: []
10:41:14:ST3_smx:INFO:	Total # of broken channels: 0
10:41:14:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
10:41:14:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:41:15:febtest:INFO:	30-01 | XA-000-09-004-013-011-002-10 |  40.9 | 1159.7
10:41:15:febtest:INFO:	28-03 | XA-000-09-004-013-011-021-13 |  25.1 | 1236.2
10:41:15:febtest:INFO:	26-05 | XA-000-09-004-013-012-019-05 |  44.1 | 1159.7
10:41:15:febtest:INFO:	24-07 | XA-000-09-004-013-012-020-05 |  44.1 | 1165.6
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_03_21-10_40_26
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2373| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9326', '1.848', '1.4630']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0100', '1.850', '1.2810']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9911', '1.850', '0.2654']
Comment