FEB_2396    22.04.25 12:48:00

TextEdit.txt
            12:48:00:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:48:00:ST3_Shared:INFO:	                       FEB-Microcable                       
12:48:00:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:48:00:febtest:INFO:	Testing FEB with SN 2396
==============================================OOO==============================================
12:48:02:smx_tester:INFO:	Scanning setup
12:48:02:elinks:INFO:	Disabling clock on downlink 0
12:48:02:elinks:INFO:	Disabling clock on downlink 1
12:48:02:elinks:INFO:	Disabling clock on downlink 2
12:48:02:elinks:INFO:	Disabling clock on downlink 3
12:48:02:elinks:INFO:	Disabling clock on downlink 4
12:48:02:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:48:02:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
12:48:02:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:48:02:elinks:INFO:	Disabling clock on downlink 0
12:48:02:elinks:INFO:	Disabling clock on downlink 1
12:48:02:elinks:INFO:	Disabling clock on downlink 2
12:48:02:elinks:INFO:	Disabling clock on downlink 3
12:48:02:elinks:INFO:	Disabling clock on downlink 4
12:48:02:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:48:02:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
12:48:02:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:48:02:elinks:INFO:	Disabling clock on downlink 0
12:48:02:elinks:INFO:	Disabling clock on downlink 1
12:48:02:elinks:INFO:	Disabling clock on downlink 2
12:48:02:elinks:INFO:	Disabling clock on downlink 3
12:48:02:elinks:INFO:	Disabling clock on downlink 4
12:48:02:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:48:02:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:48:02:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
12:48:02:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
12:48:02:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
12:48:02:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
12:48:02:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
12:48:02:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
12:48:02:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
12:48:02:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
12:48:02:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:48:02:elinks:INFO:	Disabling clock on downlink 0
12:48:02:elinks:INFO:	Disabling clock on downlink 1
12:48:02:elinks:INFO:	Disabling clock on downlink 2
12:48:02:elinks:INFO:	Disabling clock on downlink 3
12:48:02:elinks:INFO:	Disabling clock on downlink 4
12:48:02:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:48:02:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
12:48:02:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:48:02:elinks:INFO:	Disabling clock on downlink 0
12:48:02:elinks:INFO:	Disabling clock on downlink 1
12:48:02:elinks:INFO:	Disabling clock on downlink 2
12:48:02:elinks:INFO:	Disabling clock on downlink 3
12:48:02:elinks:INFO:	Disabling clock on downlink 4
12:48:02:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:48:02:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
12:48:03:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
12:48:03:setup_element:INFO:	Scanning clock phase
12:48:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:48:03:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:48:03:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
12:48:03:setup_element:INFO:	Eye window for uplink 24: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
12:48:03:setup_element:INFO:	Eye window for uplink 25: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
12:48:03:setup_element:INFO:	Eye window for uplink 26: ____________________________________________________________________XXXXXXXXXX__
Clock Delay: 32
12:48:03:setup_element:INFO:	Eye window for uplink 27: ____________________________________________________________________XXXXXXXXXX__
Clock Delay: 32
12:48:03:setup_element:INFO:	Eye window for uplink 28: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
12:48:03:setup_element:INFO:	Eye window for uplink 29: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
12:48:03:setup_element:INFO:	Eye window for uplink 30: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
12:48:03:setup_element:INFO:	Eye window for uplink 31: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
12:48:03:setup_element:INFO:	Setting the clock phase to 32 for group 0, downlink 2
==============================================OOO==============================================
12:48:03:setup_element:INFO:	Scanning data phases
12:48:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:48:03:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:48:08:setup_element:INFO:	Data phase scan results for group 0, downlink 2
12:48:08:setup_element:INFO:	Eye window for uplink 24: ___________XXXXXXXX_____________________
Data delay found: 34
12:48:08:setup_element:INFO:	Eye window for uplink 25: ____________XXXXXXXX____________________
Data delay found: 35
12:48:08:setup_element:INFO:	Eye window for uplink 26: ____________XXXXXXXXXX__________________
Data delay found: 36
12:48:08:setup_element:INFO:	Eye window for uplink 27: ____________XXX__XXXXXXX________________
Data delay found: 37
12:48:08:setup_element:INFO:	Eye window for uplink 28: ___________________XXXXX________________
Data delay found: 1
12:48:08:setup_element:INFO:	Eye window for uplink 29: __________________XXXXXX________________
Data delay found: 0
12:48:08:setup_element:INFO:	Eye window for uplink 30: ____________________XXXXXX______________
Data delay found: 2
12:48:08:setup_element:INFO:	Eye window for uplink 31: __________________XXXXXXX_______________
Data delay found: 1
12:48:08:setup_element:INFO:	Setting the data phase to 34 for uplink 24
12:48:08:setup_element:INFO:	Setting the data phase to 35 for uplink 25
12:48:08:setup_element:INFO:	Setting the data phase to 36 for uplink 26
12:48:08:setup_element:INFO:	Setting the data phase to 37 for uplink 27
12:48:08:setup_element:INFO:	Setting the data phase to 1 for uplink 28
12:48:08:setup_element:INFO:	Setting the data phase to 0 for uplink 29
12:48:08:setup_element:INFO:	Setting the data phase to 2 for uplink 30
12:48:08:setup_element:INFO:	Setting the data phase to 1 for uplink 31
==============================================OOO==============================================
12:48:08:setup_element:INFO:	Beginning SMX ASICs map scan
12:48:08:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:48:08:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:48:08:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
12:48:08:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
12:48:08:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
12:48:09:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
12:48:09:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
12:48:09:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
12:48:09:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
12:48:09:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
12:48:09:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
12:48:10:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
12:48:10:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
12:48:11:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 32
    Window Length: 70
    Eye Windows:
      Uplink 24: _____________________________________________________________________XXXXXXX____
      Uplink 25: _____________________________________________________________________XXXXXXX____
      Uplink 26: ____________________________________________________________________XXXXXXXXXX__
      Uplink 27: ____________________________________________________________________XXXXXXXXXX__
      Uplink 28: ____________________________________________________________________XXXXXXXX____
      Uplink 29: ____________________________________________________________________XXXXXXXX____
      Uplink 30: ____________________________________________________________________XXXXXXXXX___
      Uplink 31: ____________________________________________________________________XXXXXXXXX___
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 34
      Window Length: 32
      Eye Window: ___________XXXXXXXX_____________________
    Uplink 25:
      Optimal Phase: 35
      Window Length: 32
      Eye Window: ____________XXXXXXXX____________________
    Uplink 26:
      Optimal Phase: 36
      Window Length: 30
      Eye Window: ____________XXXXXXXXXX__________________
    Uplink 27:
      Optimal Phase: 37
      Window Length: 28
      Eye Window: ____________XXX__XXXXXXX________________
    Uplink 28:
      Optimal Phase: 1
      Window Length: 35
      Eye Window: ___________________XXXXX________________
    Uplink 29:
      Optimal Phase: 0
      Window Length: 34
      Eye Window: __________________XXXXXX________________
    Uplink 30:
      Optimal Phase: 2
      Window Length: 34
      Eye Window: ____________________XXXXXX______________
    Uplink 31:
      Optimal Phase: 1
      Window Length: 33
      Eye Window: __________________XXXXXXX_______________

==============================================OOO==============================================
12:48:11:setup_element:INFO:	Performing Elink synchronization
12:48:11:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:48:11:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:48:11:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
12:48:11:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
12:48:11:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
12:48:11:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
12:48:11:febtest:INFO:	Init all SMX (CSA): 30
12:48:19:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
12:48:19:febtest:INFO:	30-01 | XA-000-09-004-016-009-020-13 |  28.2 | 1165.6
12:48:20:febtest:INFO:	28-03 | XA-000-09-004-016-009-019-13 |  37.7 | 1135.9
12:48:20:febtest:INFO:	26-05 | XA-000-09-004-016-006-019-09 |  25.1 | 1171.5
12:48:20:febtest:INFO:	24-07 | XA-000-09-004-016-012-020-06 |  31.4 | 1153.7
12:48:21:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
12:48:23:ST3_smx:INFO:	chip: 30-1 	 28.225000 C 	 1177.390875 mV
12:48:23:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:23:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:23:ST3_smx:INFO:		Electrons
12:48:23:ST3_smx:INFO:	# loops 0
12:48:25:ST3_smx:INFO:	# loops 1
12:48:27:ST3_smx:INFO:	# loops 2
12:48:28:ST3_smx:INFO:	Total # of broken channels: 0
12:48:28:ST3_smx:INFO:	List of broken channels: []
12:48:28:ST3_smx:INFO:	Total # of broken channels: 0
12:48:28:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
12:48:30:ST3_smx:INFO:	chip: 28-3 	 37.726682 C 	 1141.874115 mV
12:48:30:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:30:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:30:ST3_smx:INFO:		Electrons
12:48:30:ST3_smx:INFO:	# loops 0
12:48:32:ST3_smx:INFO:	# loops 1
12:48:33:ST3_smx:INFO:	# loops 2
12:48:35:ST3_smx:INFO:	Total # of broken channels: 0
12:48:35:ST3_smx:INFO:	List of broken channels: []
12:48:35:ST3_smx:INFO:	Total # of broken channels: 0
12:48:35:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
12:48:37:ST3_smx:INFO:	chip: 26-5 	 25.062742 C 	 1183.292940 mV
12:48:37:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:37:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:37:ST3_smx:INFO:		Electrons
12:48:37:ST3_smx:INFO:	# loops 0
12:48:39:ST3_smx:INFO:	# loops 1
12:48:40:ST3_smx:INFO:	# loops 2
12:48:42:ST3_smx:INFO:	Total # of broken channels: 0
12:48:42:ST3_smx:INFO:	List of broken channels: []
12:48:42:ST3_smx:INFO:	Total # of broken channels: 0
12:48:42:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
12:48:44:ST3_smx:INFO:	chip: 24-7 	 31.389742 C 	 1159.654860 mV
12:48:44:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:44:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:48:44:ST3_smx:INFO:		Electrons
12:48:44:ST3_smx:INFO:	# loops 0
12:48:46:ST3_smx:INFO:	# loops 1
12:48:48:ST3_smx:INFO:	# loops 2
12:48:49:ST3_smx:INFO:	Total # of broken channels: 0
12:48:49:ST3_smx:INFO:	List of broken channels: []
12:48:49:ST3_smx:INFO:	Total # of broken channels: 0
12:48:49:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
12:48:50:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
12:48:50:febtest:INFO:	30-01 | XA-000-09-004-016-009-020-13 |  28.2 | 1201.0
12:48:50:febtest:INFO:	28-03 | XA-000-09-004-016-009-019-13 |  40.9 | 1165.6
12:48:50:febtest:INFO:	26-05 | XA-000-09-004-016-006-019-09 |  28.2 | 1206.9
12:48:50:febtest:INFO:	24-07 | XA-000-09-004-016-012-020-06 |  34.6 | 1183.3
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_04_22-12_48_00
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2396| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.449', '0.8005', '1.846', '1.1370']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0150', '1.850', '1.3150']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9971', '1.850', '0.2679']