FEB_2423    16.05.25 11:03:32

TextEdit.txt
            11:03:32:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:03:32:ST3_Shared:INFO:	                       FEB-Microcable                       
11:03:32:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:03:32:febtest:INFO:	Testing FEB with SN 2423
==============================================OOO==============================================
11:03:34:smx_tester:INFO:	Scanning setup
11:03:34:elinks:INFO:	Disabling clock on downlink 0
11:03:34:elinks:INFO:	Disabling clock on downlink 1
11:03:34:elinks:INFO:	Disabling clock on downlink 2
11:03:34:elinks:INFO:	Disabling clock on downlink 3
11:03:34:elinks:INFO:	Disabling clock on downlink 4
11:03:34:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:03:34:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
11:03:34:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
11:03:34:elinks:INFO:	Disabling clock on downlink 0
11:03:34:elinks:INFO:	Disabling clock on downlink 1
11:03:34:elinks:INFO:	Disabling clock on downlink 2
11:03:34:elinks:INFO:	Disabling clock on downlink 3
11:03:34:elinks:INFO:	Disabling clock on downlink 4
11:03:34:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:03:34:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
11:03:34:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
11:03:34:elinks:INFO:	Disabling clock on downlink 0
11:03:34:elinks:INFO:	Disabling clock on downlink 1
11:03:34:elinks:INFO:	Disabling clock on downlink 2
11:03:34:elinks:INFO:	Disabling clock on downlink 3
11:03:34:elinks:INFO:	Disabling clock on downlink 4
11:03:34:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:03:34:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:03:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
11:03:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
11:03:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
11:03:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
11:03:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
11:03:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
11:03:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
11:03:35:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
11:03:35:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
11:03:35:elinks:INFO:	Disabling clock on downlink 0
11:03:35:elinks:INFO:	Disabling clock on downlink 1
11:03:35:elinks:INFO:	Disabling clock on downlink 2
11:03:35:elinks:INFO:	Disabling clock on downlink 3
11:03:35:elinks:INFO:	Disabling clock on downlink 4
11:03:35:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:03:35:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
11:03:35:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
11:03:35:elinks:INFO:	Disabling clock on downlink 0
11:03:35:elinks:INFO:	Disabling clock on downlink 1
11:03:35:elinks:INFO:	Disabling clock on downlink 2
11:03:35:elinks:INFO:	Disabling clock on downlink 3
11:03:35:elinks:INFO:	Disabling clock on downlink 4
11:03:35:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:03:35:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
11:03:35:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
11:03:35:setup_element:INFO:	Scanning clock phase
11:03:35:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:03:35:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:03:35:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
11:03:35:setup_element:INFO:	Eye window for uplink 24: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
11:03:35:setup_element:INFO:	Eye window for uplink 25: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
11:03:35:setup_element:INFO:	Eye window for uplink 26: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
11:03:35:setup_element:INFO:	Eye window for uplink 27: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
11:03:35:setup_element:INFO:	Eye window for uplink 28: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
11:03:35:setup_element:INFO:	Eye window for uplink 29: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
11:03:35:setup_element:INFO:	Eye window for uplink 30: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
11:03:35:setup_element:INFO:	Eye window for uplink 31: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
11:03:35:setup_element:INFO:	Setting the clock phase to 31 for group 0, downlink 2
==============================================OOO==============================================
11:03:35:setup_element:INFO:	Scanning data phases
11:03:35:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:03:35:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:03:40:setup_element:INFO:	Data phase scan results for group 0, downlink 2
11:03:40:setup_element:INFO:	Eye window for uplink 24: ____________XXXXX_______________________
Data delay found: 34
11:03:40:setup_element:INFO:	Eye window for uplink 25: ______________XXXXX_____________________
Data delay found: 36
11:03:40:setup_element:INFO:	Eye window for uplink 26: ________________XXXXX___________________
Data delay found: 38
11:03:40:setup_element:INFO:	Eye window for uplink 27: _________________XXXXXX_________________
Data delay found: 39
11:03:40:setup_element:INFO:	Eye window for uplink 28: ___________________XXXXXX_______________
Data delay found: 1
11:03:40:setup_element:INFO:	Eye window for uplink 29: ___________________XXXXXX_______________
Data delay found: 1
11:03:41:setup_element:INFO:	Eye window for uplink 30: _____________________XXXXXXX____________
Data delay found: 4
11:03:41:setup_element:INFO:	Eye window for uplink 31: ___________________XXXXXXX______________
Data delay found: 2
11:03:41:setup_element:INFO:	Setting the data phase to 34 for uplink 24
11:03:41:setup_element:INFO:	Setting the data phase to 36 for uplink 25
11:03:41:setup_element:INFO:	Setting the data phase to 38 for uplink 26
11:03:41:setup_element:INFO:	Setting the data phase to 39 for uplink 27
11:03:41:setup_element:INFO:	Setting the data phase to 1 for uplink 28
11:03:41:setup_element:INFO:	Setting the data phase to 1 for uplink 29
11:03:41:setup_element:INFO:	Setting the data phase to 4 for uplink 30
11:03:41:setup_element:INFO:	Setting the data phase to 2 for uplink 31
==============================================OOO==============================================
11:03:41:setup_element:INFO:	Beginning SMX ASICs map scan
11:03:41:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:03:41:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:03:41:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
11:03:41:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
11:03:41:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
11:03:41:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
11:03:41:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
11:03:41:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
11:03:41:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
11:03:41:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
11:03:42:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
11:03:42:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
11:03:42:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
11:03:43:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 31
    Window Length: 70
    Eye Windows:
      Uplink 24: ___________________________________________________________________XXXXXXXX_____
      Uplink 25: ___________________________________________________________________XXXXXXXX_____
      Uplink 26: ____________________________________________________________________XXXXXXXX____
      Uplink 27: ____________________________________________________________________XXXXXXXX____
      Uplink 28: ____________________________________________________________________XXXXXXXXX___
      Uplink 29: ____________________________________________________________________XXXXXXXXX___
      Uplink 30: _____________________________________________________________________XXXXXXXX___
      Uplink 31: _____________________________________________________________________XXXXXXXX___
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 34
      Window Length: 35
      Eye Window: ____________XXXXX_______________________
    Uplink 25:
      Optimal Phase: 36
      Window Length: 35
      Eye Window: ______________XXXXX_____________________
    Uplink 26:
      Optimal Phase: 38
      Window Length: 35
      Eye Window: ________________XXXXX___________________
    Uplink 27:
      Optimal Phase: 39
      Window Length: 34
      Eye Window: _________________XXXXXX_________________
    Uplink 28:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 29:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 30:
      Optimal Phase: 4
      Window Length: 33
      Eye Window: _____________________XXXXXXX____________
    Uplink 31:
      Optimal Phase: 2
      Window Length: 33
      Eye Window: ___________________XXXXXXX______________

==============================================OOO==============================================
11:03:43:setup_element:INFO:	Performing Elink synchronization
11:03:43:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:03:43:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:03:43:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
11:03:43:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
11:03:43:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
11:03:43:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
11:03:44:febtest:INFO:	Init all SMX (CSA): 30
11:03:51:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:03:52:febtest:INFO:	30-01 | XA-000-09-004-016-008-014-07 |  40.9 | 1130.0
11:03:52:febtest:INFO:	28-03 | XA-000-09-004-015-013-014-06 |  44.1 | 1130.0
11:03:52:febtest:INFO:	26-05 | XA-000-09-004-016-011-014-09 |  40.9 | 1135.9
11:03:52:febtest:INFO:	24-07 | XA-000-09-004-015-007-015-09 |  40.9 | 1141.9
11:03:53:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
11:03:55:ST3_smx:INFO:	chip: 30-1 	 44.073563 C 	 1141.874115 mV
11:03:55:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:03:55:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:03:55:ST3_smx:INFO:		Electrons
11:03:55:ST3_smx:INFO:	# loops 0
11:03:57:ST3_smx:INFO:	# loops 1
11:03:59:ST3_smx:INFO:	# loops 2
11:04:01:ST3_smx:INFO:	Total # of broken channels: 0
11:04:01:ST3_smx:INFO:	List of broken channels: []
11:04:01:ST3_smx:INFO:	Total # of broken channels: 0
11:04:01:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:04:02:ST3_smx:INFO:	chip: 28-3 	 40.898880 C 	 1141.874115 mV
11:04:02:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:04:02:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:04:03:ST3_smx:INFO:		Electrons
11:04:03:ST3_smx:INFO:	# loops 0
11:04:04:ST3_smx:INFO:	# loops 1
11:04:06:ST3_smx:INFO:	# loops 2
11:04:08:ST3_smx:INFO:	Total # of broken channels: 0
11:04:08:ST3_smx:INFO:	List of broken channels: []
11:04:08:ST3_smx:INFO:	Total # of broken channels: 0
11:04:08:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:04:09:ST3_smx:INFO:	chip: 26-5 	 40.898880 C 	 1141.874115 mV
11:04:09:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:04:09:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:04:09:ST3_smx:INFO:		Electrons
11:04:09:ST3_smx:INFO:	# loops 0
11:04:11:ST3_smx:INFO:	# loops 1
11:04:13:ST3_smx:INFO:	# loops 2
11:04:14:ST3_smx:INFO:	Total # of broken channels: 0
11:04:14:ST3_smx:INFO:	List of broken channels: []
11:04:14:ST3_smx:INFO:	Total # of broken channels: 0
11:04:14:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:04:16:ST3_smx:INFO:	chip: 24-7 	 40.898880 C 	 1153.732915 mV
11:04:16:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:04:16:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:04:16:ST3_smx:INFO:		Electrons
11:04:16:ST3_smx:INFO:	# loops 0
11:04:18:ST3_smx:INFO:	# loops 1
11:04:20:ST3_smx:INFO:	# loops 2
11:04:21:ST3_smx:INFO:	Total # of broken channels: 1
11:04:21:ST3_smx:INFO:	List of broken channels: [60]
11:04:21:ST3_smx:INFO:	Total # of broken channels: 0
11:04:21:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:04:22:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:04:22:febtest:INFO:	30-01 | XA-000-09-004-016-008-014-07 |  44.1 | 1165.6
11:04:22:febtest:INFO:	28-03 | XA-000-09-004-015-013-014-06 |  44.1 | 1159.7
11:04:22:febtest:INFO:	26-05 | XA-000-09-004-016-011-014-09 |  44.1 | 1165.6
11:04:23:febtest:INFO:	24-07 | XA-000-09-004-015-007-015-09 |  44.1 | 1171.5
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_05_16-11_03_32
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2423| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.451', '0.8064', '1.848', '1.1400']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0240', '1.850', '1.3200']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0040', '1.850', '0.2722']