DTL-STS tests database

FEB_2428 04.06.25 09:04:26

link:
...SMX_0.root
link:
...SMX_2.root
link:
...SMX_4.root
link:
...SMX_6.root
link: XA-000-09-004-010-010-025-10
...SMX_1.root
link: XA-000-09-004-010-007-025-13
...SMX_3.root
link: XA-000-09-004-015-011-021-04
...SMX_5.root
link: XA-000-09-004-016-017-019-13
...SMX_7.root
link: XA-000-09-004-016-017-019-13
...VddmCSAstatus.root
Info
            09:04:26:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:04:26:ST3_Shared:INFO:	                       FEB-Microcable                       
09:04:26:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:04:26:febtest:INFO:	Testing FEB with SN 2428
==============================================OOO==============================================
09:04:27:smx_tester:INFO:	Scanning setup
09:04:27:elinks:INFO:	Disabling clock on downlink 0
09:04:27:elinks:INFO:	Disabling clock on downlink 1
09:04:27:elinks:INFO:	Disabling clock on downlink 2
09:04:28:elinks:INFO:	Disabling clock on downlink 3
09:04:28:elinks:INFO:	Disabling clock on downlink 4
09:04:28:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:04:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
09:04:28:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:04:28:elinks:INFO:	Disabling clock on downlink 0
09:04:28:elinks:INFO:	Disabling clock on downlink 1
09:04:28:elinks:INFO:	Disabling clock on downlink 2
09:04:28:elinks:INFO:	Disabling clock on downlink 3
09:04:28:elinks:INFO:	Disabling clock on downlink 4
09:04:28:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:04:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
09:04:28:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:04:28:elinks:INFO:	Disabling clock on downlink 0
09:04:28:elinks:INFO:	Disabling clock on downlink 1
09:04:28:elinks:INFO:	Disabling clock on downlink 2
09:04:28:elinks:INFO:	Disabling clock on downlink 3
09:04:28:elinks:INFO:	Disabling clock on downlink 4
09:04:28:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:04:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:04:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
09:04:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
09:04:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
09:04:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
09:04:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
09:04:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
09:04:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
09:04:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
09:04:28:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:04:28:elinks:INFO:	Disabling clock on downlink 0
09:04:28:elinks:INFO:	Disabling clock on downlink 1
09:04:28:elinks:INFO:	Disabling clock on downlink 2
09:04:28:elinks:INFO:	Disabling clock on downlink 3
09:04:28:elinks:INFO:	Disabling clock on downlink 4
09:04:28:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:04:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
09:04:28:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:04:28:elinks:INFO:	Disabling clock on downlink 0
09:04:28:elinks:INFO:	Disabling clock on downlink 1
09:04:28:elinks:INFO:	Disabling clock on downlink 2
09:04:28:elinks:INFO:	Disabling clock on downlink 3
09:04:28:elinks:INFO:	Disabling clock on downlink 4
09:04:28:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:04:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
09:04:28:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
09:04:28:setup_element:INFO:	Scanning clock phase
09:04:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:04:29:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:04:29:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
09:04:29:setup_element:INFO:	Eye window for uplink 24: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
09:04:29:setup_element:INFO:	Eye window for uplink 25: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
09:04:29:setup_element:INFO:	Eye window for uplink 26: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
09:04:29:setup_element:INFO:	Eye window for uplink 27: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
09:04:29:setup_element:INFO:	Eye window for uplink 28: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
09:04:29:setup_element:INFO:	Eye window for uplink 29: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
09:04:29:setup_element:INFO:	Eye window for uplink 30: ________________________________________________________________________________
Clock Delay: 40
09:04:29:setup_element:INFO:	Eye window for uplink 31: ________________________________________________________________________________
Clock Delay: 40
09:04:29:setup_element:INFO:	Setting the clock phase to 31 for group 0, downlink 2
==============================================OOO==============================================
09:04:29:setup_element:INFO:	Scanning data phases
09:04:29:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:04:29:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:04:34:setup_element:INFO:	Data phase scan results for group 0, downlink 2
09:04:34:setup_element:INFO:	Eye window for uplink 24: ______________XXXXXX____________________
Data delay found: 36
09:04:34:setup_element:INFO:	Eye window for uplink 25: ________________XXXXX___________________
Data delay found: 38
09:04:34:setup_element:INFO:	Eye window for uplink 26: _____________XXXXXX_____________________
Data delay found: 35
09:04:34:setup_element:INFO:	Eye window for uplink 27: _______________XXXXXX___________________
Data delay found: 37
09:04:34:setup_element:INFO:	Eye window for uplink 28: ____________________XXXXXX______________
Data delay found: 2
09:04:34:setup_element:INFO:	Eye window for uplink 29: ___________________XXXXXX_______________
Data delay found: 1
09:04:34:setup_element:INFO:	Eye window for uplink 30: ______________________XXXXX_____________
Data delay found: 4
09:04:34:setup_element:INFO:	Eye window for uplink 31: ____________________XXXXXX______________
Data delay found: 2
09:04:34:setup_element:INFO:	Setting the data phase to 36 for uplink 24
09:04:34:setup_element:INFO:	Setting the data phase to 38 for uplink 25
09:04:34:setup_element:INFO:	Setting the data phase to 35 for uplink 26
09:04:34:setup_element:INFO:	Setting the data phase to 37 for uplink 27
09:04:34:setup_element:INFO:	Setting the data phase to 2 for uplink 28
09:04:34:setup_element:INFO:	Setting the data phase to 1 for uplink 29
09:04:34:setup_element:INFO:	Setting the data phase to 4 for uplink 30
09:04:34:setup_element:INFO:	Setting the data phase to 2 for uplink 31
==============================================OOO==============================================
09:04:34:setup_element:INFO:	Beginning SMX ASICs map scan
09:04:34:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:04:34:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:04:34:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
09:04:34:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
09:04:34:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
09:04:34:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
09:04:34:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
09:04:35:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
09:04:35:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
09:04:35:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
09:04:35:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
09:04:35:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
09:04:35:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
09:04:37:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 31
    Window Length: 70
    Eye Windows:
      Uplink 24: ____________________________________________________________________XXXXXXXXX___
      Uplink 25: ____________________________________________________________________XXXXXXXXX___
      Uplink 26: ___________________________________________________________________XXXXXXXX_____
      Uplink 27: ___________________________________________________________________XXXXXXXX_____
      Uplink 28: ____________________________________________________________________XXXXXXXXX___
      Uplink 29: ____________________________________________________________________XXXXXXXXX___
      Uplink 30: ________________________________________________________________________________
      Uplink 31: ________________________________________________________________________________
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 36
      Window Length: 34
      Eye Window: ______________XXXXXX____________________
    Uplink 25:
      Optimal Phase: 38
      Window Length: 35
      Eye Window: ________________XXXXX___________________
    Uplink 26:
      Optimal Phase: 35
      Window Length: 34
      Eye Window: _____________XXXXXX_____________________
    Uplink 27:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 28:
      Optimal Phase: 2
      Window Length: 34
      Eye Window: ____________________XXXXXX______________
    Uplink 29:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 30:
      Optimal Phase: 4
      Window Length: 35
      Eye Window: ______________________XXXXX_____________
    Uplink 31:
      Optimal Phase: 2
      Window Length: 34
      Eye Window: ____________________XXXXXX______________

==============================================OOO==============================================
09:04:37:setup_element:INFO:	Performing Elink synchronization
09:04:37:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:04:37:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:04:37:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
09:04:37:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
09:04:37:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
09:04:37:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
09:04:37:febtest:INFO:	Init all SMX (CSA): 30
09:04:44:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:04:45:febtest:INFO:	30-01 | XA-000-09-004-010-010-025-10 |  31.4 | 1159.7
09:04:45:febtest:INFO:	28-03 | XA-000-09-004-010-007-025-13 |  31.4 | 1165.6
09:04:45:febtest:INFO:	26-05 | XA-000-09-004-015-011-021-04 |  31.4 | 1153.7
09:04:45:febtest:INFO:	24-07 | XA-000-09-004-016-017-019-13 |   3.0 | 1259.6
09:04:46:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
09:04:48:ST3_smx:INFO:	chip: 30-1 	 31.389742 C 	 1171.483840 mV
09:04:48:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:04:48:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:04:48:ST3_smx:INFO:		Electrons
09:04:48:ST3_smx:INFO:	# loops 0
09:04:50:ST3_smx:INFO:	# loops 1
09:04:52:ST3_smx:INFO:	# loops 2
09:04:53:ST3_smx:INFO:	Total # of broken channels: 0
09:04:53:ST3_smx:INFO:	List of broken channels: []
09:04:53:ST3_smx:INFO:	Total # of broken channels: 0
09:04:53:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
09:04:55:ST3_smx:INFO:	chip: 28-3 	 31.389742 C 	 1171.483840 mV
09:04:55:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:04:55:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:04:55:ST3_smx:INFO:		Electrons
09:04:55:ST3_smx:INFO:	# loops 0
09:04:57:ST3_smx:INFO:	# loops 1
09:04:58:ST3_smx:INFO:	# loops 2
09:05:00:ST3_smx:INFO:	Total # of broken channels: 0
09:05:00:ST3_smx:INFO:	List of broken channels: []
09:05:00:ST3_smx:INFO:	Total # of broken channels: 0
09:05:00:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
09:05:01:ST3_smx:INFO:	chip: 26-5 	 34.556970 C 	 1159.654860 mV
09:05:01:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:05:01:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:05:01:ST3_smx:INFO:		Electrons
09:05:02:ST3_smx:INFO:	# loops 0
09:05:03:ST3_smx:INFO:	# loops 1
09:05:05:ST3_smx:INFO:	# loops 2
09:05:06:ST3_smx:INFO:	Total # of broken channels: 1
09:05:06:ST3_smx:INFO:	List of broken channels: [72]
09:05:06:ST3_smx:INFO:	Total # of broken channels: 0
09:05:06:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
09:05:08:ST3_smx:INFO:	chip: 24-7 	 6.141382 C 	 1265.400000 mV
09:05:08:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:05:08:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:05:08:ST3_smx:INFO:		Electrons
09:05:08:ST3_smx:INFO:	# loops 0
09:05:09:ST3_smx:INFO:	# loops 1
09:05:11:ST3_smx:INFO:	# loops 2
09:05:13:ST3_smx:INFO:	Total # of broken channels: 0
09:05:13:ST3_smx:INFO:	List of broken channels: []
09:05:13:ST3_smx:INFO:	Total # of broken channels: 0
09:05:13:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
09:05:13:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:05:13:febtest:INFO:	30-01 | XA-000-09-004-010-010-025-10 |  31.4 | 1189.2
09:05:13:febtest:INFO:	28-03 | XA-000-09-004-010-007-025-13 |  31.4 | 1201.0
09:05:14:febtest:INFO:	26-05 | XA-000-09-004-015-011-021-04 |  34.6 | 1177.4
09:05:14:febtest:INFO:	24-07 | XA-000-09-004-016-017-019-13 |   6.1 | 1288.7
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_06_04-09_04_26
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2428| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.6941', '1.848', '1.1600']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9895', '1.850', '1.2900']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9790', '1.850', '0.2653']
Comment