DTL-STS tests database

FEB_2432 10.06.25 10:24:09

link:
...SMX_0.root
link:
...SMX_2.root
link:
...SMX_4.root
link:
...SMX_6.root
link: XA-000-09-004-015-012-022-12
...SMX_1.root
link: XA-000-09-004-015-012-023-12
...SMX_3.root
link: XA-000-09-004-015-003-021-08
...SMX_5.root
link: XA-000-09-004-015-009-022-07
...SMX_7.root
link: XA-000-09-004-015-009-022-07
...VddmCSAstatus.root
Info
            10:24:09:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:24:09:ST3_Shared:INFO:	                       FEB-Microcable                       
10:24:09:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:24:09:febtest:INFO:	Testing FEB with SN 2432
==============================================OOO==============================================
10:24:11:smx_tester:INFO:	Scanning setup
10:24:11:elinks:INFO:	Disabling clock on downlink 0
10:24:11:elinks:INFO:	Disabling clock on downlink 1
10:24:11:elinks:INFO:	Disabling clock on downlink 2
10:24:11:elinks:INFO:	Disabling clock on downlink 3
10:24:11:elinks:INFO:	Disabling clock on downlink 4
10:24:11:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:24:11:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
10:24:11:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:24:11:elinks:INFO:	Disabling clock on downlink 0
10:24:11:elinks:INFO:	Disabling clock on downlink 1
10:24:11:elinks:INFO:	Disabling clock on downlink 2
10:24:11:elinks:INFO:	Disabling clock on downlink 3
10:24:11:elinks:INFO:	Disabling clock on downlink 4
10:24:11:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:24:11:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
10:24:11:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:24:11:elinks:INFO:	Disabling clock on downlink 0
10:24:11:elinks:INFO:	Disabling clock on downlink 1
10:24:11:elinks:INFO:	Disabling clock on downlink 2
10:24:11:elinks:INFO:	Disabling clock on downlink 3
10:24:11:elinks:INFO:	Disabling clock on downlink 4
10:24:11:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:24:11:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:24:11:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
10:24:11:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
10:24:11:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
10:24:11:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
10:24:11:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
10:24:11:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
10:24:11:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
10:24:11:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
10:24:11:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:24:11:elinks:INFO:	Disabling clock on downlink 0
10:24:11:elinks:INFO:	Disabling clock on downlink 1
10:24:11:elinks:INFO:	Disabling clock on downlink 2
10:24:11:elinks:INFO:	Disabling clock on downlink 3
10:24:11:elinks:INFO:	Disabling clock on downlink 4
10:24:11:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:24:11:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
10:24:11:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:24:11:elinks:INFO:	Disabling clock on downlink 0
10:24:11:elinks:INFO:	Disabling clock on downlink 1
10:24:11:elinks:INFO:	Disabling clock on downlink 2
10:24:11:elinks:INFO:	Disabling clock on downlink 3
10:24:11:elinks:INFO:	Disabling clock on downlink 4
10:24:11:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:24:11:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
10:24:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
10:24:12:setup_element:INFO:	Scanning clock phase
10:24:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:24:12:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:24:12:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
10:24:12:setup_element:INFO:	Eye window for uplink 24: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
10:24:12:setup_element:INFO:	Eye window for uplink 25: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
10:24:12:setup_element:INFO:	Eye window for uplink 26: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
10:24:12:setup_element:INFO:	Eye window for uplink 27: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
10:24:12:setup_element:INFO:	Eye window for uplink 28: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
10:24:12:setup_element:INFO:	Eye window for uplink 29: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
10:24:12:setup_element:INFO:	Eye window for uplink 30: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
10:24:12:setup_element:INFO:	Eye window for uplink 31: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
10:24:12:setup_element:INFO:	Setting the clock phase to 33 for group 0, downlink 2
==============================================OOO==============================================
10:24:12:setup_element:INFO:	Scanning data phases
10:24:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:24:12:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:24:17:setup_element:INFO:	Data phase scan results for group 0, downlink 2
10:24:17:setup_element:INFO:	Eye window for uplink 24: ______________XXXXXX____________________
Data delay found: 36
10:24:17:setup_element:INFO:	Eye window for uplink 25: ________________XXXX____________________
Data delay found: 37
10:24:17:setup_element:INFO:	Eye window for uplink 26: _______________XXXXXX___________________
Data delay found: 37
10:24:17:setup_element:INFO:	Eye window for uplink 27: ________________XXXXXXX_________________
Data delay found: 39
10:24:17:setup_element:INFO:	Eye window for uplink 28: ___________________XXXXXX_______________
Data delay found: 1
10:24:17:setup_element:INFO:	Eye window for uplink 29: ___________________XXXXXX_______________
Data delay found: 1
10:24:17:setup_element:INFO:	Eye window for uplink 30: _____________________XXXXXX_____________
Data delay found: 3
10:24:17:setup_element:INFO:	Eye window for uplink 31: ___________________XXXXXXX______________
Data delay found: 2
10:24:17:setup_element:INFO:	Setting the data phase to 36 for uplink 24
10:24:17:setup_element:INFO:	Setting the data phase to 37 for uplink 25
10:24:17:setup_element:INFO:	Setting the data phase to 37 for uplink 26
10:24:17:setup_element:INFO:	Setting the data phase to 39 for uplink 27
10:24:17:setup_element:INFO:	Setting the data phase to 1 for uplink 28
10:24:17:setup_element:INFO:	Setting the data phase to 1 for uplink 29
10:24:17:setup_element:INFO:	Setting the data phase to 3 for uplink 30
10:24:17:setup_element:INFO:	Setting the data phase to 2 for uplink 31
==============================================OOO==============================================
10:24:17:setup_element:INFO:	Beginning SMX ASICs map scan
10:24:17:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:24:17:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:24:17:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
10:24:17:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
10:24:17:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
10:24:17:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
10:24:17:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
10:24:18:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
10:24:18:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
10:24:18:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
10:24:18:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
10:24:18:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
10:24:18:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
10:24:20:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 33
    Window Length: 71
    Eye Windows:
      Uplink 24: _____________________________________________________________________XXXXXXXX___
      Uplink 25: _____________________________________________________________________XXXXXXXX___
      Uplink 26: _____________________________________________________________________XXXXXXXXX__
      Uplink 27: _____________________________________________________________________XXXXXXXXX__
      Uplink 28: _____________________________________________________________________XXXXXXXXX__
      Uplink 29: _____________________________________________________________________XXXXXXXXX__
      Uplink 30: _____________________________________________________________________XXXXXXXXX__
      Uplink 31: _____________________________________________________________________XXXXXXXXX__
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 36
      Window Length: 34
      Eye Window: ______________XXXXXX____________________
    Uplink 25:
      Optimal Phase: 37
      Window Length: 36
      Eye Window: ________________XXXX____________________
    Uplink 26:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 27:
      Optimal Phase: 39
      Window Length: 33
      Eye Window: ________________XXXXXXX_________________
    Uplink 28:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 29:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 30:
      Optimal Phase: 3
      Window Length: 34
      Eye Window: _____________________XXXXXX_____________
    Uplink 31:
      Optimal Phase: 2
      Window Length: 33
      Eye Window: ___________________XXXXXXX______________

==============================================OOO==============================================
10:24:20:setup_element:INFO:	Performing Elink synchronization
10:24:20:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:24:20:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:24:20:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
10:24:20:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
10:24:20:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
10:24:20:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
10:24:20:ST3_emu_feb:DEBUG:	Chip address:  	0x1
10:24:20:ST3_emu_feb:DEBUG:	Chip address:  	0x3
10:24:20:ST3_emu_feb:DEBUG:	Chip address:  	0x5
10:24:20:ST3_emu_feb:DEBUG:	Chip address:  	0x7
10:24:20:febtest:INFO:	Init all SMX (CSA): 30
10:24:27:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:24:28:febtest:INFO:	30-01 | XA-000-09-004-015-012-022-12 |  18.7 | 1165.6
10:24:28:febtest:INFO:	28-03 | XA-000-09-004-015-012-023-12 |  18.7 | 1165.6
10:24:28:febtest:INFO:	26-05 | XA-000-09-004-015-003-021-08 |  31.4 | 1130.0
10:24:28:febtest:INFO:	24-07 | XA-000-09-004-015-009-022-07 |  31.4 | 1130.0
10:24:29:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
10:24:32:ST3_smx:INFO:	chip: 30-1 	 18.745682 C 	 1183.292940 mV
10:24:32:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:24:32:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:24:32:ST3_smx:INFO:		Electrons
10:24:36:ST3_smx:INFO:	Total # of broken channels: 9
10:24:36:ST3_smx:INFO:	List of broken channels: [11, 12, 15, 18, 40, 73, 78, 103, 111]
10:24:36:ST3_smx:INFO:	Total # of broken channels: 0
10:24:36:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
10:24:38:ST3_smx:INFO:	chip: 28-3 	 18.745682 C 	 1171.483840 mV
10:24:38:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:24:38:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:24:38:ST3_smx:INFO:		Electrons
10:24:43:ST3_smx:INFO:	Total # of broken channels: 4
10:24:43:ST3_smx:INFO:	List of broken channels: [4, 39, 40, 56]
10:24:43:ST3_smx:INFO:	Total # of broken channels: 0
10:24:43:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
10:24:44:ST3_smx:INFO:	chip: 26-5 	 31.389742 C 	 1141.874115 mV
10:24:44:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:24:44:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:24:44:ST3_smx:INFO:		Electrons
10:24:49:ST3_smx:INFO:	Total # of broken channels: 11
10:24:49:ST3_smx:INFO:	List of broken channels: [2, 32, 41, 53, 76, 80, 83, 84, 86, 93, 108]
10:24:49:ST3_smx:INFO:	Total # of broken channels: 0
10:24:49:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
10:24:51:ST3_smx:INFO:	chip: 24-7 	 34.556970 C 	 1135.937260 mV
10:24:51:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:24:51:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:24:51:ST3_smx:INFO:		Electrons
10:24:56:ST3_smx:INFO:	Total # of broken channels: 4
10:24:56:ST3_smx:INFO:	List of broken channels: [9, 53, 80, 121]
10:24:56:ST3_smx:INFO:	Total # of broken channels: 0
10:24:56:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
10:24:56:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:24:56:febtest:INFO:	30-01 | XA-000-09-004-015-012-022-12 |  18.7 | 1201.0
10:24:56:febtest:INFO:	28-03 | XA-000-09-004-015-012-023-12 |  21.9 | 1195.1
10:24:57:febtest:INFO:	26-05 | XA-000-09-004-015-003-021-08 |  31.4 | 1159.7
10:24:57:febtest:INFO:	24-07 | XA-000-09-004-015-009-022-07 |  34.6 | 1153.7
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_06_10-10_24_09
OPERATOR  : Robert V.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2432| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.6980', '1.848', '1.0540']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0230', '1.850', '1.2980']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0020', '1.850', '0.2708']
Comment