DTL-STS tests database

FEB_2442 20.06.25 12:58:35

link:
...SMX_0.root
link:
...SMX_2.root
link:
...SMX_4.root
link:
...SMX_6.root
link: XA-000-09-004-016-010-024-03
...SMX_1.root
link: XA-000-09-004-016-014-003-02
...SMX_3.root
link: XA-000-09-004-016-013-026-11
...SMX_5.root
link: XA-000-09-004-016-004-023-10
...SMX_7.root
link: XA-000-09-004-016-004-023-10
...VddmCSAstatus.root
Info
            12:58:35:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:58:35:ST3_Shared:INFO:	                       FEB-Microcable                       
12:58:35:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:58:35:febtest:INFO:	Testing FEB with SN 2442
==============================================OOO==============================================
12:58:37:smx_tester:INFO:	Scanning setup
12:58:37:elinks:INFO:	Disabling clock on downlink 0
12:58:37:elinks:INFO:	Disabling clock on downlink 1
12:58:37:elinks:INFO:	Disabling clock on downlink 2
12:58:37:elinks:INFO:	Disabling clock on downlink 3
12:58:37:elinks:INFO:	Disabling clock on downlink 4
12:58:37:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:58:37:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
12:58:37:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:58:37:elinks:INFO:	Disabling clock on downlink 0
12:58:37:elinks:INFO:	Disabling clock on downlink 1
12:58:37:elinks:INFO:	Disabling clock on downlink 2
12:58:37:elinks:INFO:	Disabling clock on downlink 3
12:58:37:elinks:INFO:	Disabling clock on downlink 4
12:58:37:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:58:37:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
12:58:37:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:58:37:elinks:INFO:	Disabling clock on downlink 0
12:58:37:elinks:INFO:	Disabling clock on downlink 1
12:58:37:elinks:INFO:	Disabling clock on downlink 2
12:58:37:elinks:INFO:	Disabling clock on downlink 3
12:58:37:elinks:INFO:	Disabling clock on downlink 4
12:58:37:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:58:37:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:58:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
12:58:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
12:58:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
12:58:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
12:58:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
12:58:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
12:58:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
12:58:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
12:58:37:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:58:37:elinks:INFO:	Disabling clock on downlink 0
12:58:37:elinks:INFO:	Disabling clock on downlink 1
12:58:37:elinks:INFO:	Disabling clock on downlink 2
12:58:37:elinks:INFO:	Disabling clock on downlink 3
12:58:37:elinks:INFO:	Disabling clock on downlink 4
12:58:37:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:58:37:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
12:58:37:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
12:58:37:elinks:INFO:	Disabling clock on downlink 0
12:58:37:elinks:INFO:	Disabling clock on downlink 1
12:58:37:elinks:INFO:	Disabling clock on downlink 2
12:58:37:elinks:INFO:	Disabling clock on downlink 3
12:58:37:elinks:INFO:	Disabling clock on downlink 4
12:58:37:setup_element:INFO:	Checking SOS, encoding_mode: SOS
12:58:37:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
12:58:38:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
12:58:38:setup_element:INFO:	Scanning clock phase
12:58:38:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:58:38:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:58:38:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
12:58:38:setup_element:INFO:	Eye window for uplink 24: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
12:58:38:setup_element:INFO:	Eye window for uplink 25: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
12:58:38:setup_element:INFO:	Eye window for uplink 26: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
12:58:38:setup_element:INFO:	Eye window for uplink 27: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
12:58:38:setup_element:INFO:	Eye window for uplink 28: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
12:58:38:setup_element:INFO:	Eye window for uplink 29: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
12:58:38:setup_element:INFO:	Eye window for uplink 30: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
12:58:38:setup_element:INFO:	Eye window for uplink 31: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
12:58:38:setup_element:INFO:	Setting the clock phase to 32 for group 0, downlink 2
==============================================OOO==============================================
12:58:38:setup_element:INFO:	Scanning data phases
12:58:38:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:58:38:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:58:43:setup_element:INFO:	Data phase scan results for group 0, downlink 2
12:58:43:setup_element:INFO:	Eye window for uplink 24: ________________XXXXXX__________________
Data delay found: 38
12:58:43:setup_element:INFO:	Eye window for uplink 25: __________________XXXXX_________________
Data delay found: 0
12:58:43:setup_element:INFO:	Eye window for uplink 26: __________________XXXXXX________________
Data delay found: 0
12:58:43:setup_element:INFO:	Eye window for uplink 27: ___________________XXXXXXX______________
Data delay found: 2
12:58:43:setup_element:INFO:	Eye window for uplink 28: ___________________XXXXXXX______________
Data delay found: 2
12:58:43:setup_element:INFO:	Eye window for uplink 29: ___________________XXXXXX_______________
Data delay found: 1
12:58:43:setup_element:INFO:	Eye window for uplink 30: ___________________XXXXXX_______________
Data delay found: 1
12:58:43:setup_element:INFO:	Eye window for uplink 31: _________________XXXXXX_________________
Data delay found: 39
12:58:43:setup_element:INFO:	Setting the data phase to 38 for uplink 24
12:58:43:setup_element:INFO:	Setting the data phase to 0 for uplink 25
12:58:43:setup_element:INFO:	Setting the data phase to 0 for uplink 26
12:58:43:setup_element:INFO:	Setting the data phase to 2 for uplink 27
12:58:43:setup_element:INFO:	Setting the data phase to 2 for uplink 28
12:58:43:setup_element:INFO:	Setting the data phase to 1 for uplink 29
12:58:43:setup_element:INFO:	Setting the data phase to 1 for uplink 30
12:58:43:setup_element:INFO:	Setting the data phase to 39 for uplink 31
==============================================OOO==============================================
12:58:43:setup_element:INFO:	Beginning SMX ASICs map scan
12:58:43:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:58:43:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:58:43:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
12:58:43:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
12:58:43:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
12:58:44:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
12:58:44:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
12:58:44:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
12:58:44:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
12:58:44:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
12:58:44:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
12:58:45:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
12:58:45:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
12:58:46:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 32
    Window Length: 70
    Eye Windows:
      Uplink 24: _____________________________________________________________________XXXXXXXX___
      Uplink 25: _____________________________________________________________________XXXXXXXX___
      Uplink 26: _____________________________________________________________________XXXXXXXXX__
      Uplink 27: _____________________________________________________________________XXXXXXXXX__
      Uplink 28: ____________________________________________________________________XXXXXXXXX___
      Uplink 29: ____________________________________________________________________XXXXXXXXX___
      Uplink 30: ____________________________________________________________________XXXXXXX_____
      Uplink 31: ____________________________________________________________________XXXXXXX_____
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 38
      Window Length: 34
      Eye Window: ________________XXXXXX__________________
    Uplink 25:
      Optimal Phase: 0
      Window Length: 35
      Eye Window: __________________XXXXX_________________
    Uplink 26:
      Optimal Phase: 0
      Window Length: 34
      Eye Window: __________________XXXXXX________________
    Uplink 27:
      Optimal Phase: 2
      Window Length: 33
      Eye Window: ___________________XXXXXXX______________
    Uplink 28:
      Optimal Phase: 2
      Window Length: 33
      Eye Window: ___________________XXXXXXX______________
    Uplink 29:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 30:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 31:
      Optimal Phase: 39
      Window Length: 34
      Eye Window: _________________XXXXXX_________________

==============================================OOO==============================================
12:58:46:setup_element:INFO:	Performing Elink synchronization
12:58:46:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
12:58:46:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:58:46:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
12:58:46:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
12:58:46:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
12:58:46:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
12:58:46:ST3_emu_feb:DEBUG:	Chip address:  	0x1
12:58:46:ST3_emu_feb:DEBUG:	Chip address:  	0x3
12:58:46:ST3_emu_feb:DEBUG:	Chip address:  	0x5
12:58:46:ST3_emu_feb:DEBUG:	Chip address:  	0x7
12:58:46:febtest:INFO:	Init all SMX (CSA): 30
12:58:54:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
12:58:54:febtest:INFO:	30-01 | XA-000-09-004-016-010-024-03 |  28.2 | 1147.8
12:58:54:febtest:INFO:	28-03 | XA-000-09-004-016-014-003-02 |  44.1 | 1088.3
12:58:55:febtest:INFO:	26-05 | XA-000-09-004-016-013-026-11 |   9.3 | 1195.1
12:58:55:febtest:INFO:	24-07 | XA-000-09-004-016-004-023-10 |  21.9 | 1165.6
12:58:56:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
12:58:58:ST3_smx:INFO:	chip: 30-1 	 28.225000 C 	 1159.654860 mV
12:58:58:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:58:58:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:58:58:ST3_smx:INFO:		Electrons
12:59:03:ST3_smx:INFO:	Total # of broken channels: 5
12:59:03:ST3_smx:INFO:	List of broken channels: [1, 14, 24, 29, 111]
12:59:03:ST3_smx:INFO:	Total # of broken channels: 0
12:59:03:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
12:59:05:ST3_smx:INFO:	chip: 28-3 	 40.898880 C 	 1100.211760 mV
12:59:05:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:59:05:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:59:05:ST3_smx:INFO:		Electrons
12:59:09:ST3_smx:INFO:	Total # of broken channels: 8
12:59:09:ST3_smx:INFO:	List of broken channels: [4, 44, 53, 58, 63, 78, 79, 94]
12:59:09:ST3_smx:INFO:	Total # of broken channels: 0
12:59:09:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
12:59:11:ST3_smx:INFO:	chip: 26-5 	 9.288730 C 	 1206.851500 mV
12:59:11:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:59:11:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:59:11:ST3_smx:INFO:		Electrons
12:59:16:ST3_smx:INFO:	Total # of broken channels: 5
12:59:16:ST3_smx:INFO:	List of broken channels: [53, 81, 82, 86, 98]
12:59:16:ST3_smx:INFO:	Total # of broken channels: 0
12:59:16:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
12:59:18:ST3_smx:INFO:	chip: 24-7 	 21.902970 C 	 1177.390875 mV
12:59:18:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:59:18:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
12:59:18:ST3_smx:INFO:		Electrons
12:59:23:ST3_smx:INFO:	Total # of broken channels: 5
12:59:23:ST3_smx:INFO:	List of broken channels: [4, 10, 96, 106, 123]
12:59:23:ST3_smx:INFO:	Total # of broken channels: 0
12:59:23:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
12:59:23:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
12:59:23:febtest:INFO:	30-01 | XA-000-09-004-016-010-024-03 |  25.1 | 1183.3
12:59:23:febtest:INFO:	28-03 | XA-000-09-004-016-014-003-02 |  44.1 | 1118.1
12:59:24:febtest:INFO:	26-05 | XA-000-09-004-016-013-026-11 |  12.4 | 1230.3
12:59:24:febtest:INFO:	24-07 | XA-000-09-004-016-004-023-10 |  25.1 | 1195.1
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_06_20-12_58_35
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2442| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.449', '0.7830', '1.846', '1.4720']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0080', '1.850', '1.3100']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9885', '1.850', '0.2625']
Comment