DTL-STS tests database

FEB_2447 13.06.25 13:03:06

link:
...SMX_0.root
link:
...SMX_2.root
link:
...SMX_4.root
link:
...SMX_6.root
link: XA-000-09-004-016-010-003-04
...SMX_1.root
link: XA-000-09-004-016-013-003-12
...SMX_3.root
link: XA-000-09-004-016-010-002-04
...SMX_5.root
link: XA-000-09-004-016-007-007-03
...SMX_7.root
link: XA-000-09-004-016-007-007-03
...VddmCSAstatus.root
Info
            13:03:06:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:03:06:ST3_Shared:INFO:	                       FEB-Microcable                       
13:03:06:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:03:06:febtest:INFO:	Testing FEB with SN 2447
==============================================OOO==============================================
13:03:08:smx_tester:INFO:	Scanning setup
13:03:08:elinks:INFO:	Disabling clock on downlink 0
13:03:08:elinks:INFO:	Disabling clock on downlink 1
13:03:08:elinks:INFO:	Disabling clock on downlink 2
13:03:08:elinks:INFO:	Disabling clock on downlink 3
13:03:08:elinks:INFO:	Disabling clock on downlink 4
13:03:08:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:03:08:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
13:03:08:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:03:08:elinks:INFO:	Disabling clock on downlink 0
13:03:08:elinks:INFO:	Disabling clock on downlink 1
13:03:08:elinks:INFO:	Disabling clock on downlink 2
13:03:08:elinks:INFO:	Disabling clock on downlink 3
13:03:08:elinks:INFO:	Disabling clock on downlink 4
13:03:08:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:03:08:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
13:03:08:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:03:08:elinks:INFO:	Disabling clock on downlink 0
13:03:08:elinks:INFO:	Disabling clock on downlink 1
13:03:08:elinks:INFO:	Disabling clock on downlink 2
13:03:08:elinks:INFO:	Disabling clock on downlink 3
13:03:08:elinks:INFO:	Disabling clock on downlink 4
13:03:08:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:03:08:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:03:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
13:03:08:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
13:03:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
13:03:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
13:03:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
13:03:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
13:03:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
13:03:09:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
13:03:09:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:03:09:elinks:INFO:	Disabling clock on downlink 0
13:03:09:elinks:INFO:	Disabling clock on downlink 1
13:03:09:elinks:INFO:	Disabling clock on downlink 2
13:03:09:elinks:INFO:	Disabling clock on downlink 3
13:03:09:elinks:INFO:	Disabling clock on downlink 4
13:03:09:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:03:09:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
13:03:09:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:03:09:elinks:INFO:	Disabling clock on downlink 0
13:03:09:elinks:INFO:	Disabling clock on downlink 1
13:03:09:elinks:INFO:	Disabling clock on downlink 2
13:03:09:elinks:INFO:	Disabling clock on downlink 3
13:03:09:elinks:INFO:	Disabling clock on downlink 4
13:03:09:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:03:09:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
13:03:09:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
13:03:09:setup_element:INFO:	Scanning clock phase
13:03:09:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:03:09:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:03:09:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
13:03:09:setup_element:INFO:	Eye window for uplink 24: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:03:09:setup_element:INFO:	Eye window for uplink 25: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:03:09:setup_element:INFO:	Eye window for uplink 26: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
13:03:09:setup_element:INFO:	Eye window for uplink 27: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
13:03:09:setup_element:INFO:	Eye window for uplink 28: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
13:03:09:setup_element:INFO:	Eye window for uplink 29: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
13:03:09:setup_element:INFO:	Eye window for uplink 30: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
13:03:09:setup_element:INFO:	Eye window for uplink 31: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
13:03:09:setup_element:INFO:	Setting the clock phase to 32 for group 0, downlink 2
==============================================OOO==============================================
13:03:09:setup_element:INFO:	Scanning data phases
13:03:09:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:03:09:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:03:14:setup_element:INFO:	Data phase scan results for group 0, downlink 2
13:03:14:setup_element:INFO:	Eye window for uplink 24: _____________XXXXXX_____________________
Data delay found: 35
13:03:15:setup_element:INFO:	Eye window for uplink 25: _______________XXXXXX___________________
Data delay found: 37
13:03:15:setup_element:INFO:	Eye window for uplink 26: _________________XXXXXX_________________
Data delay found: 39
13:03:15:setup_element:INFO:	Eye window for uplink 27: ___________________XXXXXX_______________
Data delay found: 1
13:03:15:setup_element:INFO:	Eye window for uplink 28: __________________XXXXXXX_______________
Data delay found: 1
13:03:15:setup_element:INFO:	Eye window for uplink 29: _________________XXXXXXX________________
Data delay found: 0
13:03:15:setup_element:INFO:	Eye window for uplink 30: ___________________XXXXXX_______________
Data delay found: 1
13:03:15:setup_element:INFO:	Eye window for uplink 31: _________________XXXXXXX________________
Data delay found: 0
13:03:15:setup_element:INFO:	Setting the data phase to 35 for uplink 24
13:03:15:setup_element:INFO:	Setting the data phase to 37 for uplink 25
13:03:15:setup_element:INFO:	Setting the data phase to 39 for uplink 26
13:03:15:setup_element:INFO:	Setting the data phase to 1 for uplink 27
13:03:15:setup_element:INFO:	Setting the data phase to 1 for uplink 28
13:03:15:setup_element:INFO:	Setting the data phase to 0 for uplink 29
13:03:15:setup_element:INFO:	Setting the data phase to 1 for uplink 30
13:03:15:setup_element:INFO:	Setting the data phase to 0 for uplink 31
==============================================OOO==============================================
13:03:15:setup_element:INFO:	Beginning SMX ASICs map scan
13:03:15:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:03:15:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:03:15:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
13:03:15:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
13:03:15:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
13:03:15:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
13:03:15:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
13:03:15:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
13:03:15:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
13:03:16:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
13:03:16:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
13:03:16:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
13:03:16:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
13:03:17:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 32
    Window Length: 70
    Eye Windows:
      Uplink 24: _____________________________________________________________________XXXXXXXX___
      Uplink 25: _____________________________________________________________________XXXXXXXX___
      Uplink 26: _____________________________________________________________________XXXXXXXXX__
      Uplink 27: _____________________________________________________________________XXXXXXXXX__
      Uplink 28: ____________________________________________________________________XXXXXXXXX___
      Uplink 29: ____________________________________________________________________XXXXXXXXX___
      Uplink 30: ____________________________________________________________________XXXXXXXX____
      Uplink 31: ____________________________________________________________________XXXXXXXX____
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 35
      Window Length: 34
      Eye Window: _____________XXXXXX_____________________
    Uplink 25:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 26:
      Optimal Phase: 39
      Window Length: 34
      Eye Window: _________________XXXXXX_________________
    Uplink 27:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 28:
      Optimal Phase: 1
      Window Length: 33
      Eye Window: __________________XXXXXXX_______________
    Uplink 29:
      Optimal Phase: 0
      Window Length: 33
      Eye Window: _________________XXXXXXX________________
    Uplink 30:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 31:
      Optimal Phase: 0
      Window Length: 33
      Eye Window: _________________XXXXXXX________________

==============================================OOO==============================================
13:03:17:setup_element:INFO:	Performing Elink synchronization
13:03:17:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:03:17:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:03:17:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
13:03:17:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
13:03:17:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
13:03:17:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
13:03:17:ST3_emu_feb:DEBUG:	Chip address:  	0x1
13:03:18:ST3_emu_feb:DEBUG:	Chip address:  	0x3
13:03:18:ST3_emu_feb:DEBUG:	Chip address:  	0x5
13:03:18:ST3_emu_feb:DEBUG:	Chip address:  	0x7
13:03:18:febtest:INFO:	Init all SMX (CSA): 30
13:03:25:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
13:03:26:febtest:INFO:	30-01 | XA-000-09-004-016-010-003-04 |  34.6 | 1153.7
13:03:26:febtest:INFO:	28-03 | XA-000-09-004-016-013-003-12 |  37.7 | 1130.0
13:03:26:febtest:INFO:	26-05 | XA-000-09-004-016-010-002-04 |  34.6 | 1147.8
13:03:26:febtest:INFO:	24-07 | XA-000-09-004-016-007-007-03 |  31.4 | 1153.7
13:03:27:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
13:03:29:ST3_smx:INFO:	chip: 30-1 	 34.556970 C 	 1165.571835 mV
13:03:29:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:03:29:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:03:29:ST3_smx:INFO:		Electrons
13:03:34:ST3_smx:INFO:	Total # of broken channels: 6
13:03:34:ST3_smx:INFO:	List of broken channels: [6, 18, 34, 58, 101, 102]
13:03:34:ST3_smx:INFO:	Total # of broken channels: 0
13:03:34:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
13:03:36:ST3_smx:INFO:	chip: 28-3 	 37.726682 C 	 1141.874115 mV
13:03:36:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:03:36:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:03:36:ST3_smx:INFO:		Electrons
13:03:41:ST3_smx:INFO:	Total # of broken channels: 4
13:03:41:ST3_smx:INFO:	List of broken channels: [46, 51, 68, 119]
13:03:41:ST3_smx:INFO:	Total # of broken channels: 0
13:03:41:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
13:03:43:ST3_smx:INFO:	chip: 26-5 	 34.556970 C 	 1153.732915 mV
13:03:43:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:03:43:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:03:43:ST3_smx:INFO:		Electrons
13:03:47:ST3_smx:INFO:	Total # of broken channels: 7
13:03:47:ST3_smx:INFO:	List of broken channels: [17, 33, 63, 67, 81, 104, 106]
13:03:47:ST3_smx:INFO:	Total # of broken channels: 0
13:03:47:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
13:03:49:ST3_smx:INFO:	chip: 24-7 	 31.389742 C 	 1165.571835 mV
13:03:49:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:03:49:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
13:03:49:ST3_smx:INFO:		Electrons
13:03:54:ST3_smx:INFO:	Total # of broken channels: 6
13:03:54:ST3_smx:INFO:	List of broken channels: [2, 37, 50, 62, 121, 124]
13:03:54:ST3_smx:INFO:	Total # of broken channels: 0
13:03:54:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
13:03:54:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
13:03:55:febtest:INFO:	30-01 | XA-000-09-004-016-010-003-04 |  34.6 | 1183.3
13:03:55:febtest:INFO:	28-03 | XA-000-09-004-016-013-003-12 |  37.7 | 1159.7
13:03:55:febtest:INFO:	26-05 | XA-000-09-004-016-010-002-04 |  34.6 | 1177.4
13:03:55:febtest:INFO:	24-07 | XA-000-09-004-016-007-007-03 |  34.6 | 1183.3
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_06_13-13_03_06
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2447| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.6976', '1.848', '1.1380']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0130', '1.850', '1.2980']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9931', '1.851', '0.2666']
Comment