DTL-STS tests database

FEB_2456 01.07.25 08:27:37

link:
...SMX_0.root
link:
...SMX_2.root
link:
...SMX_4.root
link:
...SMX_6.root
link: XA-000-09-004-016-009-006-10
...SMX_1.root
link: XA-000-09-004-016-006-006-14
...SMX_3.root
link: XA-000-09-004-016-009-013-10
...SMX_5.root
link: XA-000-09-004-016-006-013-14
...SMX_7.root
link: XA-000-09-004-016-006-013-14
...VddmCSAstatus.root
Info
            08:27:37:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:27:37:ST3_Shared:INFO:	                       FEB-Microcable                       
08:27:37:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:27:37:febtest:INFO:	Testing FEB with SN 2456
==============================================OOO==============================================
08:27:39:smx_tester:INFO:	Scanning setup
08:27:39:elinks:INFO:	Disabling clock on downlink 0
08:27:39:elinks:INFO:	Disabling clock on downlink 1
08:27:39:elinks:INFO:	Disabling clock on downlink 2
08:27:39:elinks:INFO:	Disabling clock on downlink 3
08:27:39:elinks:INFO:	Disabling clock on downlink 4
08:27:39:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:27:39:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
08:27:39:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:27:39:elinks:INFO:	Disabling clock on downlink 0
08:27:39:elinks:INFO:	Disabling clock on downlink 1
08:27:39:elinks:INFO:	Disabling clock on downlink 2
08:27:39:elinks:INFO:	Disabling clock on downlink 3
08:27:39:elinks:INFO:	Disabling clock on downlink 4
08:27:39:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:27:39:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
08:27:39:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:27:39:elinks:INFO:	Disabling clock on downlink 0
08:27:39:elinks:INFO:	Disabling clock on downlink 1
08:27:39:elinks:INFO:	Disabling clock on downlink 2
08:27:39:elinks:INFO:	Disabling clock on downlink 3
08:27:39:elinks:INFO:	Disabling clock on downlink 4
08:27:39:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:27:39:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:27:39:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
08:27:39:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
08:27:39:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
08:27:39:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
08:27:39:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
08:27:39:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
08:27:39:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
08:27:39:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
08:27:39:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:27:39:elinks:INFO:	Disabling clock on downlink 0
08:27:39:elinks:INFO:	Disabling clock on downlink 1
08:27:39:elinks:INFO:	Disabling clock on downlink 2
08:27:39:elinks:INFO:	Disabling clock on downlink 3
08:27:39:elinks:INFO:	Disabling clock on downlink 4
08:27:39:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:27:39:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
08:27:39:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:27:39:elinks:INFO:	Disabling clock on downlink 0
08:27:39:elinks:INFO:	Disabling clock on downlink 1
08:27:39:elinks:INFO:	Disabling clock on downlink 2
08:27:39:elinks:INFO:	Disabling clock on downlink 3
08:27:39:elinks:INFO:	Disabling clock on downlink 4
08:27:40:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:27:40:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
08:27:40:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
08:27:40:setup_element:INFO:	Scanning clock phase
08:27:40:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:27:40:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:27:40:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
08:27:40:setup_element:INFO:	Eye window for uplink 24: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:27:40:setup_element:INFO:	Eye window for uplink 25: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:27:40:setup_element:INFO:	Eye window for uplink 26: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:27:40:setup_element:INFO:	Eye window for uplink 27: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:27:40:setup_element:INFO:	Eye window for uplink 28: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
08:27:40:setup_element:INFO:	Eye window for uplink 29: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
08:27:40:setup_element:INFO:	Eye window for uplink 30: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
08:27:40:setup_element:INFO:	Eye window for uplink 31: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
08:27:40:setup_element:INFO:	Setting the clock phase to 31 for group 0, downlink 2
==============================================OOO==============================================
08:27:40:setup_element:INFO:	Scanning data phases
08:27:40:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:27:40:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:27:45:setup_element:INFO:	Data phase scan results for group 0, downlink 2
08:27:45:setup_element:INFO:	Eye window for uplink 24: ___________XXXXX_X______________________
Data delay found: 34
08:27:45:setup_element:INFO:	Eye window for uplink 25: _____________XXXXX______________________
Data delay found: 35
08:27:45:setup_element:INFO:	Eye window for uplink 26: _____________XXXXXX_X___________________
Data delay found: 36
08:27:45:setup_element:INFO:	Eye window for uplink 27: ______________XXXXXXXX__________________
Data delay found: 37
08:27:45:setup_element:INFO:	Eye window for uplink 28: _______________XXXXXXX__________________
Data delay found: 38
08:27:45:setup_element:INFO:	Eye window for uplink 29: _______________XXXXXXX__________________
Data delay found: 38
08:27:45:setup_element:INFO:	Eye window for uplink 30: ________________XXXXXXX_X_______________
Data delay found: 0
08:27:45:setup_element:INFO:	Eye window for uplink 31: _______________XXXXXXXX_________________
Data delay found: 38
08:27:45:setup_element:INFO:	Setting the data phase to 34 for uplink 24
08:27:45:setup_element:INFO:	Setting the data phase to 35 for uplink 25
08:27:45:setup_element:INFO:	Setting the data phase to 36 for uplink 26
08:27:45:setup_element:INFO:	Setting the data phase to 37 for uplink 27
08:27:45:setup_element:INFO:	Setting the data phase to 38 for uplink 28
08:27:45:setup_element:INFO:	Setting the data phase to 38 for uplink 29
08:27:46:setup_element:INFO:	Setting the data phase to 0 for uplink 30
08:27:46:setup_element:INFO:	Setting the data phase to 38 for uplink 31
==============================================OOO==============================================
08:27:46:setup_element:INFO:	Beginning SMX ASICs map scan
08:27:46:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:27:46:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:27:46:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
08:27:46:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
08:27:46:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
08:27:46:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
08:27:46:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
08:27:46:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
08:27:46:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
08:27:46:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
08:27:47:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
08:27:47:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
08:27:47:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
08:27:48:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 31
    Window Length: 71
    Eye Windows:
      Uplink 24: ____________________________________________________________________XXXXXXXX____
      Uplink 25: ____________________________________________________________________XXXXXXXX____
      Uplink 26: ____________________________________________________________________XXXXXXXX____
      Uplink 27: ____________________________________________________________________XXXXXXXX____
      Uplink 28: ___________________________________________________________________XXXXXXXX_____
      Uplink 29: ___________________________________________________________________XXXXXXXX_____
      Uplink 30: _____________________________________________________________________XXXXXXX____
      Uplink 31: _____________________________________________________________________XXXXXXX____
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 34
      Window Length: 33
      Eye Window: ___________XXXXX_X______________________
    Uplink 25:
      Optimal Phase: 35
      Window Length: 35
      Eye Window: _____________XXXXX______________________
    Uplink 26:
      Optimal Phase: 36
      Window Length: 32
      Eye Window: _____________XXXXXX_X___________________
    Uplink 27:
      Optimal Phase: 37
      Window Length: 32
      Eye Window: ______________XXXXXXXX__________________
    Uplink 28:
      Optimal Phase: 38
      Window Length: 33
      Eye Window: _______________XXXXXXX__________________
    Uplink 29:
      Optimal Phase: 38
      Window Length: 33
      Eye Window: _______________XXXXXXX__________________
    Uplink 30:
      Optimal Phase: 0
      Window Length: 31
      Eye Window: ________________XXXXXXX_X_______________
    Uplink 31:
      Optimal Phase: 38
      Window Length: 32
      Eye Window: _______________XXXXXXXX_________________

==============================================OOO==============================================
08:27:48:setup_element:INFO:	Performing Elink synchronization
08:27:48:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:27:48:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:27:48:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
08:27:48:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
08:27:48:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
08:27:48:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
08:27:48:ST3_emu_feb:DEBUG:	Chip address:  	0x1
08:27:49:ST3_emu_feb:DEBUG:	Chip address:  	0x3
08:27:49:ST3_emu_feb:DEBUG:	Chip address:  	0x5
08:27:49:ST3_emu_feb:DEBUG:	Chip address:  	0x7
08:27:49:febtest:INFO:	Init all SMX (CSA): 30
08:27:56:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:27:56:febtest:INFO:	30-01 | XA-000-09-004-016-009-006-10 |  34.6 | 1171.5
08:27:56:febtest:INFO:	28-03 | XA-000-09-004-016-006-006-14 |  37.7 | 1153.7
08:27:56:febtest:INFO:	26-05 | XA-000-09-004-016-009-013-10 |  37.7 | 1153.7
08:27:57:febtest:INFO:	24-07 | XA-000-09-004-016-006-013-14 |  37.7 | 1159.7
08:27:58:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
08:28:00:ST3_smx:INFO:	chip: 30-1 	 34.556970 C 	 1183.292940 mV
08:28:00:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:28:00:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:28:00:ST3_smx:INFO:		Electrons
08:28:05:ST3_smx:INFO:	Total # of broken channels: 8
08:28:05:ST3_smx:INFO:	List of broken channels: [3, 25, 37, 75, 109, 112, 116, 127]
08:28:05:ST3_smx:INFO:	Total # of broken channels: 0
08:28:05:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
08:28:06:ST3_smx:INFO:	chip: 28-3 	 37.726682 C 	 1159.654860 mV
08:28:06:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:28:06:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:28:06:ST3_smx:INFO:		Electrons
08:28:11:ST3_smx:INFO:	Total # of broken channels: 8
08:28:11:ST3_smx:INFO:	List of broken channels: [13, 26, 34, 61, 68, 74, 99, 100]
08:28:11:ST3_smx:INFO:	Total # of broken channels: 0
08:28:11:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
08:28:13:ST3_smx:INFO:	chip: 26-5 	 40.898880 C 	 1159.654860 mV
08:28:13:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:28:13:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:28:13:ST3_smx:INFO:		Electrons
08:28:18:ST3_smx:INFO:	Total # of broken channels: 9
08:28:18:ST3_smx:INFO:	List of broken channels: [2, 7, 24, 31, 57, 64, 86, 112, 114]
08:28:18:ST3_smx:INFO:	Total # of broken channels: 0
08:28:18:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
08:28:19:ST3_smx:INFO:	chip: 24-7 	 37.726682 C 	 1165.571835 mV
08:28:19:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:28:19:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:28:19:ST3_smx:INFO:		Electrons
08:28:24:ST3_smx:INFO:	Total # of broken channels: 15
08:28:24:ST3_smx:INFO:	List of broken channels: [7, 14, 15, 40, 45, 49, 55, 62, 77, 84, 85, 87, 88, 99, 115]
08:28:24:ST3_smx:INFO:	Total # of broken channels: 0
08:28:24:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
08:28:24:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:28:25:febtest:INFO:	30-01 | XA-000-09-004-016-009-006-10 |  34.6 | 1206.9
08:28:25:febtest:INFO:	28-03 | XA-000-09-004-016-006-006-14 |  37.7 | 1183.3
08:28:25:febtest:INFO:	26-05 | XA-000-09-004-016-009-013-10 |  40.9 | 1183.3
08:28:25:febtest:INFO:	24-07 | XA-000-09-004-016-006-013-14 |  40.9 | 1183.3
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_07_01-08_27_37
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2456| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.7449', '1.847', '1.0050']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0140', '1.850', '1.3180']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0040', '1.850', '0.2701']
Comment