DTL-STS tests database

FEB_2466 24.07.25 08:39:51

link:
...SMX_0.root
link:
...SMX_2.root
link:
...SMX_4.root
link:
...SMX_6.root
link: XA-000-09-004-043-013-005-10
...SMX_1.root
link: XA-000-09-004-043-010-004-02
...SMX_3.root
link: XA-000-09-004-043-013-004-10
...SMX_5.root
link: XA-000-09-004-043-010-013-02
...SMX_7.root
link: XA-000-09-004-043-010-013-02
...VddmCSAstatus.root
TextEdit.txt
            08:39:51:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:39:51:ST3_Shared:INFO:	                       FEB-Microcable                       
08:39:51:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
08:39:51:febtest:INFO:	Testing FEB with SN 2466
==============================================OOO==============================================
08:39:52:smx_tester:INFO:	Scanning setup
08:39:52:elinks:INFO:	Disabling clock on downlink 0
08:39:52:elinks:INFO:	Disabling clock on downlink 1
08:39:52:elinks:INFO:	Disabling clock on downlink 2
08:39:52:elinks:INFO:	Disabling clock on downlink 3
08:39:52:elinks:INFO:	Disabling clock on downlink 4
08:39:52:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:39:52:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
08:39:52:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:39:52:elinks:INFO:	Disabling clock on downlink 0
08:39:52:elinks:INFO:	Disabling clock on downlink 1
08:39:52:elinks:INFO:	Disabling clock on downlink 2
08:39:52:elinks:INFO:	Disabling clock on downlink 3
08:39:52:elinks:INFO:	Disabling clock on downlink 4
08:39:52:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:39:52:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
08:39:53:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:39:53:elinks:INFO:	Disabling clock on downlink 0
08:39:53:elinks:INFO:	Disabling clock on downlink 1
08:39:53:elinks:INFO:	Disabling clock on downlink 2
08:39:53:elinks:INFO:	Disabling clock on downlink 3
08:39:53:elinks:INFO:	Disabling clock on downlink 4
08:39:53:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:39:53:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:39:53:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
08:39:53:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
08:39:53:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
08:39:53:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
08:39:53:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
08:39:53:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
08:39:53:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
08:39:53:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
08:39:53:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:39:53:elinks:INFO:	Disabling clock on downlink 0
08:39:53:elinks:INFO:	Disabling clock on downlink 1
08:39:53:elinks:INFO:	Disabling clock on downlink 2
08:39:53:elinks:INFO:	Disabling clock on downlink 3
08:39:53:elinks:INFO:	Disabling clock on downlink 4
08:39:53:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:39:53:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
08:39:53:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
08:39:53:elinks:INFO:	Disabling clock on downlink 0
08:39:53:elinks:INFO:	Disabling clock on downlink 1
08:39:53:elinks:INFO:	Disabling clock on downlink 2
08:39:53:elinks:INFO:	Disabling clock on downlink 3
08:39:53:elinks:INFO:	Disabling clock on downlink 4
08:39:53:setup_element:INFO:	Checking SOS, encoding_mode: SOS
08:39:53:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
08:39:53:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
08:39:53:setup_element:INFO:	Scanning clock phase
08:39:53:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:39:53:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:39:53:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
08:39:53:setup_element:INFO:	Eye window for uplink 24: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
08:39:53:setup_element:INFO:	Eye window for uplink 25: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
08:39:53:setup_element:INFO:	Eye window for uplink 26: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:39:53:setup_element:INFO:	Eye window for uplink 27: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
08:39:53:setup_element:INFO:	Eye window for uplink 28: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
08:39:53:setup_element:INFO:	Eye window for uplink 29: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
08:39:53:setup_element:INFO:	Eye window for uplink 30: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
08:39:53:setup_element:INFO:	Eye window for uplink 31: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
08:39:53:setup_element:INFO:	Setting the clock phase to 31 for group 0, downlink 2
==============================================OOO==============================================
08:39:53:setup_element:INFO:	Scanning data phases
08:39:53:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:39:54:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:39:59:setup_element:INFO:	Data phase scan results for group 0, downlink 2
08:39:59:setup_element:INFO:	Eye window for uplink 24: __________XXXXXXX_______________________
Data delay found: 33
08:39:59:setup_element:INFO:	Eye window for uplink 25: ____________XXXXXX______________________
Data delay found: 34
08:39:59:setup_element:INFO:	Eye window for uplink 26: _______________XXXXXX___________________
Data delay found: 37
08:39:59:setup_element:INFO:	Eye window for uplink 27: _________________XXXXXX_________________
Data delay found: 39
08:39:59:setup_element:INFO:	Eye window for uplink 28: __________________XXXXXX________________
Data delay found: 0
08:39:59:setup_element:INFO:	Eye window for uplink 29: __________________XXXXXX________________
Data delay found: 0
08:39:59:setup_element:INFO:	Eye window for uplink 30: _____________________XXXXX______________
Data delay found: 3
08:39:59:setup_element:INFO:	Eye window for uplink 31: ___________________XXXXXX_______________
Data delay found: 1
08:39:59:setup_element:INFO:	Setting the data phase to 33 for uplink 24
08:39:59:setup_element:INFO:	Setting the data phase to 34 for uplink 25
08:39:59:setup_element:INFO:	Setting the data phase to 37 for uplink 26
08:39:59:setup_element:INFO:	Setting the data phase to 39 for uplink 27
08:39:59:setup_element:INFO:	Setting the data phase to 0 for uplink 28
08:39:59:setup_element:INFO:	Setting the data phase to 0 for uplink 29
08:39:59:setup_element:INFO:	Setting the data phase to 3 for uplink 30
08:39:59:setup_element:INFO:	Setting the data phase to 1 for uplink 31
==============================================OOO==============================================
08:39:59:setup_element:INFO:	Beginning SMX ASICs map scan
08:39:59:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:39:59:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:39:59:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
08:39:59:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
08:39:59:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
08:39:59:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
08:39:59:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
08:39:59:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
08:39:59:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
08:40:00:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
08:40:00:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
08:40:00:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
08:40:00:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
08:40:01:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 31
    Window Length: 70
    Eye Windows:
      Uplink 24: ___________________________________________________________________XXXXXXXX_____
      Uplink 25: ___________________________________________________________________XXXXXXXX_____
      Uplink 26: ____________________________________________________________________XXXXXXXX____
      Uplink 27: ____________________________________________________________________XXXXXXXX____
      Uplink 28: ____________________________________________________________________XXXXXXX_____
      Uplink 29: ____________________________________________________________________XXXXXXX_____
      Uplink 30: ____________________________________________________________________XXXXXXXXX___
      Uplink 31: ____________________________________________________________________XXXXXXXXX___
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 33
      Window Length: 33
      Eye Window: __________XXXXXXX_______________________
    Uplink 25:
      Optimal Phase: 34
      Window Length: 34
      Eye Window: ____________XXXXXX______________________
    Uplink 26:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 27:
      Optimal Phase: 39
      Window Length: 34
      Eye Window: _________________XXXXXX_________________
    Uplink 28:
      Optimal Phase: 0
      Window Length: 34
      Eye Window: __________________XXXXXX________________
    Uplink 29:
      Optimal Phase: 0
      Window Length: 34
      Eye Window: __________________XXXXXX________________
    Uplink 30:
      Optimal Phase: 3
      Window Length: 35
      Eye Window: _____________________XXXXX______________
    Uplink 31:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________

==============================================OOO==============================================
08:40:01:setup_element:INFO:	Performing Elink synchronization
08:40:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
08:40:01:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
08:40:02:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
08:40:02:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
08:40:02:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
08:40:02:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
08:40:02:ST3_emu_feb:DEBUG:	Chip address:  	0x1
08:40:02:ST3_emu_feb:DEBUG:	Chip address:  	0x3
08:40:02:ST3_emu_feb:DEBUG:	Chip address:  	0x5
08:40:02:ST3_emu_feb:DEBUG:	Chip address:  	0x7
08:40:02:febtest:INFO:	Init all SMX (CSA): 30
08:40:09:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:40:09:febtest:INFO:	30-01 | XA-000-09-004-043-013-005-10 |  31.4 | 1183.3
08:40:09:febtest:INFO:	28-03 | XA-000-09-004-043-010-004-02 |  34.6 | 1171.5
08:40:10:febtest:INFO:	26-05 | XA-000-09-004-043-013-004-10 |  31.4 | 1201.0
08:40:10:febtest:INFO:	24-07 | XA-000-09-004-043-010-013-02 |  34.6 | 1171.5
08:40:11:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
08:40:13:ST3_smx:INFO:	chip: 30-1 	 31.389742 C 	 1195.082160 mV
08:40:13:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:40:13:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:40:13:ST3_smx:INFO:		Electrons
08:40:18:ST3_smx:INFO:	Total # of broken channels: 8
08:40:18:ST3_smx:INFO:	List of broken channels: [0, 3, 7, 20, 25, 46, 52, 80]
08:40:18:ST3_smx:INFO:	Total # of broken channels: 0
08:40:18:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
08:40:20:ST3_smx:INFO:	chip: 28-3 	 34.556970 C 	 1183.292940 mV
08:40:20:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:40:20:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:40:20:ST3_smx:INFO:		Electrons
08:40:24:ST3_smx:INFO:	Total # of broken channels: 6
08:40:24:ST3_smx:INFO:	List of broken channels: [0, 23, 55, 68, 101, 103]
08:40:24:ST3_smx:INFO:	Total # of broken channels: 0
08:40:24:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
08:40:26:ST3_smx:INFO:	chip: 26-5 	 31.389742 C 	 1212.728715 mV
08:40:26:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:40:26:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:40:26:ST3_smx:INFO:		Electrons
08:40:31:ST3_smx:INFO:	Total # of broken channels: 10
08:40:31:ST3_smx:INFO:	List of broken channels: [14, 55, 60, 63, 68, 72, 81, 95, 111, 122]
08:40:31:ST3_smx:INFO:	Total # of broken channels: 0
08:40:31:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
08:40:33:ST3_smx:INFO:	chip: 24-7 	 34.556970 C 	 1177.390875 mV
08:40:33:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:40:33:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
08:40:33:ST3_smx:INFO:		Electrons
08:40:37:ST3_smx:INFO:	Total # of broken channels: 7
08:40:37:ST3_smx:INFO:	List of broken channels: [0, 2, 17, 27, 29, 46, 52]
08:40:37:ST3_smx:INFO:	Total # of broken channels: 0
08:40:37:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
08:40:38:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
08:40:38:febtest:INFO:	30-01 | XA-000-09-004-043-013-005-10 |  34.6 | 1218.6
08:40:38:febtest:INFO:	28-03 | XA-000-09-004-043-010-004-02 |  37.7 | 1206.9
08:40:39:febtest:INFO:	26-05 | XA-000-09-004-043-013-004-10 |  31.4 | 1242.0
08:40:39:febtest:INFO:	24-07 | XA-000-09-004-043-010-013-02 |  37.7 | 1201.0
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_07_24-08_39_51
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2466| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.7633', '1.848', '1.1580']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9997', '1.850', '1.2580']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9790', '1.850', '0.2649']
Comment.txt