DTL-STS tests database

FEB_2467 30.07.25 10:35:10

link:
...SMX_0.root
link:
...SMX_2.root
link:
...SMX_4.root
link:
...SMX_6.root
link: XA-000-09-004-032-008-015-15
...SMX_1.root
link: XA-000-09-004-032-005-015-08
...SMX_3.root
link: XA-000-09-004-032-011-016-06
...SMX_5.root
link: XA-000-09-004-032-011-015-01
...SMX_7.root
link: XA-000-09-004-032-011-015-01
...VddmCSAstatus.root
Info
            10:35:10:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:35:10:ST3_Shared:INFO:	                       FEB-Microcable                       
10:35:10:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:35:10:febtest:INFO:	Testing FEB with SN 2467
==============================================OOO==============================================
10:35:12:smx_tester:INFO:	Scanning setup
10:35:12:elinks:INFO:	Disabling clock on downlink 0
10:35:12:elinks:INFO:	Disabling clock on downlink 1
10:35:12:elinks:INFO:	Disabling clock on downlink 2
10:35:12:elinks:INFO:	Disabling clock on downlink 3
10:35:12:elinks:INFO:	Disabling clock on downlink 4
10:35:12:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:35:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
10:35:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:35:12:elinks:INFO:	Disabling clock on downlink 0
10:35:12:elinks:INFO:	Disabling clock on downlink 1
10:35:12:elinks:INFO:	Disabling clock on downlink 2
10:35:12:elinks:INFO:	Disabling clock on downlink 3
10:35:12:elinks:INFO:	Disabling clock on downlink 4
10:35:12:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:35:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
10:35:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:35:12:elinks:INFO:	Disabling clock on downlink 0
10:35:12:elinks:INFO:	Disabling clock on downlink 1
10:35:12:elinks:INFO:	Disabling clock on downlink 2
10:35:12:elinks:INFO:	Disabling clock on downlink 3
10:35:12:elinks:INFO:	Disabling clock on downlink 4
10:35:12:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:35:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:35:12:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
10:35:12:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
10:35:12:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
10:35:12:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
10:35:12:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
10:35:12:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
10:35:12:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
10:35:12:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
10:35:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:35:12:elinks:INFO:	Disabling clock on downlink 0
10:35:12:elinks:INFO:	Disabling clock on downlink 1
10:35:12:elinks:INFO:	Disabling clock on downlink 2
10:35:12:elinks:INFO:	Disabling clock on downlink 3
10:35:12:elinks:INFO:	Disabling clock on downlink 4
10:35:12:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:35:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
10:35:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:35:12:elinks:INFO:	Disabling clock on downlink 0
10:35:12:elinks:INFO:	Disabling clock on downlink 1
10:35:13:elinks:INFO:	Disabling clock on downlink 2
10:35:13:elinks:INFO:	Disabling clock on downlink 3
10:35:13:elinks:INFO:	Disabling clock on downlink 4
10:35:13:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:35:13:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
10:35:13:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
10:35:13:setup_element:INFO:	Scanning clock phase
10:35:13:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:35:13:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:35:13:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
10:35:13:setup_element:INFO:	Eye window for uplink 24: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
10:35:13:setup_element:INFO:	Eye window for uplink 25: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
10:35:13:setup_element:INFO:	Eye window for uplink 26: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
10:35:13:setup_element:INFO:	Eye window for uplink 27: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
10:35:13:setup_element:INFO:	Eye window for uplink 28: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
10:35:13:setup_element:INFO:	Eye window for uplink 29: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
10:35:13:setup_element:INFO:	Eye window for uplink 30: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
10:35:13:setup_element:INFO:	Eye window for uplink 31: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
10:35:13:setup_element:INFO:	Setting the clock phase to 31 for group 0, downlink 2
==============================================OOO==============================================
10:35:13:setup_element:INFO:	Scanning data phases
10:35:13:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:35:13:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:35:18:setup_element:INFO:	Data phase scan results for group 0, downlink 2
10:35:18:setup_element:INFO:	Eye window for uplink 24: __________XXXXXX________________________
Data delay found: 32
10:35:18:setup_element:INFO:	Eye window for uplink 25: ____________XXXXXX______________________
Data delay found: 34
10:35:18:setup_element:INFO:	Eye window for uplink 26: _______________XXXXXX___________________
Data delay found: 37
10:35:18:setup_element:INFO:	Eye window for uplink 27: _________________XXXXXX_________________
Data delay found: 39
10:35:18:setup_element:INFO:	Eye window for uplink 28: ___________________XXXXX________________
Data delay found: 1
10:35:18:setup_element:INFO:	Eye window for uplink 29: __________________XXXXX_________________
Data delay found: 0
10:35:18:setup_element:INFO:	Eye window for uplink 30: ___________________XXXXXX_______________
Data delay found: 1
10:35:18:setup_element:INFO:	Eye window for uplink 31: _________________XXXXXXX________________
Data delay found: 0
10:35:18:setup_element:INFO:	Setting the data phase to 32 for uplink 24
10:35:18:setup_element:INFO:	Setting the data phase to 34 for uplink 25
10:35:18:setup_element:INFO:	Setting the data phase to 37 for uplink 26
10:35:18:setup_element:INFO:	Setting the data phase to 39 for uplink 27
10:35:18:setup_element:INFO:	Setting the data phase to 1 for uplink 28
10:35:18:setup_element:INFO:	Setting the data phase to 0 for uplink 29
10:35:18:setup_element:INFO:	Setting the data phase to 1 for uplink 30
10:35:18:setup_element:INFO:	Setting the data phase to 0 for uplink 31
==============================================OOO==============================================
10:35:18:setup_element:INFO:	Beginning SMX ASICs map scan
10:35:18:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:35:18:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:35:18:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
10:35:18:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
10:35:18:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
10:35:19:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
10:35:19:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
10:35:19:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
10:35:19:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
10:35:19:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
10:35:19:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
10:35:20:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
10:35:20:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
10:35:21:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 31
    Window Length: 71
    Eye Windows:
      Uplink 24: ___________________________________________________________________XXXXXXXXX____
      Uplink 25: ___________________________________________________________________XXXXXXXXX____
      Uplink 26: ____________________________________________________________________XXXXXXXX____
      Uplink 27: ____________________________________________________________________XXXXXXXX____
      Uplink 28: ___________________________________________________________________XXXXXXXXX____
      Uplink 29: ___________________________________________________________________XXXXXXXXX____
      Uplink 30: ____________________________________________________________________XXXXXXX_____
      Uplink 31: ____________________________________________________________________XXXXXXX_____
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 32
      Window Length: 34
      Eye Window: __________XXXXXX________________________
    Uplink 25:
      Optimal Phase: 34
      Window Length: 34
      Eye Window: ____________XXXXXX______________________
    Uplink 26:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 27:
      Optimal Phase: 39
      Window Length: 34
      Eye Window: _________________XXXXXX_________________
    Uplink 28:
      Optimal Phase: 1
      Window Length: 35
      Eye Window: ___________________XXXXX________________
    Uplink 29:
      Optimal Phase: 0
      Window Length: 35
      Eye Window: __________________XXXXX_________________
    Uplink 30:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 31:
      Optimal Phase: 0
      Window Length: 33
      Eye Window: _________________XXXXXXX________________

==============================================OOO==============================================
10:35:21:setup_element:INFO:	Performing Elink synchronization
10:35:21:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:35:21:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:35:21:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
10:35:21:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
10:35:21:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
10:35:21:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
10:35:21:ST3_emu_feb:DEBUG:	Chip address:  	0x1
10:35:21:ST3_emu_feb:DEBUG:	Chip address:  	0x3
10:35:21:ST3_emu_feb:DEBUG:	Chip address:  	0x5
10:35:21:ST3_emu_feb:DEBUG:	Chip address:  	0x7
10:35:22:febtest:INFO:	Init all SMX (CSA): 30
10:35:28:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:35:29:febtest:INFO:	30-01 | XA-000-09-004-032-008-015-15 |  15.6 | 1206.9
10:35:29:febtest:INFO:	28-03 | XA-000-09-004-032-005-015-08 |   9.3 | 1230.3
10:35:29:febtest:INFO:	26-05 | XA-000-09-004-032-011-016-06 |  21.9 | 1177.4
10:35:29:febtest:INFO:	24-07 | XA-000-09-004-032-011-015-01 |  12.4 | 1212.7
10:35:30:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
10:35:33:ST3_smx:INFO:	chip: 30-1 	 15.590880 C 	 1212.728715 mV
10:35:33:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:35:33:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:35:33:ST3_smx:INFO:		Electrons
10:35:37:ST3_smx:INFO:	Total # of broken channels: 6
10:35:37:ST3_smx:INFO:	List of broken channels: [26, 33, 59, 86, 108, 115]
10:35:37:ST3_smx:INFO:	Total # of broken channels: 0
10:35:37:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
10:35:39:ST3_smx:INFO:	chip: 28-3 	 9.288730 C 	 1236.187875 mV
10:35:39:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:35:39:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:35:39:ST3_smx:INFO:		Electrons
10:35:44:ST3_smx:INFO:	Total # of broken channels: 6
10:35:44:ST3_smx:INFO:	List of broken channels: [28, 34, 64, 77, 78, 115]
10:35:44:ST3_smx:INFO:	Total # of broken channels: 0
10:35:44:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
10:35:46:ST3_smx:INFO:	chip: 26-5 	 21.902970 C 	 1189.190035 mV
10:35:46:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:35:46:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:35:46:ST3_smx:INFO:		Electrons
10:35:50:ST3_smx:INFO:	Total # of broken channels: 2
10:35:50:ST3_smx:INFO:	List of broken channels: [67, 122]
10:35:50:ST3_smx:INFO:	Total # of broken channels: 0
10:35:50:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
10:35:52:ST3_smx:INFO:	chip: 24-7 	 12.438562 C 	 1224.468235 mV
10:35:52:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:35:52:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:35:52:ST3_smx:INFO:		Electrons
10:35:57:ST3_smx:INFO:	Total # of broken channels: 9
10:35:57:ST3_smx:INFO:	List of broken channels: [10, 23, 28, 31, 68, 78, 86, 98, 116]
10:35:57:ST3_smx:INFO:	Total # of broken channels: 0
10:35:57:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
10:35:57:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:35:57:febtest:INFO:	30-01 | XA-000-09-004-032-008-015-15 |  15.6 | 1236.2
10:35:58:febtest:INFO:	28-03 | XA-000-09-004-032-005-015-08 |   9.3 | 1259.6
10:35:58:febtest:INFO:	26-05 | XA-000-09-004-032-011-016-06 |  25.1 | 1206.9
10:35:58:febtest:INFO:	24-07 | XA-000-09-004-032-011-015-01 |  15.6 | 1242.0
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_07_30-10_35_10
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2467| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.7706', '1.848', '1.0520']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0200', '1.849', '1.2700']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9770', '1.850', '0.2578']
Comment