DTL-STS tests database

FEB_2478 03.09.25 11:15:49

link:
...SMX_0.root
link:
...SMX_2.root
link:
...SMX_4.root
link:
...SMX_6.root
link: XA-000-09-004-025-002-016-08
...SMX_1.root
link: XA-000-09-004-025-017-018-10
...SMX_3.root
link: XA-000-09-004-025-011-017-09
...SMX_5.root
link: XA-000-09-004-025-017-017-10
...SMX_7.root
link: XA-000-09-004-025-017-017-10
...VddmCSAstatus.root
Info
            11:15:49:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:15:49:ST3_Shared:INFO:	                       FEB-Microcable                       
11:15:49:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:15:49:febtest:INFO:	Testing FEB with SN 2478
==============================================OOO==============================================
11:15:50:smx_tester:INFO:	Scanning setup
11:15:50:elinks:INFO:	Disabling clock on downlink 0
11:15:50:elinks:INFO:	Disabling clock on downlink 1
11:15:50:elinks:INFO:	Disabling clock on downlink 2
11:15:50:elinks:INFO:	Disabling clock on downlink 3
11:15:50:elinks:INFO:	Disabling clock on downlink 4
11:15:50:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:15:50:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
11:15:50:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
11:15:50:elinks:INFO:	Disabling clock on downlink 0
11:15:50:elinks:INFO:	Disabling clock on downlink 1
11:15:50:elinks:INFO:	Disabling clock on downlink 2
11:15:50:elinks:INFO:	Disabling clock on downlink 3
11:15:50:elinks:INFO:	Disabling clock on downlink 4
11:15:50:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:15:50:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
11:15:50:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
11:15:50:elinks:INFO:	Disabling clock on downlink 0
11:15:50:elinks:INFO:	Disabling clock on downlink 1
11:15:50:elinks:INFO:	Disabling clock on downlink 2
11:15:50:elinks:INFO:	Disabling clock on downlink 3
11:15:50:elinks:INFO:	Disabling clock on downlink 4
11:15:50:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:15:50:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:15:51:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
11:15:51:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
11:15:51:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
11:15:51:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
11:15:51:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
11:15:51:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
11:15:51:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
11:15:51:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
11:15:51:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
11:15:51:elinks:INFO:	Disabling clock on downlink 0
11:15:51:elinks:INFO:	Disabling clock on downlink 1
11:15:51:elinks:INFO:	Disabling clock on downlink 2
11:15:51:elinks:INFO:	Disabling clock on downlink 3
11:15:51:elinks:INFO:	Disabling clock on downlink 4
11:15:51:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:15:51:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
11:15:51:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
11:15:51:elinks:INFO:	Disabling clock on downlink 0
11:15:51:elinks:INFO:	Disabling clock on downlink 1
11:15:51:elinks:INFO:	Disabling clock on downlink 2
11:15:51:elinks:INFO:	Disabling clock on downlink 3
11:15:51:elinks:INFO:	Disabling clock on downlink 4
11:15:51:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:15:51:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
11:15:51:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
11:15:51:setup_element:INFO:	Scanning clock phase
11:15:51:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:15:51:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:15:51:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
11:15:51:setup_element:INFO:	Eye window for uplink 24: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
11:15:51:setup_element:INFO:	Eye window for uplink 25: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
11:15:51:setup_element:INFO:	Eye window for uplink 26: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
11:15:51:setup_element:INFO:	Eye window for uplink 27: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
11:15:51:setup_element:INFO:	Eye window for uplink 28: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
11:15:51:setup_element:INFO:	Eye window for uplink 29: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
11:15:51:setup_element:INFO:	Eye window for uplink 30: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
11:15:51:setup_element:INFO:	Eye window for uplink 31: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
11:15:51:setup_element:INFO:	Setting the clock phase to 31 for group 0, downlink 2
==============================================OOO==============================================
11:15:51:setup_element:INFO:	Scanning data phases
11:15:51:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:15:51:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:15:56:setup_element:INFO:	Data phase scan results for group 0, downlink 2
11:15:56:setup_element:INFO:	Eye window for uplink 24: ______________XXXXXX____________________
Data delay found: 36
11:15:56:setup_element:INFO:	Eye window for uplink 25: ________________XXXXX___________________
Data delay found: 38
11:15:56:setup_element:INFO:	Eye window for uplink 26: _______________XXXXXX___________________
Data delay found: 37
11:15:56:setup_element:INFO:	Eye window for uplink 27: _________________XXXXXX_________________
Data delay found: 39
11:15:56:setup_element:INFO:	Eye window for uplink 28: ___________________XXXXX________________
Data delay found: 1
11:15:56:setup_element:INFO:	Eye window for uplink 29: __________________XXXXX_________________
Data delay found: 0
11:15:56:setup_element:INFO:	Eye window for uplink 30: _____________________XXXXXX_____________
Data delay found: 3
11:15:56:setup_element:INFO:	Eye window for uplink 31: ___________________XXXXXX_______________
Data delay found: 1
11:15:56:setup_element:INFO:	Setting the data phase to 36 for uplink 24
11:15:56:setup_element:INFO:	Setting the data phase to 38 for uplink 25
11:15:56:setup_element:INFO:	Setting the data phase to 37 for uplink 26
11:15:56:setup_element:INFO:	Setting the data phase to 39 for uplink 27
11:15:56:setup_element:INFO:	Setting the data phase to 1 for uplink 28
11:15:56:setup_element:INFO:	Setting the data phase to 0 for uplink 29
11:15:56:setup_element:INFO:	Setting the data phase to 3 for uplink 30
11:15:56:setup_element:INFO:	Setting the data phase to 1 for uplink 31
==============================================OOO==============================================
11:15:56:setup_element:INFO:	Beginning SMX ASICs map scan
11:15:56:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:15:56:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:15:56:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
11:15:56:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
11:15:56:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
11:15:56:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
11:15:56:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
11:15:57:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
11:15:57:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
11:15:57:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
11:15:57:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
11:15:57:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
11:15:57:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
11:15:59:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 31
    Window Length: 70
    Eye Windows:
      Uplink 24: _____________________________________________________________________XXXXXXXX___
      Uplink 25: _____________________________________________________________________XXXXXXXX___
      Uplink 26: ____________________________________________________________________XXXXXXXX____
      Uplink 27: ____________________________________________________________________XXXXXXXX____
      Uplink 28: ___________________________________________________________________XXXXXXXX_____
      Uplink 29: ___________________________________________________________________XXXXXXXX_____
      Uplink 30: ____________________________________________________________________XXXXXXXX____
      Uplink 31: ____________________________________________________________________XXXXXXXX____
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 36
      Window Length: 34
      Eye Window: ______________XXXXXX____________________
    Uplink 25:
      Optimal Phase: 38
      Window Length: 35
      Eye Window: ________________XXXXX___________________
    Uplink 26:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 27:
      Optimal Phase: 39
      Window Length: 34
      Eye Window: _________________XXXXXX_________________
    Uplink 28:
      Optimal Phase: 1
      Window Length: 35
      Eye Window: ___________________XXXXX________________
    Uplink 29:
      Optimal Phase: 0
      Window Length: 35
      Eye Window: __________________XXXXX_________________
    Uplink 30:
      Optimal Phase: 3
      Window Length: 34
      Eye Window: _____________________XXXXXX_____________
    Uplink 31:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________

==============================================OOO==============================================
11:15:59:setup_element:INFO:	Performing Elink synchronization
11:15:59:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:15:59:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:15:59:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
11:15:59:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
11:15:59:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
11:15:59:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
11:15:59:febtest:INFO:	Init all SMX (CSA): 30
11:16:06:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:16:06:febtest:INFO:	30-01 | XA-000-09-004-025-002-016-08 |  37.7 | 1135.9
11:16:07:febtest:INFO:	28-03 | XA-000-09-004-025-017-018-10 |   9.3 | 1224.5
11:16:07:febtest:INFO:	26-05 | XA-000-09-004-025-011-017-09 |  31.4 | 1153.7
11:16:07:febtest:INFO:	24-07 | XA-000-09-004-025-017-017-10 |  15.6 | 1212.7
11:16:08:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
11:16:10:ST3_smx:INFO:	chip: 30-1 	 37.726682 C 	 1147.806000 mV
11:16:10:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:16:10:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:16:10:ST3_smx:INFO:		Electrons
11:16:15:ST3_smx:INFO:	Total # of broken channels: 6
11:16:15:ST3_smx:INFO:	List of broken channels: [32, 51, 70, 108, 110, 121]
11:16:15:ST3_smx:INFO:	Total # of broken channels: 0
11:16:15:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:16:17:ST3_smx:INFO:	chip: 28-3 	 9.288730 C 	 1236.187875 mV
11:16:17:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:16:17:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:16:17:ST3_smx:INFO:		Electrons
11:16:21:ST3_smx:INFO:	Total # of broken channels: 5
11:16:21:ST3_smx:INFO:	List of broken channels: [4, 27, 109, 112, 115]
11:16:21:ST3_smx:INFO:	Total # of broken channels: 0
11:16:21:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:16:23:ST3_smx:INFO:	chip: 26-5 	 31.389742 C 	 1165.571835 mV
11:16:23:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:16:23:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:16:23:ST3_smx:INFO:		Electrons
11:16:28:ST3_smx:INFO:	Total # of broken channels: 11
11:16:28:ST3_smx:INFO:	List of broken channels: [10, 12, 35, 44, 46, 57, 76, 79, 97, 102, 104]
11:16:28:ST3_smx:INFO:	Total # of broken channels: 0
11:16:28:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:16:30:ST3_smx:INFO:	chip: 24-7 	 15.590880 C 	 1218.600960 mV
11:16:30:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:16:30:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:16:30:ST3_smx:INFO:		Electrons
11:16:34:ST3_smx:INFO:	Total # of broken channels: 9
11:16:34:ST3_smx:INFO:	List of broken channels: [27, 59, 66, 71, 78, 81, 84, 101, 123]
11:16:34:ST3_smx:INFO:	Total # of broken channels: 0
11:16:34:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:16:35:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:16:35:febtest:INFO:	30-01 | XA-000-09-004-025-002-016-08 |  34.6 | 1171.5
11:16:35:febtest:INFO:	28-03 | XA-000-09-004-025-017-018-10 |   9.3 | 1259.6
11:16:35:febtest:INFO:	26-05 | XA-000-09-004-025-011-017-09 |  34.6 | 1183.3
11:16:35:febtest:INFO:	24-07 | XA-000-09-004-025-017-017-10 |  18.7 | 1242.0
{'CSA_FRONT': 55, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 55, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 55, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 55, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 55, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 55, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 55, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 55, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 55, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 55, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 55, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 55, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_09_03-11_15_49
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2478| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.7404', '1.848', '1.1580']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0250', '1.850', '1.2890']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9931', '1.850', '0.2627']
Comment