DTL-STS tests database

FEB_2480 27.08.25 11:17:10

link:
...SMX_0.root
link:
...SMX_2.root
link:
...SMX_4.root
link:
...SMX_6.root
link: XA-000-09-004-043-014-021-03
...SMX_1.root
link: XA-000-09-004-043-008-020-06
...SMX_3.root
link: XA-000-09-004-043-017-019-11
...SMX_5.root
link: XA-000-09-004-043-011-021-08
...SMX_7.root
link: XA-000-09-004-043-011-021-08
...VddmCSAstatus.root
Info
            11:17:10:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:17:10:ST3_Shared:INFO:	                       FEB-Microcable                       
11:17:10:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:17:10:febtest:INFO:	Testing FEB with SN 2480
==============================================OOO==============================================
11:17:11:smx_tester:INFO:	Scanning setup
11:17:11:elinks:INFO:	Disabling clock on downlink 0
11:17:11:elinks:INFO:	Disabling clock on downlink 1
11:17:11:elinks:INFO:	Disabling clock on downlink 2
11:17:11:elinks:INFO:	Disabling clock on downlink 3
11:17:11:elinks:INFO:	Disabling clock on downlink 4
11:17:11:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:17:11:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
11:17:11:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
11:17:11:elinks:INFO:	Disabling clock on downlink 0
11:17:11:elinks:INFO:	Disabling clock on downlink 1
11:17:11:elinks:INFO:	Disabling clock on downlink 2
11:17:11:elinks:INFO:	Disabling clock on downlink 3
11:17:11:elinks:INFO:	Disabling clock on downlink 4
11:17:11:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:17:11:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
11:17:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
11:17:12:elinks:INFO:	Disabling clock on downlink 0
11:17:12:elinks:INFO:	Disabling clock on downlink 1
11:17:12:elinks:INFO:	Disabling clock on downlink 2
11:17:12:elinks:INFO:	Disabling clock on downlink 3
11:17:12:elinks:INFO:	Disabling clock on downlink 4
11:17:12:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:17:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:17:12:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
11:17:12:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
11:17:12:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
11:17:12:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
11:17:12:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
11:17:12:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
11:17:12:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
11:17:12:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
11:17:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
11:17:12:elinks:INFO:	Disabling clock on downlink 0
11:17:12:elinks:INFO:	Disabling clock on downlink 1
11:17:12:elinks:INFO:	Disabling clock on downlink 2
11:17:12:elinks:INFO:	Disabling clock on downlink 3
11:17:12:elinks:INFO:	Disabling clock on downlink 4
11:17:12:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:17:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
11:17:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
11:17:12:elinks:INFO:	Disabling clock on downlink 0
11:17:12:elinks:INFO:	Disabling clock on downlink 1
11:17:12:elinks:INFO:	Disabling clock on downlink 2
11:17:12:elinks:INFO:	Disabling clock on downlink 3
11:17:12:elinks:INFO:	Disabling clock on downlink 4
11:17:12:setup_element:INFO:	Checking SOS, encoding_mode: SOS
11:17:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
11:17:12:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
11:17:12:setup_element:INFO:	Scanning clock phase
11:17:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:17:12:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:17:12:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
11:17:12:setup_element:INFO:	Eye window for uplink 24: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
11:17:12:setup_element:INFO:	Eye window for uplink 25: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
11:17:12:setup_element:INFO:	Eye window for uplink 26: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
11:17:12:setup_element:INFO:	Eye window for uplink 27: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
11:17:12:setup_element:INFO:	Eye window for uplink 28: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
11:17:12:setup_element:INFO:	Eye window for uplink 29: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
11:17:12:setup_element:INFO:	Eye window for uplink 30: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
11:17:12:setup_element:INFO:	Eye window for uplink 31: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
11:17:12:setup_element:INFO:	Setting the clock phase to 31 for group 0, downlink 2
==============================================OOO==============================================
11:17:12:setup_element:INFO:	Scanning data phases
11:17:12:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:17:13:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:17:18:setup_element:INFO:	Data phase scan results for group 0, downlink 2
11:17:18:setup_element:INFO:	Eye window for uplink 24: ___________XXXXXX_______________________
Data delay found: 33
11:17:18:setup_element:INFO:	Eye window for uplink 25: _____________XXXXX______________________
Data delay found: 35
11:17:18:setup_element:INFO:	Eye window for uplink 26: __________________XXXXXX_XXXXXXXXXXXXXXX
Data delay found: 8
11:17:18:setup_element:INFO:	Eye window for uplink 27: ___________________XXXXXXXXXXXXXXXXXXXXX
Data delay found: 9
11:17:18:setup_element:INFO:	Eye window for uplink 28: ___________________XXXXXX_______________
Data delay found: 1
11:17:18:setup_element:INFO:	Eye window for uplink 29: __________________XXXXXX________________
Data delay found: 0
11:17:18:setup_element:INFO:	Eye window for uplink 30: ___________________XXXXXX_______________
Data delay found: 1
11:17:18:setup_element:INFO:	Eye window for uplink 31: _________________XXXXXXX________________
Data delay found: 0
11:17:18:setup_element:INFO:	Setting the data phase to 33 for uplink 24
11:17:18:setup_element:INFO:	Setting the data phase to 35 for uplink 25
11:17:18:setup_element:INFO:	Setting the data phase to 8 for uplink 26
11:17:18:setup_element:INFO:	Setting the data phase to 9 for uplink 27
11:17:18:setup_element:INFO:	Setting the data phase to 1 for uplink 28
11:17:18:setup_element:INFO:	Setting the data phase to 0 for uplink 29
11:17:18:setup_element:INFO:	Setting the data phase to 1 for uplink 30
11:17:18:setup_element:INFO:	Setting the data phase to 0 for uplink 31
==============================================OOO==============================================
11:17:18:setup_element:INFO:	Beginning SMX ASICs map scan
11:17:18:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:17:18:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:17:18:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
11:17:18:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
11:17:18:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
11:17:18:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
11:17:18:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
11:17:18:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
11:17:18:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
11:17:19:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
11:17:19:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
11:17:19:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
11:17:19:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
11:17:20:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 31
    Window Length: 70
    Eye Windows:
      Uplink 24: ___________________________________________________________________XXXXXXXXX____
      Uplink 25: ___________________________________________________________________XXXXXXXXX____
      Uplink 26: _____________________________________________________________________XXXXXXXX___
      Uplink 27: _____________________________________________________________________XXXXXXXX___
      Uplink 28: ____________________________________________________________________XXXXXXXX____
      Uplink 29: ____________________________________________________________________XXXXXXXX____
      Uplink 30: ____________________________________________________________________XXXXXXX_____
      Uplink 31: ____________________________________________________________________XXXXXXX_____
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 33
      Window Length: 34
      Eye Window: ___________XXXXXX_______________________
    Uplink 25:
      Optimal Phase: 35
      Window Length: 35
      Eye Window: _____________XXXXX______________________
    Uplink 26:
      Optimal Phase: 8
      Window Length: 18
      Eye Window: __________________XXXXXX_XXXXXXXXXXXXXXX
    Uplink 27:
      Optimal Phase: 9
      Window Length: 19
      Eye Window: ___________________XXXXXXXXXXXXXXXXXXXXX
    Uplink 28:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 29:
      Optimal Phase: 0
      Window Length: 34
      Eye Window: __________________XXXXXX________________
    Uplink 30:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 31:
      Optimal Phase: 0
      Window Length: 33
      Eye Window: _________________XXXXXXX________________

==============================================OOO==============================================
11:17:20:setup_element:INFO:	Performing Elink synchronization
11:17:20:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
11:17:20:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:17:20:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
11:17:20:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
11:17:20:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
11:17:20:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
11:17:21:ST3_emu_feb:DEBUG:	Chip address:  	0x1
11:17:21:ST3_emu_feb:DEBUG:	Chip address:  	0x3
11:17:21:ST3_emu_feb:DEBUG:	Chip address:  	0x5
11:17:21:ST3_emu_feb:DEBUG:	Chip address:  	0x7
11:17:21:febtest:INFO:	Init all SMX (CSA): 30
11:17:29:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:17:29:febtest:INFO:	30-01 | XA-000-09-004-043-014-021-03 |  18.7 | 1212.7
11:17:29:febtest:INFO:	28-03 | XA-000-09-004-043-008-020-06 |  34.6 | 1159.7
11:17:29:febtest:INFO:	26-05 | XA-000-09-004-043-017-019-11 |  15.6 | 1224.5
11:17:29:febtest:INFO:	24-07 | XA-000-09-004-043-011-021-08 |  34.6 | 1165.6
11:17:30:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
11:17:33:ST3_smx:INFO:	chip: 30-1 	 21.902970 C 	 1224.468235 mV
11:17:33:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:17:33:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:17:33:ST3_smx:INFO:		Electrons
11:17:37:ST3_smx:INFO:	Total # of broken channels: 9
11:17:37:ST3_smx:INFO:	List of broken channels: [27, 42, 61, 75, 80, 95, 107, 112, 117]
11:17:37:ST3_smx:INFO:	Total # of broken channels: 0
11:17:37:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:17:39:ST3_smx:INFO:	chip: 28-3 	 34.556970 C 	 1171.483840 mV
11:17:39:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:17:39:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:17:39:ST3_smx:INFO:		Electrons
11:17:44:ST3_smx:INFO:	Total # of broken channels: 3
11:17:44:ST3_smx:INFO:	List of broken channels: [31, 39, 101]
11:17:44:ST3_smx:INFO:	Total # of broken channels: 0
11:17:44:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:17:46:ST3_smx:INFO:	chip: 26-5 	 15.590880 C 	 1236.187875 mV
11:17:46:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:17:46:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:17:46:ST3_smx:INFO:		Electrons
11:17:50:ST3_smx:INFO:	Total # of broken channels: 12
11:17:50:ST3_smx:INFO:	List of broken channels: [30, 43, 44, 47, 49, 50, 52, 53, 55, 82, 84, 108]
11:17:50:ST3_smx:INFO:	Total # of broken channels: 0
11:17:50:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:17:52:ST3_smx:INFO:	chip: 24-7 	 34.556970 C 	 1171.483840 mV
11:17:52:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:17:52:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
11:17:52:ST3_smx:INFO:		Electrons
11:17:57:ST3_smx:INFO:	Total # of broken channels: 9
11:17:57:ST3_smx:INFO:	List of broken channels: [2, 3, 9, 54, 64, 89, 93, 104, 122]
11:17:57:ST3_smx:INFO:	Total # of broken channels: 0
11:17:57:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
11:17:57:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
11:17:58:febtest:INFO:	30-01 | XA-000-09-004-043-014-021-03 |  18.7 | 1242.0
11:17:58:febtest:INFO:	28-03 | XA-000-09-004-043-008-020-06 |  34.6 | 1195.1
11:17:58:febtest:INFO:	26-05 | XA-000-09-004-043-017-019-11 |  15.6 | 1253.7
11:17:58:febtest:INFO:	24-07 | XA-000-09-004-043-011-021-08 |  37.7 | 1195.1
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_08_27-11_17_10
OPERATOR  : Oleksandr S.; Robert V.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2480| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.7497', '1.848', '1.1430']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0210', '1.850', '1.2480']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0000', '1.850', '0.2634']
Comment