DTL-STS tests database

FEB_2495 17.11.25 14:03:57

link:
...SMX_0.root
link:
...SMX_2.root
link:
...SMX_4.root
link:
...SMX_6.root
link: XA-000-09-004-021-006-009-13
...SMX_1.root
link: XA-000-09-004-021-006-008-13
...SMX_3.root
link: XA-000-09-004-021-012-014-02
...SMX_5.root
link: XA-000-09-004-021-009-009-09
...SMX_7.root
link: XA-000-09-004-021-009-009-09
...VddmCSAstatus.root
Info
            14:03:57:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:03:57:ST3_Shared:INFO:	                       FEB-Microcable                       
14:03:57:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:03:57:febtest:INFO:	Testing FEB with SN 2495
==============================================OOO==============================================
14:03:58:smx_tester:INFO:	Scanning setup
14:03:58:elinks:INFO:	Disabling clock on downlink 0
14:03:58:elinks:INFO:	Disabling clock on downlink 1
14:03:58:elinks:INFO:	Disabling clock on downlink 2
14:03:58:elinks:INFO:	Disabling clock on downlink 3
14:03:58:elinks:INFO:	Disabling clock on downlink 4
14:03:58:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:03:58:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
14:03:58:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:03:58:elinks:INFO:	Disabling clock on downlink 0
14:03:58:elinks:INFO:	Disabling clock on downlink 1
14:03:58:elinks:INFO:	Disabling clock on downlink 2
14:03:58:elinks:INFO:	Disabling clock on downlink 3
14:03:58:elinks:INFO:	Disabling clock on downlink 4
14:03:58:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:03:58:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:03:58:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:03:58:elinks:INFO:	Disabling clock on downlink 0
14:03:58:elinks:INFO:	Disabling clock on downlink 1
14:03:58:elinks:INFO:	Disabling clock on downlink 2
14:03:58:elinks:INFO:	Disabling clock on downlink 3
14:03:58:elinks:INFO:	Disabling clock on downlink 4
14:03:58:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:03:58:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:03:59:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
14:03:59:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
14:03:59:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
14:03:59:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
14:03:59:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
14:03:59:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
14:03:59:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
14:03:59:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
14:03:59:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:03:59:elinks:INFO:	Disabling clock on downlink 0
14:03:59:elinks:INFO:	Disabling clock on downlink 1
14:03:59:elinks:INFO:	Disabling clock on downlink 2
14:03:59:elinks:INFO:	Disabling clock on downlink 3
14:03:59:elinks:INFO:	Disabling clock on downlink 4
14:03:59:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:03:59:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
14:03:59:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:03:59:elinks:INFO:	Disabling clock on downlink 0
14:03:59:elinks:INFO:	Disabling clock on downlink 1
14:03:59:elinks:INFO:	Disabling clock on downlink 2
14:03:59:elinks:INFO:	Disabling clock on downlink 3
14:03:59:elinks:INFO:	Disabling clock on downlink 4
14:03:59:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:03:59:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
14:03:59:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
14:03:59:setup_element:INFO:	Scanning clock phase
14:03:59:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:03:59:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:03:59:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
14:03:59:setup_element:INFO:	Eye window for uplink 24: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
14:03:59:setup_element:INFO:	Eye window for uplink 25: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
14:03:59:setup_element:INFO:	Eye window for uplink 26: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
14:03:59:setup_element:INFO:	Eye window for uplink 27: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
14:03:59:setup_element:INFO:	Eye window for uplink 28: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
14:03:59:setup_element:INFO:	Eye window for uplink 29: ____________________________________________________________________XXXXXXXXX___
Clock Delay: 32
14:03:59:setup_element:INFO:	Eye window for uplink 30: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
14:03:59:setup_element:INFO:	Eye window for uplink 31: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
14:03:59:setup_element:INFO:	Setting the clock phase to 31 for group 0, downlink 2
==============================================OOO==============================================
14:03:59:setup_element:INFO:	Scanning data phases
14:03:59:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:03:59:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:04:04:setup_element:INFO:	Data phase scan results for group 0, downlink 2
14:04:04:setup_element:INFO:	Eye window for uplink 24: ___________XXXXXX_______________________
Data delay found: 33
14:04:04:setup_element:INFO:	Eye window for uplink 25: _____________XXXXXX_____________________
Data delay found: 35
14:04:04:setup_element:INFO:	Eye window for uplink 26: ________________XXXXXX__________________
Data delay found: 38
14:04:04:setup_element:INFO:	Eye window for uplink 27: __________________XXXXX_________________
Data delay found: 0
14:04:05:setup_element:INFO:	Eye window for uplink 28: ____________________XXXXXX______________
Data delay found: 2
14:04:05:setup_element:INFO:	Eye window for uplink 29: ____________________XXXXXX______________
Data delay found: 2
14:04:05:setup_element:INFO:	Eye window for uplink 30: ___________________XXXXX________________
Data delay found: 1
14:04:05:setup_element:INFO:	Eye window for uplink 31: _________________XXXXXX_________________
Data delay found: 39
14:04:05:setup_element:INFO:	Setting the data phase to 33 for uplink 24
14:04:05:setup_element:INFO:	Setting the data phase to 35 for uplink 25
14:04:05:setup_element:INFO:	Setting the data phase to 38 for uplink 26
14:04:05:setup_element:INFO:	Setting the data phase to 0 for uplink 27
14:04:05:setup_element:INFO:	Setting the data phase to 2 for uplink 28
14:04:05:setup_element:INFO:	Setting the data phase to 2 for uplink 29
14:04:05:setup_element:INFO:	Setting the data phase to 1 for uplink 30
14:04:05:setup_element:INFO:	Setting the data phase to 39 for uplink 31
==============================================OOO==============================================
14:04:05:setup_element:INFO:	Beginning SMX ASICs map scan
14:04:05:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:04:05:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:04:05:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
14:04:05:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
14:04:05:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
14:04:05:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
14:04:05:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
14:04:05:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
14:04:05:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
14:04:06:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
14:04:06:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
14:04:06:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
14:04:06:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
14:04:07:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 31
    Window Length: 70
    Eye Windows:
      Uplink 24: ___________________________________________________________________XXXXXXXXX____
      Uplink 25: ___________________________________________________________________XXXXXXXXX____
      Uplink 26: ___________________________________________________________________XXXXXXXXX____
      Uplink 27: ___________________________________________________________________XXXXXXXXX____
      Uplink 28: ____________________________________________________________________XXXXXXXXX___
      Uplink 29: ____________________________________________________________________XXXXXXXXX___
      Uplink 30: ____________________________________________________________________XXXXXXX_____
      Uplink 31: ____________________________________________________________________XXXXXXX_____
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 33
      Window Length: 34
      Eye Window: ___________XXXXXX_______________________
    Uplink 25:
      Optimal Phase: 35
      Window Length: 34
      Eye Window: _____________XXXXXX_____________________
    Uplink 26:
      Optimal Phase: 38
      Window Length: 34
      Eye Window: ________________XXXXXX__________________
    Uplink 27:
      Optimal Phase: 0
      Window Length: 35
      Eye Window: __________________XXXXX_________________
    Uplink 28:
      Optimal Phase: 2
      Window Length: 34
      Eye Window: ____________________XXXXXX______________
    Uplink 29:
      Optimal Phase: 2
      Window Length: 34
      Eye Window: ____________________XXXXXX______________
    Uplink 30:
      Optimal Phase: 1
      Window Length: 35
      Eye Window: ___________________XXXXX________________
    Uplink 31:
      Optimal Phase: 39
      Window Length: 34
      Eye Window: _________________XXXXXX_________________

==============================================OOO==============================================
14:04:07:setup_element:INFO:	Performing Elink synchronization
14:04:07:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:04:07:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:04:07:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
14:04:07:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
14:04:07:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
14:04:07:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
14:04:08:febtest:INFO:	Init all SMX (CSA): 30
14:04:15:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:04:15:febtest:INFO:	30-01 | XA-000-09-004-021-006-009-13 |  28.2 | 1153.7
14:04:15:febtest:INFO:	28-03 | XA-000-09-004-021-006-008-13 |  18.7 | 1183.3
14:04:15:febtest:INFO:	26-05 | XA-000-09-004-021-012-014-02 |  18.7 | 1183.3
14:04:16:febtest:INFO:	24-07 | XA-000-09-004-021-009-009-09 |  28.2 | 1147.8
14:04:17:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
14:04:19:ST3_smx:INFO:	chip: 30-1 	 28.225000 C 	 1165.571835 mV
14:04:19:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:04:19:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:04:19:ST3_smx:INFO:		Electrons
14:04:23:ST3_smx:INFO:	Total # of broken channels: 7
14:04:23:ST3_smx:INFO:	List of broken channels: [32, 35, 52, 54, 75, 106, 122]
14:04:23:ST3_smx:INFO:	Total # of broken channels: 0
14:04:23:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
14:04:25:ST3_smx:INFO:	chip: 28-3 	 18.745682 C 	 1189.190035 mV
14:04:25:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:04:25:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:04:25:ST3_smx:INFO:		Electrons
14:04:30:ST3_smx:INFO:	Total # of broken channels: 6
14:04:30:ST3_smx:INFO:	List of broken channels: [31, 32, 41, 49, 83, 87]
14:04:30:ST3_smx:INFO:	Total # of broken channels: 0
14:04:30:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
14:04:32:ST3_smx:INFO:	chip: 26-5 	 18.745682 C 	 1195.082160 mV
14:04:32:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:04:32:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:04:32:ST3_smx:INFO:		Electrons
14:04:36:ST3_smx:INFO:	Total # of broken channels: 4
14:04:36:ST3_smx:INFO:	List of broken channels: [26, 77, 104, 117]
14:04:36:ST3_smx:INFO:	Total # of broken channels: 0
14:04:36:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
14:04:38:ST3_smx:INFO:	chip: 24-7 	 28.225000 C 	 1159.654860 mV
14:04:38:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:04:38:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:04:38:ST3_smx:INFO:		Electrons
14:04:43:ST3_smx:INFO:	Total # of broken channels: 6
14:04:43:ST3_smx:INFO:	List of broken channels: [16, 54, 87, 100, 102, 116]
14:04:43:ST3_smx:INFO:	Total # of broken channels: 0
14:04:43:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
14:04:43:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:04:43:febtest:INFO:	30-01 | XA-000-09-004-021-006-009-13 |  28.2 | 1183.3
14:04:44:febtest:INFO:	28-03 | XA-000-09-004-021-006-008-13 |  18.7 | 1212.7
14:04:44:febtest:INFO:	26-05 | XA-000-09-004-021-012-014-02 |  18.7 | 1212.7
14:04:44:febtest:INFO:	24-07 | XA-000-09-004-021-009-009-09 |  31.4 | 1177.4
{'CSA_FRONT': 55, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 55, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 55, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 55, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 55, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 55, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 55, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 55, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 55, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 55, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 55, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 55, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_11_17-14_03_57
OPERATOR  : Alois Alzheimer
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2495| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.8406', '1.848', '1.1000']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0230', '1.850', '1.2750']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0010', '1.850', '0.2683']
14:04:45:ST3_Shared:INFO:	Listo of operators:Robert V.;
Comment