DTL-STS tests database

FEB_2506 04.12.25 09:26:36

link:
...SMX_0.root
link:
...SMX_2.root
link:
...SMX_4.root
link:
...SMX_6.root
link: XA-000-09-004-032-006-015-06
...SMX_1.root
link: XA-000-09-004-032-006-014-06
...SMX_3.root
link: XA-000-09-004-032-015-013-07
...SMX_5.root
link: XA-000-09-004-032-003-015-13
...SMX_7.root
link: XA-000-09-004-032-003-015-13
...VddmCSAstatus.root
Info
            09:26:36:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:26:36:ST3_Shared:INFO:	                       FEB-Microcable                       
09:26:36:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:26:36:febtest:INFO:	Testing FEB with SN 2506
==============================================OOO==============================================
09:26:38:smx_tester:INFO:	Scanning setup
09:26:38:elinks:INFO:	Disabling clock on downlink 0
09:26:38:elinks:INFO:	Disabling clock on downlink 1
09:26:38:elinks:INFO:	Disabling clock on downlink 2
09:26:38:elinks:INFO:	Disabling clock on downlink 3
09:26:38:elinks:INFO:	Disabling clock on downlink 4
09:26:38:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:26:38:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
09:26:38:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:26:38:elinks:INFO:	Disabling clock on downlink 0
09:26:38:elinks:INFO:	Disabling clock on downlink 1
09:26:38:elinks:INFO:	Disabling clock on downlink 2
09:26:38:elinks:INFO:	Disabling clock on downlink 3
09:26:38:elinks:INFO:	Disabling clock on downlink 4
09:26:38:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:26:38:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
09:26:38:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:26:38:elinks:INFO:	Disabling clock on downlink 0
09:26:38:elinks:INFO:	Disabling clock on downlink 1
09:26:38:elinks:INFO:	Disabling clock on downlink 2
09:26:38:elinks:INFO:	Disabling clock on downlink 3
09:26:38:elinks:INFO:	Disabling clock on downlink 4
09:26:38:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:26:38:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:26:38:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
09:26:38:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
09:26:38:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
09:26:38:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
09:26:38:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
09:26:38:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
09:26:38:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
09:26:38:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
09:26:38:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:26:38:elinks:INFO:	Disabling clock on downlink 0
09:26:38:elinks:INFO:	Disabling clock on downlink 1
09:26:38:elinks:INFO:	Disabling clock on downlink 2
09:26:38:elinks:INFO:	Disabling clock on downlink 3
09:26:38:elinks:INFO:	Disabling clock on downlink 4
09:26:38:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:26:38:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
09:26:38:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:26:38:elinks:INFO:	Disabling clock on downlink 0
09:26:38:elinks:INFO:	Disabling clock on downlink 1
09:26:38:elinks:INFO:	Disabling clock on downlink 2
09:26:38:elinks:INFO:	Disabling clock on downlink 3
09:26:38:elinks:INFO:	Disabling clock on downlink 4
09:26:38:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:26:38:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
09:26:38:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
09:26:38:setup_element:INFO:	Scanning clock phase
09:26:38:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:26:38:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:26:39:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
09:26:39:setup_element:INFO:	Eye window for uplink 24: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
09:26:39:setup_element:INFO:	Eye window for uplink 25: ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
09:26:39:setup_element:INFO:	Eye window for uplink 26: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
09:26:39:setup_element:INFO:	Eye window for uplink 27: ___________________________________________________________________XXXXXXXX_____
Clock Delay: 30
09:26:39:setup_element:INFO:	Eye window for uplink 28: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
09:26:39:setup_element:INFO:	Eye window for uplink 29: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
09:26:39:setup_element:INFO:	Eye window for uplink 30: __________________________________________________________________XXXXXXXXX_____
Clock Delay: 30
09:26:39:setup_element:INFO:	Eye window for uplink 31: __________________________________________________________________XXXXXXXXX_____
Clock Delay: 30
09:26:39:setup_element:INFO:	Setting the clock phase to 30 for group 0, downlink 2
==============================================OOO==============================================
09:26:39:setup_element:INFO:	Scanning data phases
09:26:39:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:26:39:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:26:44:setup_element:INFO:	Data phase scan results for group 0, downlink 2
09:26:44:setup_element:INFO:	Eye window for uplink 24: _____________XXXXX______________________
Data delay found: 35
09:26:44:setup_element:INFO:	Eye window for uplink 25: ______________XXXXXX____________________
Data delay found: 36
09:26:44:setup_element:INFO:	Eye window for uplink 26: ________________XXXXXXX_________________
Data delay found: 39
09:26:44:setup_element:INFO:	Eye window for uplink 27: _________________XXXXXXX________________
Data delay found: 0
09:26:44:setup_element:INFO:	Eye window for uplink 28: ____________________XXXXX_______________
Data delay found: 2
09:26:44:setup_element:INFO:	Eye window for uplink 29: ___________________XXXXXX_______________
Data delay found: 1
09:26:44:setup_element:INFO:	Eye window for uplink 30: ____________________XXXXX_______________
Data delay found: 2
09:26:44:setup_element:INFO:	Eye window for uplink 31: __________________XXXXXX________________
Data delay found: 0
09:26:44:setup_element:INFO:	Setting the data phase to 35 for uplink 24
09:26:44:setup_element:INFO:	Setting the data phase to 36 for uplink 25
09:26:44:setup_element:INFO:	Setting the data phase to 39 for uplink 26
09:26:44:setup_element:INFO:	Setting the data phase to 0 for uplink 27
09:26:44:setup_element:INFO:	Setting the data phase to 2 for uplink 28
09:26:44:setup_element:INFO:	Setting the data phase to 1 for uplink 29
09:26:44:setup_element:INFO:	Setting the data phase to 2 for uplink 30
09:26:44:setup_element:INFO:	Setting the data phase to 0 for uplink 31
==============================================OOO==============================================
09:26:44:setup_element:INFO:	Beginning SMX ASICs map scan
09:26:44:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:26:44:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:26:44:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
09:26:44:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
09:26:44:uplink:INFO:	Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
09:26:44:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
09:26:44:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
09:26:44:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
09:26:44:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
09:26:45:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
09:26:45:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
09:26:45:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
09:26:45:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
09:26:46:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 30
    Window Length: 70
    Eye Windows:
      Uplink 24: ___________________________________________________________________XXXXXXXXX____
      Uplink 25: ___________________________________________________________________XXXXXXXXX____
      Uplink 26: ___________________________________________________________________XXXXXXXX_____
      Uplink 27: ___________________________________________________________________XXXXXXXX_____
      Uplink 28: ____________________________________________________________________XXXXXXX_____
      Uplink 29: ____________________________________________________________________XXXXXXX_____
      Uplink 30: __________________________________________________________________XXXXXXXXX_____
      Uplink 31: __________________________________________________________________XXXXXXXXX_____
  Data phase characteristics:
    Uplink 24:
      Optimal Phase: 35
      Window Length: 35
      Eye Window: _____________XXXXX______________________
    Uplink 25:
      Optimal Phase: 36
      Window Length: 34
      Eye Window: ______________XXXXXX____________________
    Uplink 26:
      Optimal Phase: 39
      Window Length: 33
      Eye Window: ________________XXXXXXX_________________
    Uplink 27:
      Optimal Phase: 0
      Window Length: 33
      Eye Window: _________________XXXXXXX________________
    Uplink 28:
      Optimal Phase: 2
      Window Length: 35
      Eye Window: ____________________XXXXX_______________
    Uplink 29:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 30:
      Optimal Phase: 2
      Window Length: 35
      Eye Window: ____________________XXXXX_______________
    Uplink 31:
      Optimal Phase: 0
      Window Length: 34
      Eye Window: __________________XXXXXX________________

==============================================OOO==============================================
09:26:46:setup_element:INFO:	Performing Elink synchronization
09:26:46:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:26:46:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:26:46:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
09:26:46:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
09:26:46:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
09:26:46:uplink:INFO:	Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
09:26:47:febtest:INFO:	Init all SMX (CSA): 30
09:26:55:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:26:55:febtest:INFO:	30-01 | XA-000-09-004-032-006-015-06 |  25.1 | 1201.0
09:26:55:febtest:INFO:	28-03 | XA-000-09-004-032-006-014-06 |  37.7 | 1153.7
09:26:55:febtest:INFO:	26-05 | XA-000-09-004-032-015-013-07 |  18.7 | 1224.5
09:26:56:febtest:INFO:	24-07 | XA-000-09-004-032-003-015-13 |  25.1 | 1195.1
09:26:57:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
09:26:59:ST3_smx:INFO:	chip: 30-1 	 25.062742 C 	 1206.851500 mV
09:26:59:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:26:59:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:26:59:ST3_smx:INFO:		Electrons
09:27:03:ST3_smx:INFO:	Total # of broken channels: 4
09:27:03:ST3_smx:INFO:	List of broken channels: [13, 92, 102, 116]
09:27:03:ST3_smx:INFO:	Total # of broken channels: 0
09:27:03:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
09:27:05:ST3_smx:INFO:	chip: 28-3 	 37.726682 C 	 1165.571835 mV
09:27:05:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:27:05:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:27:05:ST3_smx:INFO:		Electrons
09:27:10:ST3_smx:INFO:	Total # of broken channels: 8
09:27:10:ST3_smx:INFO:	List of broken channels: [4, 5, 45, 48, 52, 59, 76, 125]
09:27:10:ST3_smx:INFO:	Total # of broken channels: 0
09:27:10:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
09:27:12:ST3_smx:INFO:	chip: 26-5 	 21.902970 C 	 1224.468235 mV
09:27:12:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:27:12:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:27:12:ST3_smx:INFO:		Electrons
09:27:17:ST3_smx:INFO:	Total # of broken channels: 4
09:27:17:ST3_smx:INFO:	List of broken channels: [8, 66, 106, 117]
09:27:17:ST3_smx:INFO:	Total # of broken channels: 0
09:27:17:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
09:27:18:ST3_smx:INFO:	chip: 24-7 	 28.225000 C 	 1195.082160 mV
09:27:18:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:27:18:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
09:27:18:ST3_smx:INFO:		Electrons
09:27:23:ST3_smx:INFO:	Total # of broken channels: 5
09:27:23:ST3_smx:INFO:	List of broken channels: [73, 83, 90, 110, 124]
09:27:23:ST3_smx:INFO:	Total # of broken channels: 0
09:27:23:ST3_smx:INFO:	List of broken channels: []
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
THistPainter::MakeChopt:0: RuntimeWarning: option SCAT is deprecated.
09:27:24:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:27:24:febtest:INFO:	30-01 | XA-000-09-004-032-006-015-06 |  28.2 | 1230.3
09:27:24:febtest:INFO:	28-03 | XA-000-09-004-032-006-014-06 |  40.9 | 1177.4
09:27:24:febtest:INFO:	26-05 | XA-000-09-004-032-015-013-07 |  21.9 | 1247.9
09:27:24:febtest:INFO:	24-07 | XA-000-09-004-032-003-015-13 |  28.2 | 1212.7
{'CSA_FRONT': 55, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 55, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 55, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 55, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 55, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 55, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 55, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 55, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 55, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 55, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 55, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 55, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_12_04-09_26_36
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 2506| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.8436', '1.848', '1.4100']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0020', '1.850', '1.2800']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.9951', '1.850', '0.2649']
Comment