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FEB_263 31.10.24 14:32:51
Info
14:32:51:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:32:51:ST3_Shared:INFO: FEB-Microcable
14:32:51:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:32:51:febtest:INFO: Testing FEB with SN 263
14:32:53:smx_tester:INFO: Scanning setup
14:32:53:elinks:INFO: Disabling clock on downlink 0
14:32:53:elinks:INFO: Disabling clock on downlink 1
14:32:53:elinks:INFO: Disabling clock on downlink 2
14:32:53:elinks:INFO: Disabling clock on downlink 3
14:32:53:elinks:INFO: Disabling clock on downlink 4
14:32:53:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:32:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:32:53:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:32:53:elinks:INFO: Disabling clock on downlink 0
14:32:53:elinks:INFO: Disabling clock on downlink 1
14:32:53:elinks:INFO: Disabling clock on downlink 2
14:32:53:elinks:INFO: Disabling clock on downlink 3
14:32:53:elinks:INFO: Disabling clock on downlink 4
14:32:53:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:32:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:32:53:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:32:53:elinks:INFO: Disabling clock on downlink 0
14:32:53:elinks:INFO: Disabling clock on downlink 1
14:32:53:elinks:INFO: Disabling clock on downlink 2
14:32:53:elinks:INFO: Disabling clock on downlink 3
14:32:53:elinks:INFO: Disabling clock on downlink 4
14:32:53:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:32:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:32:53:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:32:53:elinks:INFO: Disabling clock on downlink 0
14:32:53:elinks:INFO: Disabling clock on downlink 1
14:32:53:elinks:INFO: Disabling clock on downlink 2
14:32:53:elinks:INFO: Disabling clock on downlink 3
14:32:53:elinks:INFO: Disabling clock on downlink 4
14:32:53:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:32:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:32:54:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 24
14:32:54:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 25
14:32:54:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 26
14:32:54:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 27
14:32:54:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 28
14:32:54:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 29
14:32:54:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 30
14:32:54:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 31
14:32:54:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:32:54:elinks:INFO: Disabling clock on downlink 0
14:32:54:elinks:INFO: Disabling clock on downlink 1
14:32:54:elinks:INFO: Disabling clock on downlink 2
14:32:54:elinks:INFO: Disabling clock on downlink 3
14:32:54:elinks:INFO: Disabling clock on downlink 4
14:32:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:32:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:32:54:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
14:32:54:setup_element:INFO: Scanning clock phase
14:32:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:32:54:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:32:54:setup_element:INFO: Clock phase scan results for group 0, downlink 3
14:32:54:setup_element:INFO: Eye window for uplink 24: ______________________________________________________________________XXXXXX____
Clock Delay: 32
14:32:54:setup_element:INFO: Eye window for uplink 25: ________________________________________________________________________________
Clock Delay: 40
14:32:54:setup_element:INFO: Eye window for uplink 26: ________________________________________________________________________________
Clock Delay: 40
14:32:54:setup_element:INFO: Eye window for uplink 27: ______________________________________________________________________XXXX______
Clock Delay: 31
14:32:54:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXX_X__
Clock Delay: 34
14:32:54:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________________XXXXXX___
Clock Delay: 33
14:32:54:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________________XXXXXX___
Clock Delay: 33
14:32:54:setup_element:INFO: Eye window for uplink 31: ______________________________________________________________________XXXXX_____
Clock Delay: 32
14:32:54:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 3
==============================================OOO==============================================
14:32:54:setup_element:INFO: Scanning data phases
14:32:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:32:54:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:32:59:setup_element:INFO: Data phase scan results for group 0, downlink 3
14:32:59:setup_element:INFO: Eye window for uplink 24: XXX____________________________________X
Data delay found: 20
14:32:59:setup_element:INFO: Eye window for uplink 25: __XXXXX_________________________________
Data delay found: 24
14:32:59:setup_element:INFO: Eye window for uplink 26: XXX__________________________________XXX
Data delay found: 19
14:32:59:setup_element:INFO: Eye window for uplink 27: _____XXXX_______________________________
Data delay found: 26
14:32:59:setup_element:INFO: Eye window for uplink 28: _________XXXX___________________________
Data delay found: 30
14:32:59:setup_element:INFO: Eye window for uplink 29: __________XXXX__________________________
Data delay found: 31
14:32:59:setup_element:INFO: Eye window for uplink 30: ________XXXXX___________________________
Data delay found: 30
14:32:59:setup_element:INFO: Eye window for uplink 31: ___XXXXX_______________XXXXXXXXXXXXXXXXX
Data delay found: 15
14:32:59:setup_element:INFO: Setting the data phase to 20 for uplink 24
14:32:59:setup_element:INFO: Setting the data phase to 24 for uplink 25
14:32:59:setup_element:INFO: Setting the data phase to 19 for uplink 26
14:32:59:setup_element:INFO: Setting the data phase to 26 for uplink 27
14:32:59:setup_element:INFO: Setting the data phase to 30 for uplink 28
14:32:59:setup_element:INFO: Setting the data phase to 31 for uplink 29
14:32:59:setup_element:INFO: Setting the data phase to 30 for uplink 30
14:32:59:setup_element:INFO: Setting the data phase to 15 for uplink 31
==============================================OOO==============================================
14:32:59:setup_element:INFO: Beginning SMX ASICs map scan
14:32:59:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:32:59:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:32:59:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
14:32:59:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
14:32:59:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
14:32:59:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 28
14:32:59:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 24
14:33:00:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 29
14:33:00:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 25
14:33:00:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 30
14:33:00:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
14:33:00:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 31
14:33:00:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 27
14:33:02:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 3
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 28)
ASIC address 0x1: (ASIC uplink, uplink): (0, 24)
ASIC address 0x2: (ASIC uplink, uplink): (0, 29)
ASIC address 0x3: (ASIC uplink, uplink): (0, 25)
ASIC address 0x4: (ASIC uplink, uplink): (0, 30)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26)
ASIC address 0x6: (ASIC uplink, uplink): (0, 31)
ASIC address 0x7: (ASIC uplink, uplink): (0, 27)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 72
Eye Windows:
Uplink 24: ______________________________________________________________________XXXXXX____
Uplink 25: ________________________________________________________________________________
Uplink 26: ________________________________________________________________________________
Uplink 27: ______________________________________________________________________XXXX______
Uplink 28: _______________________________________________________________________XXXXX_X__
Uplink 29: _______________________________________________________________________XXXXXX___
Uplink 30: _______________________________________________________________________XXXXXX___
Uplink 31: ______________________________________________________________________XXXXX_____
Data phase characteristics:
Uplink 24:
Optimal Phase: 20
Window Length: 36
Eye Window: XXX____________________________________X
Uplink 25:
Optimal Phase: 24
Window Length: 35
Eye Window: __XXXXX_________________________________
Uplink 26:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 27:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
Uplink 28:
Optimal Phase: 30
Window Length: 36
Eye Window: _________XXXX___________________________
Uplink 29:
Optimal Phase: 31
Window Length: 36
Eye Window: __________XXXX__________________________
Uplink 30:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 31:
Optimal Phase: 15
Window Length: 15
Eye Window: ___XXXXX_______________XXXXXXXXXXXXXXXXX
==============================================OOO==============================================
14:33:02:setup_element:INFO: Performing Elink synchronization
14:33:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:33:02:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:33:02:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
14:33:02:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
==============================================OOO==============================================
14:33:02:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 3
14:33:02:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 3 | 0 | [28] | 1 | [(0, 28)]
1 | [0] | 3 | 0 | [24] | 1 | [(0, 24)]
2 | [0] | 3 | 0 | [29] | 1 | [(0, 29)]
3 | [0] | 3 | 0 | [25] | 1 | [(0, 25)]
4 | [0] | 3 | 0 | [30] | 1 | [(0, 30)]
5 | [0] | 3 | 0 | [26] | 1 | [(0, 26)]
6 | [0] | 3 | 0 | [31] | 1 | [(0, 31)]
7 | [0] | 3 | 0 | [27] | 1 | [(0, 27)]
|_________________________________________________________________________|
14:33:03:febtest:INFO: Init all SMX (CSA): 30
14:33:16:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:33:17:febtest:INFO: 28-00 | XA-000-09-004-005-004-019-06 | 40.9 | 1135.9
14:33:17:febtest:INFO: 24-01 | XA-000-09-004-004-002-018-11 | 31.4 | 1165.6
14:33:17:febtest:INFO: 29-02 | XA-000-09-004-004-002-019-11 | 44.1 | 1135.9
14:33:17:febtest:INFO: 25-03 | XA-000-09-004-004-002-017-11 | 31.4 | 1165.6
14:33:18:febtest:INFO: 30-04 | XA-000-09-004-004-003-020-06 | 37.7 | 1153.7
14:33:18:febtest:INFO: 26-05 | XA-000-09-004-004-002-015-12 | 47.3 | 1118.1
14:33:18:febtest:INFO: 31-06 | XA-000-09-004-004-003-021-06 | 53.6 | 1118.1
14:33:18:febtest:INFO: 27-07 | XA-000-09-004-004-002-014-12 | 44.1 | 1124.0
14:33:19:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
14:33:21:ST3_smx:INFO: chip: 28-0 44.073563 C 1153.732915 mV
14:33:21:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:33:21:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:33:21:ST3_smx:INFO: Electrons
14:33:21:ST3_smx:INFO: # loops 0
14:33:23:ST3_smx:INFO: # loops 1
14:33:24:ST3_smx:INFO: # loops 2
14:33:26:ST3_smx:INFO: Total # of broken channels: 0
14:33:26:ST3_smx:INFO: List of broken channels: []
14:33:26:ST3_smx:INFO: Total # of broken channels: 0
14:33:26:ST3_smx:INFO: List of broken channels: []
14:33:28:ST3_smx:INFO: chip: 24-1 31.389742 C 1183.292940 mV
14:33:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:33:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:33:28:ST3_smx:INFO: Electrons
14:33:28:ST3_smx:INFO: # loops 0
14:33:30:ST3_smx:INFO: # loops 1
14:33:31:ST3_smx:INFO: # loops 2
14:33:33:ST3_smx:INFO: Total # of broken channels: 0
14:33:33:ST3_smx:INFO: List of broken channels: []
14:33:33:ST3_smx:INFO: Total # of broken channels: 2
14:33:33:ST3_smx:INFO: List of broken channels: [118, 120]
14:33:34:ST3_smx:INFO: chip: 29-2 44.073563 C 1147.806000 mV
14:33:34:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:33:34:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:33:34:ST3_smx:INFO: Electrons
14:33:34:ST3_smx:INFO: # loops 0
14:33:36:ST3_smx:INFO: # loops 1
14:33:37:ST3_smx:INFO: # loops 2
14:33:39:ST3_smx:INFO: Total # of broken channels: 0
14:33:39:ST3_smx:INFO: List of broken channels: []
14:33:39:ST3_smx:INFO: Total # of broken channels: 12
14:33:39:ST3_smx:INFO: List of broken channels: [96, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120]
14:33:41:ST3_smx:INFO: chip: 25-3 31.389742 C 1177.390875 mV
14:33:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:33:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:33:41:ST3_smx:INFO: Electrons
14:33:41:ST3_smx:INFO: # loops 0
14:33:42:ST3_smx:INFO: # loops 1
14:33:44:ST3_smx:INFO: # loops 2
14:33:45:ST3_smx:INFO: Total # of broken channels: 0
14:33:45:ST3_smx:INFO: List of broken channels: []
14:33:45:ST3_smx:INFO: Total # of broken channels: 5
14:33:45:ST3_smx:INFO: List of broken channels: [4, 18, 80, 88, 120]
14:33:47:ST3_smx:INFO: chip: 30-4 37.726682 C 1165.571835 mV
14:33:47:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:33:47:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:33:47:ST3_smx:INFO: Electrons
14:33:47:ST3_smx:INFO: # loops 0
14:33:49:ST3_smx:INFO: # loops 1
14:33:50:ST3_smx:INFO: # loops 2
14:33:52:ST3_smx:INFO: Total # of broken channels: 0
14:33:52:ST3_smx:INFO: List of broken channels: []
14:33:52:ST3_smx:INFO: Total # of broken channels: 7
14:33:52:ST3_smx:INFO: List of broken channels: [9, 11, 13, 15, 17, 19, 21]
14:33:53:ST3_smx:INFO: chip: 26-5 47.250730 C 1129.995435 mV
14:33:53:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:33:53:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:33:53:ST3_smx:INFO: Electrons
14:33:53:ST3_smx:INFO: # loops 0
14:33:55:ST3_smx:INFO: # loops 1
14:33:56:ST3_smx:INFO: # loops 2
14:33:58:ST3_smx:INFO: Total # of broken channels: 0
14:33:58:ST3_smx:INFO: List of broken channels: []
14:33:58:ST3_smx:INFO: Total # of broken channels: 1
14:33:58:ST3_smx:INFO: List of broken channels: [118]
14:34:00:ST3_smx:INFO: chip: 31-6 53.612520 C 1124.048640 mV
14:34:00:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:34:00:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:34:00:ST3_smx:INFO: Electrons
14:34:00:ST3_smx:INFO: # loops 0
14:34:01:ST3_smx:INFO: # loops 1
14:34:03:ST3_smx:INFO: # loops 2
14:34:04:ST3_smx:INFO: Total # of broken channels: 0
14:34:04:ST3_smx:INFO: List of broken channels: []
14:34:04:ST3_smx:INFO: Total # of broken channels: 4
14:34:04:ST3_smx:INFO: List of broken channels: [2, 4, 6, 8]
14:34:06:ST3_smx:INFO: chip: 27-7 44.073563 C 1129.995435 mV
14:34:06:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:34:06:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:34:06:ST3_smx:INFO: Electrons
14:34:06:ST3_smx:INFO: # loops 0
14:34:08:ST3_smx:INFO: # loops 1
14:34:09:ST3_smx:INFO: # loops 2
14:34:11:ST3_smx:INFO: Total # of broken channels: 0
14:34:11:ST3_smx:INFO: List of broken channels: []
14:34:11:ST3_smx:INFO: Total # of broken channels: 1
14:34:11:ST3_smx:INFO: List of broken channels: [30]
14:34:11:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:34:12:febtest:INFO: 28-00 | XA-000-09-004-005-004-019-06 | 40.9 | 1171.5
14:34:12:febtest:INFO: 24-01 | XA-000-09-004-004-002-018-11 | 31.4 | 1218.6
14:34:12:febtest:INFO: 29-02 | XA-000-09-004-004-002-019-11 | 44.1 | 1171.5
14:34:12:febtest:INFO: 25-03 | XA-000-09-004-004-002-017-11 | 31.4 | 1201.0
14:34:12:febtest:INFO: 30-04 | XA-000-09-004-004-003-020-06 | 40.9 | 1183.3
14:34:13:febtest:INFO: 26-05 | XA-000-09-004-004-002-015-12 | 47.3 | 1147.8
14:34:13:febtest:INFO: 31-06 | XA-000-09-004-004-003-021-06 | 53.6 | 1147.8
14:34:13:febtest:INFO: 27-07 | XA-000-09-004-004-002-014-12 | 47.3 | 1153.7
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_10_31-14_32_51
OPERATOR : Robert V.; Irakli K.;
SITE : GSI | SETUP : GSI_TEST_SETUP_2
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| FEB_SN : 263| FEB_TYPE : 8.1| FEB_UPLINKS : 1| FEB_B
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VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.8350', '1.849', '2.4420']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9750', '1.849', '2.6220']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9790', '1.850', '0.5301']