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FEB_264 31.10.24 14:23:37
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14:23:37:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:23:37:ST3_Shared:INFO: FEB-Microcable
14:23:37:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:23:37:febtest:INFO: Testing FEB with SN 264
14:23:38:smx_tester:INFO: Scanning setup
14:23:38:elinks:INFO: Disabling clock on downlink 0
14:23:38:elinks:INFO: Disabling clock on downlink 1
14:23:38:elinks:INFO: Disabling clock on downlink 2
14:23:38:elinks:INFO: Disabling clock on downlink 3
14:23:38:elinks:INFO: Disabling clock on downlink 4
14:23:38:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:23:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:23:38:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:23:38:elinks:INFO: Disabling clock on downlink 0
14:23:38:elinks:INFO: Disabling clock on downlink 1
14:23:38:elinks:INFO: Disabling clock on downlink 2
14:23:38:elinks:INFO: Disabling clock on downlink 3
14:23:38:elinks:INFO: Disabling clock on downlink 4
14:23:38:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:23:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:23:38:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:23:38:elinks:INFO: Disabling clock on downlink 0
14:23:38:elinks:INFO: Disabling clock on downlink 1
14:23:38:elinks:INFO: Disabling clock on downlink 2
14:23:38:elinks:INFO: Disabling clock on downlink 3
14:23:38:elinks:INFO: Disabling clock on downlink 4
14:23:38:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:23:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:23:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:23:39:elinks:INFO: Disabling clock on downlink 0
14:23:39:elinks:INFO: Disabling clock on downlink 1
14:23:39:elinks:INFO: Disabling clock on downlink 2
14:23:39:elinks:INFO: Disabling clock on downlink 3
14:23:39:elinks:INFO: Disabling clock on downlink 4
14:23:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:23:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:23:39:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 24
14:23:39:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 25
14:23:39:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 26
14:23:39:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 27
14:23:39:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 28
14:23:39:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 30
14:23:39:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 31
14:23:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:23:39:elinks:INFO: Disabling clock on downlink 0
14:23:39:elinks:INFO: Disabling clock on downlink 1
14:23:39:elinks:INFO: Disabling clock on downlink 2
14:23:39:elinks:INFO: Disabling clock on downlink 3
14:23:39:elinks:INFO: Disabling clock on downlink 4
14:23:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:23:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:23:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
14:23:39:setup_element:INFO: Scanning clock phase
14:23:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:23:39:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:23:39:setup_element:INFO: Clock phase scan results for group 0, downlink 3
14:23:39:setup_element:INFO: Eye window for uplink 24: ____________________________________________________________________XXXXXX_X____
Clock Delay: 31
14:23:39:setup_element:INFO: Eye window for uplink 25: ________________________________________________________________________________
Clock Delay: 40
14:23:39:setup_element:INFO: Eye window for uplink 26: _______________________________________________________________________XXXXX____
Clock Delay: 33
14:23:39:setup_element:INFO: Eye window for uplink 27: ________________________________________________________________________________
Clock Delay: 40
14:23:39:setup_element:INFO: Eye window for uplink 28: ________________________________________________________________________________
Clock Delay: 40
14:23:39:setup_element:INFO: Eye window for uplink 30: ________________________________________________________________________________
Clock Delay: 40
14:23:39:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________________XXXXXX___
Clock Delay: 33
14:23:39:setup_element:INFO: Setting the clock phase to 32 for group 0, downlink 3
==============================================OOO==============================================
14:23:39:setup_element:INFO: Scanning data phases
14:23:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:23:39:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:23:44:setup_element:INFO: Data phase scan results for group 0, downlink 3
14:23:44:setup_element:INFO: Eye window for uplink 24: XXXX__________________________________XX
Data delay found: 20
14:23:44:setup_element:INFO: Eye window for uplink 25: _XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 20
14:23:45:setup_element:INFO: Eye window for uplink 26: XXXXX__________________________________X
Data delay found: 21
14:23:45:setup_element:INFO: Eye window for uplink 27: _XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 20
14:23:45:setup_element:INFO: Eye window for uplink 28: _XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 20
14:23:45:setup_element:INFO: Eye window for uplink 30: _XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 20
14:23:45:setup_element:INFO: Eye window for uplink 31: _______XXXXXX___________________________
Data delay found: 29
14:23:45:setup_element:INFO: Setting the data phase to 20 for uplink 24
14:23:45:setup_element:INFO: Setting the data phase to 20 for uplink 25
14:23:45:setup_element:INFO: Setting the data phase to 21 for uplink 26
14:23:45:setup_element:INFO: Setting the data phase to 20 for uplink 27
14:23:45:setup_element:INFO: Setting the data phase to 20 for uplink 28
14:23:45:setup_element:INFO: Setting the data phase to 20 for uplink 30
14:23:45:setup_element:INFO: Setting the data phase to 29 for uplink 31
==============================================OOO==============================================
14:23:45:setup_element:INFO: Beginning SMX ASICs map scan
14:23:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:23:45:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:23:45:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
14:23:45:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
14:23:45:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 30, 31]
14:23:45:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 28
14:23:45:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 24
14:23:45:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 25
14:23:45:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 30
14:23:46:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
14:23:46:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 31
14:23:46:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 27
14:23:47:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 3
Uplinks: [24, 25, 26, 27, 28, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 28)
ASIC address 0x1: (ASIC uplink, uplink): (0, 24)
ASIC address 0x3: (ASIC uplink, uplink): (0, 25)
ASIC address 0x4: (ASIC uplink, uplink): (0, 30)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26)
ASIC address 0x6: (ASIC uplink, uplink): (0, 31)
ASIC address 0x7: (ASIC uplink, uplink): (0, 27)
Clock Phase Characteristic:
Optimal Phase: 32
Window Length: 71
Eye Windows:
Uplink 24: ____________________________________________________________________XXXXXX_X____
Uplink 25: ________________________________________________________________________________
Uplink 26: _______________________________________________________________________XXXXX____
Uplink 27: ________________________________________________________________________________
Uplink 28: ________________________________________________________________________________
Uplink 30: ________________________________________________________________________________
Uplink 31: _______________________________________________________________________XXXXXX___
Data phase characteristics:
Uplink 24:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 25:
Optimal Phase: 20
Window Length: 1
Eye Window: _XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 26:
Optimal Phase: 21
Window Length: 34
Eye Window: XXXXX__________________________________X
Uplink 27:
Optimal Phase: 20
Window Length: 1
Eye Window: _XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 28:
Optimal Phase: 20
Window Length: 1
Eye Window: _XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 30:
Optimal Phase: 20
Window Length: 1
Eye Window: _XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 31:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
==============================================OOO==============================================
14:23:47:setup_element:INFO: Performing Elink synchronization
14:23:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:23:47:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:23:47:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
14:23:47:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
==============================================OOO==============================================
14:23:47:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 3
14:23:47:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 3 | 0 | [28] | 1 | [(0, 28)]
1 | [0] | 3 | 0 | [24] | 1 | [(0, 24)]
3 | [0] | 3 | 0 | [25] | 1 | [(0, 25)]
4 | [0] | 3 | 0 | [30] | 1 | [(0, 30)]
5 | [0] | 3 | 0 | [26] | 1 | [(0, 26)]
6 | [0] | 3 | 0 | [31] | 1 | [(0, 31)]
7 | [0] | 3 | 0 | [27] | 1 | [(0, 27)]
|_________________________________________________________________________|
14:23:48:febtest:INFO: Init all SMX (CSA): 30
14:24:00:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:24:00:febtest:INFO: 28-00 | XA-000-09-004-005-008-003-11 | 28.2 | 1177.4
14:24:01:febtest:INFO: 24-01 | XA-000-09-004-005-004-009-01 | 15.6 | 1230.3
14:24:01:febtest:INFO: 25-03 | XA-000-09-004-005-009-014-06 | 31.4 | 1159.7
14:24:01:febtest:INFO: 30-04 | XA-000-09-004-005-016-020-12 | 28.2 | 1171.5
14:24:01:febtest:INFO: 26-05 | XA-000-09-004-005-005-024-11 | 37.7 | 1130.0
14:24:01:febtest:INFO: 31-06 | XA-000-09-004-004-018-019-07 | 28.2 | 1183.3
14:24:02:febtest:INFO: 27-07 | XA-000-09-004-005-006-012-02 | 28.2 | 1171.5
14:24:03:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
14:24:03:febtest:ERROR: HW addres 3 != 2
14:24:09:ST3_smx:INFO: chip: 28-0 28.225000 C 1183.292940 mV
14:24:09:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:24:09:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:24:09:ST3_smx:INFO: Electrons
14:24:09:ST3_smx:INFO: # loops 0
14:24:10:ST3_smx:INFO: # loops 1
14:24:12:ST3_smx:INFO: # loops 2
14:24:14:ST3_smx:INFO: Total # of broken channels: 2
14:24:14:ST3_smx:INFO: List of broken channels: [0, 2]
14:24:14:ST3_smx:INFO: Total # of broken channels: 71
14:24:14:ST3_smx:INFO: List of broken channels: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, 97, 99, 101, 103, 105, 107, 109, 111, 113, 115, 117, 119, 121, 123, 125]
14:24:16:ST3_smx:INFO: chip: 24-1 15.590880 C 1253.730060 mV
14:24:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:24:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:24:16:ST3_smx:INFO: Electrons
14:24:16:ST3_smx:INFO: # loops 0
14:24:17:ST3_smx:INFO: # loops 1
14:24:19:ST3_smx:INFO: # loops 2
14:24:20:ST3_smx:INFO: Total # of broken channels: 2
14:24:20:ST3_smx:INFO: List of broken channels: [83, 113]
14:24:20:ST3_smx:INFO: Total # of broken channels: 64
14:24:20:ST3_smx:INFO: List of broken channels: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, 97, 99, 101, 103, 105, 107, 109, 111, 113, 115, 117, 119, 121, 123, 125, 127]
14:24:22:ST3_smx:INFO: chip: 25-3 31.389742 C 1171.483840 mV
14:24:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:24:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:24:22:ST3_smx:INFO: Electrons
14:24:22:ST3_smx:INFO: # loops 0
14:24:24:ST3_smx:INFO: # loops 1
14:24:25:ST3_smx:INFO: # loops 2
14:24:27:ST3_smx:INFO: Total # of broken channels: 11
14:24:27:ST3_smx:INFO: List of broken channels: [99, 103, 107, 109, 111, 113, 115, 117, 119, 121, 123]
14:24:27:ST3_smx:INFO: Total # of broken channels: 63
14:24:27:ST3_smx:INFO: List of broken channels: [3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, 97, 99, 101, 103, 105, 107, 109, 111, 113, 115, 117, 119, 121, 123, 125, 127]
14:24:28:ST3_smx:INFO: chip: 30-4 28.225000 C 1183.292940 mV
14:24:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:24:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:24:28:ST3_smx:INFO: Electrons
14:24:28:ST3_smx:INFO: # loops 0
14:24:30:ST3_smx:INFO: # loops 1
14:24:31:ST3_smx:INFO: # loops 2
14:24:33:ST3_smx:INFO: Total # of broken channels: 0
14:24:33:ST3_smx:INFO: List of broken channels: []
14:24:33:ST3_smx:INFO: Total # of broken channels: 0
14:24:33:ST3_smx:INFO: List of broken channels: []
14:24:35:ST3_smx:INFO: chip: 26-5 40.898880 C 1141.874115 mV
14:24:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:24:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:24:35:ST3_smx:INFO: Electrons
14:24:35:ST3_smx:INFO: # loops 0
14:24:36:ST3_smx:INFO: # loops 1
14:24:37:ST3_smx:INFO: # loops 2
14:24:39:ST3_smx:INFO: Total # of broken channels: 0
14:24:39:ST3_smx:INFO: List of broken channels: []
14:24:39:ST3_smx:INFO: Total # of broken channels: 0
14:24:39:ST3_smx:INFO: List of broken channels: []
14:24:41:ST3_smx:INFO: chip: 31-6 28.225000 C 1189.190035 mV
14:24:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:24:41:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:24:41:ST3_smx:INFO: Electrons
14:24:41:ST3_smx:INFO: # loops 0
14:24:42:ST3_smx:INFO: # loops 1
14:24:44:ST3_smx:INFO: # loops 2
14:24:45:ST3_smx:INFO: Total # of broken channels: 0
14:24:45:ST3_smx:INFO: List of broken channels: []
14:24:45:ST3_smx:INFO: Total # of broken channels: 0
14:24:45:ST3_smx:INFO: List of broken channels: []
14:24:47:ST3_smx:INFO: chip: 27-7 31.389742 C 1183.292940 mV
14:24:47:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:24:47:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:24:47:ST3_smx:INFO: Electrons
14:24:47:ST3_smx:INFO: # loops 0
14:24:48:ST3_smx:INFO: # loops 1
14:24:50:ST3_smx:INFO: # loops 2
14:24:51:ST3_smx:INFO: Total # of broken channels: 0
14:24:51:ST3_smx:INFO: List of broken channels: []
14:24:51:ST3_smx:INFO: Total # of broken channels: 0
14:24:51:ST3_smx:INFO: List of broken channels: []
14:24:52:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:24:52:febtest:INFO: 28-00 | XA-000-09-004-005-008-003-11 | 28.2 | 1206.9
14:24:52:febtest:INFO: 24-01 | XA-000-09-004-005-004-009-01 | 15.6 | 1311.9
14:24:52:febtest:INFO: 25-03 | XA-000-09-004-005-009-014-06 | 31.4 | 1195.1
14:24:53:febtest:INFO: 30-04 | XA-000-09-004-005-016-020-12 | 31.4 | 1201.0
14:24:53:febtest:INFO: 26-05 | XA-000-09-004-005-005-024-11 | 40.9 | 1159.7
14:24:53:febtest:INFO: 31-06 | XA-000-09-004-004-018-019-07 | 28.2 | 1206.9
14:24:53:febtest:INFO: 27-07 | XA-000-09-004-005-006-012-02 | 31.4 | 1206.9
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_10_31-14_23_37
OPERATOR : Robert V.; Irakli K.;
SITE : GSI | SETUP : GSI_TEST_SETUP_2
------------------------------------------------------------
| FEB_SN : 264| FEB_TYPE : 8.1| FEB_UPLINKS : 1| FEB_B
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.8360', '1.849', '2.4980']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9190', '1.850', '2.5600']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.8940', '1.850', '0.7418']