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FEB_265 31.10.24 14:17:26
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14:17:26:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:17:26:ST3_Shared:INFO: FEB-Microcable
14:17:26:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:17:26:febtest:INFO: Testing FEB with SN 265
14:17:27:smx_tester:INFO: Scanning setup
14:17:27:elinks:INFO: Disabling clock on downlink 0
14:17:27:elinks:INFO: Disabling clock on downlink 1
14:17:27:elinks:INFO: Disabling clock on downlink 2
14:17:27:elinks:INFO: Disabling clock on downlink 3
14:17:27:elinks:INFO: Disabling clock on downlink 4
14:17:27:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:17:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:17:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:17:28:elinks:INFO: Disabling clock on downlink 0
14:17:28:elinks:INFO: Disabling clock on downlink 1
14:17:28:elinks:INFO: Disabling clock on downlink 2
14:17:28:elinks:INFO: Disabling clock on downlink 3
14:17:28:elinks:INFO: Disabling clock on downlink 4
14:17:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:17:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:17:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:17:28:elinks:INFO: Disabling clock on downlink 0
14:17:28:elinks:INFO: Disabling clock on downlink 1
14:17:28:elinks:INFO: Disabling clock on downlink 2
14:17:28:elinks:INFO: Disabling clock on downlink 3
14:17:28:elinks:INFO: Disabling clock on downlink 4
14:17:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:17:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:17:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:17:28:elinks:INFO: Disabling clock on downlink 0
14:17:28:elinks:INFO: Disabling clock on downlink 1
14:17:28:elinks:INFO: Disabling clock on downlink 2
14:17:28:elinks:INFO: Disabling clock on downlink 3
14:17:28:elinks:INFO: Disabling clock on downlink 4
14:17:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:17:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:17:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 24
14:17:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 25
14:17:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 26
14:17:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 27
14:17:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 28
14:17:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 29
14:17:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 30
14:17:28:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 31
14:17:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:17:28:elinks:INFO: Disabling clock on downlink 0
14:17:28:elinks:INFO: Disabling clock on downlink 1
14:17:28:elinks:INFO: Disabling clock on downlink 2
14:17:28:elinks:INFO: Disabling clock on downlink 3
14:17:28:elinks:INFO: Disabling clock on downlink 4
14:17:28:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:17:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:17:28:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
14:17:28:setup_element:INFO: Scanning clock phase
14:17:28:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:17:28:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:17:29:setup_element:INFO: Clock phase scan results for group 0, downlink 3
14:17:29:setup_element:INFO: Eye window for uplink 24: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
14:17:29:setup_element:INFO: Eye window for uplink 25: _____________________________________________________________________XXXXXX_____
Clock Delay: 31
14:17:29:setup_element:INFO: Eye window for uplink 26: _____________________________________________________________________XXXXXX_____
Clock Delay: 31
14:17:29:setup_element:INFO: Eye window for uplink 27: ________________________________________________________________________________
Clock Delay: 40
14:17:29:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXXX___
Clock Delay: 33
14:17:29:setup_element:INFO: Eye window for uplink 29: ________________________________________________________________________________
Clock Delay: 40
14:17:29:setup_element:INFO: Eye window for uplink 30: ________________________________________________________________________________
Clock Delay: 40
14:17:29:setup_element:INFO: Eye window for uplink 31: ________________________________________________________________________________
Clock Delay: 40
14:17:29:setup_element:INFO: Setting the clock phase to 32 for group 0, downlink 3
==============================================OOO==============================================
14:17:29:setup_element:INFO: Scanning data phases
14:17:29:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:17:29:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:17:34:setup_element:INFO: Data phase scan results for group 0, downlink 3
14:17:34:setup_element:INFO: Eye window for uplink 24: XXX___________________________________XX
Data delay found: 20
14:17:34:setup_element:INFO: Eye window for uplink 25: XXXX__________________________________XX
Data delay found: 20
14:17:34:setup_element:INFO: Eye window for uplink 26: XXXXX___________________________________
Data delay found: 22
14:17:34:setup_element:WARNING: Group 0, downlink 3, uplink 27: No True values in scanned data!
Traceback (most recent call last):
File "/home/cbm/ST3_BASE/smx_software_FEB8_2_20MHz/python/hctsp/setup_element.py", line 261, in characterize_data_phases
data_delay, window_len = find_center(fcl)
File "/home/cbm/ST3_BASE/smx_software_FEB8_2_20MHz/python/hctsp/hctsp.py", line 87, in find_center
raise Exception("No True values in scanned data!")
Exception: No True values in scanned data!
14:17:34:setup_element:INFO: Eye window for uplink 28: _________XXXX___________________________
Data delay found: 30
14:17:34:setup_element:WARNING: Group 0, downlink 3, uplink 29: No True values in scanned data!
Traceback (most recent call last):
File "/home/cbm/ST3_BASE/smx_software_FEB8_2_20MHz/python/hctsp/setup_element.py", line 261, in characterize_data_phases
data_delay, window_len = find_center(fcl)
File "/home/cbm/ST3_BASE/smx_software_FEB8_2_20MHz/python/hctsp/hctsp.py", line 87, in find_center
raise Exception("No True values in scanned data!")
Exception: No True values in scanned data!
14:17:34:setup_element:INFO: Eye window for uplink 30: ______XXXXX________XXXXXXXXXXXXXXXXXXXXX
Data delay found: 14
14:17:34:setup_element:INFO: Eye window for uplink 31: _____XXXX_______________________________
Data delay found: 26
14:17:34:setup_element:INFO: Setting the data phase to 20 for uplink 24
14:17:34:setup_element:INFO: Setting the data phase to 20 for uplink 25
14:17:34:setup_element:INFO: Setting the data phase to 22 for uplink 26
14:17:34:setup_element:INFO: Setting the data phase to 30 for uplink 28
14:17:34:setup_element:INFO: Setting the data phase to 14 for uplink 30
14:17:34:setup_element:INFO: Setting the data phase to 26 for uplink 31
==============================================OOO==============================================
14:17:34:setup_element:INFO: Beginning SMX ASICs map scan
14:17:34:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:17:34:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:17:34:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
14:17:34:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
14:17:34:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
14:17:34:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 28
14:17:34:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 24
14:17:34:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 29
14:17:34:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 25
14:17:35:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 30
14:17:35:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
14:17:35:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 31
14:17:35:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 27
14:17:36:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 3
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 28)
ASIC address 0x1: (ASIC uplink, uplink): (0, 24)
ASIC address 0x2: (ASIC uplink, uplink): (0, 29)
ASIC address 0x3: (ASIC uplink, uplink): (0, 25)
ASIC address 0x4: (ASIC uplink, uplink): (0, 30)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26)
ASIC address 0x6: (ASIC uplink, uplink): (0, 31)
ASIC address 0x7: (ASIC uplink, uplink): (0, 27)
Clock Phase Characteristic:
Optimal Phase: 32
Window Length: 71
Eye Windows:
Uplink 24: ____________________________________________________________________XXXXXXX_____
Uplink 25: _____________________________________________________________________XXXXXX_____
Uplink 26: _____________________________________________________________________XXXXXX_____
Uplink 27: ________________________________________________________________________________
Uplink 28: _______________________________________________________________________XXXXXX___
Uplink 29: ________________________________________________________________________________
Uplink 30: ________________________________________________________________________________
Uplink 31: ________________________________________________________________________________
Data phase characteristics:
Uplink 24:
Optimal Phase: 20
Window Length: 35
Eye Window: XXX___________________________________XX
Uplink 25:
Optimal Phase: 20
Window Length: 34
Eye Window: XXXX__________________________________XX
Uplink 26:
Optimal Phase: 22
Window Length: 35
Eye Window: XXXXX___________________________________
Uplink 28:
Optimal Phase: 30
Window Length: 36
Eye Window: _________XXXX___________________________
Uplink 30:
Optimal Phase: 14
Window Length: 8
Eye Window: ______XXXXX________XXXXXXXXXXXXXXXXXXXXX
Uplink 31:
Optimal Phase: 26
Window Length: 36
Eye Window: _____XXXX_______________________________
==============================================OOO==============================================
14:17:36:setup_element:INFO: Performing Elink synchronization
14:17:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:17:36:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:17:36:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
14:17:36:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
==============================================OOO==============================================
14:17:36:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 3
14:17:36:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 3 | 0 | [28] | 1 | [(0, 28)]
1 | [0] | 3 | 0 | [24] | 1 | [(0, 24)]
2 | [0] | 3 | 0 | [29] | 1 | [(0, 29)]
3 | [0] | 3 | 0 | [25] | 1 | [(0, 25)]
4 | [0] | 3 | 0 | [30] | 1 | [(0, 30)]
5 | [0] | 3 | 0 | [26] | 1 | [(0, 26)]
6 | [0] | 3 | 0 | [31] | 1 | [(0, 31)]
7 | [0] | 3 | 0 | [27] | 1 | [(0, 27)]
|_________________________________________________________________________|
14:17:37:febtest:INFO: Init all SMX (CSA): 30
14:17:51:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:17:52:febtest:INFO: 28-00 | XA-000-09-004-012-012-010-10 | 15.6 | 1206.9
14:17:52:febtest:INFO: 24-01 | XA-000-09-004-012-009-009-01 | 21.9 | 1171.5
14:17:52:febtest:INFO: 29-02 | XA-000-09-004-012-010-012-15 | 31.4 | 1153.7
14:17:52:febtest:INFO: 25-03 | XA-000-09-004-012-008-009-12 | 40.9 | 1124.0
14:17:52:febtest:INFO: 30-04 | XA-000-09-004-012-010-013-15 | 37.7 | 1130.0
14:17:53:febtest:INFO: 26-05 | XA-000-09-004-012-008-011-12 | 31.4 | 1147.8
14:17:53:febtest:INFO: 31-06 | XA-000-09-004-012-010-016-08 | 40.9 | 1135.9
14:17:53:febtest:INFO: 27-07 | XA-000-09-004-012-009-002-01 | 34.6 | 1141.9
14:17:54:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
14:17:56:ST3_smx:INFO: chip: 28-0 15.590880 C 1218.600960 mV
14:17:56:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:17:56:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:17:56:ST3_smx:INFO: Electrons
14:17:56:ST3_smx:INFO: # loops 0
14:17:58:ST3_smx:INFO: # loops 1
14:17:59:ST3_smx:INFO: # loops 2
14:18:01:ST3_smx:INFO: Total # of broken channels: 1
14:18:01:ST3_smx:INFO: List of broken channels: [45]
14:18:01:ST3_smx:INFO: Total # of broken channels: 0
14:18:01:ST3_smx:INFO: List of broken channels: []
14:18:03:ST3_smx:INFO: chip: 24-1 21.902970 C 1195.082160 mV
14:18:03:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:03:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:03:ST3_smx:INFO: Electrons
14:18:03:ST3_smx:INFO: # loops 0
14:18:05:ST3_smx:INFO: # loops 1
14:18:06:ST3_smx:INFO: # loops 2
14:18:08:ST3_smx:INFO: Total # of broken channels: 0
14:18:08:ST3_smx:INFO: List of broken channels: []
14:18:08:ST3_smx:INFO: Total # of broken channels: 0
14:18:08:ST3_smx:INFO: List of broken channels: []
14:18:10:ST3_smx:INFO: chip: 29-2 31.389742 C 1165.571835 mV
14:18:10:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:10:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:10:ST3_smx:INFO: Electrons
14:18:10:ST3_smx:INFO: # loops 0
14:18:11:ST3_smx:INFO: # loops 1
14:18:13:ST3_smx:INFO: # loops 2
14:18:15:ST3_smx:INFO: Total # of broken channels: 0
14:18:15:ST3_smx:INFO: List of broken channels: []
14:18:15:ST3_smx:INFO: Total # of broken channels: 0
14:18:15:ST3_smx:INFO: List of broken channels: []
14:18:16:ST3_smx:INFO: chip: 25-3 40.898880 C 1135.937260 mV
14:18:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:16:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:16:ST3_smx:INFO: Electrons
14:18:16:ST3_smx:INFO: # loops 0
14:18:18:ST3_smx:INFO: # loops 1
14:18:19:ST3_smx:INFO: # loops 2
14:18:21:ST3_smx:INFO: Total # of broken channels: 0
14:18:21:ST3_smx:INFO: List of broken channels: []
14:18:21:ST3_smx:INFO: Total # of broken channels: 0
14:18:21:ST3_smx:INFO: List of broken channels: []
14:18:23:ST3_smx:INFO: chip: 30-4 37.726682 C 1147.806000 mV
14:18:23:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:23:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:23:ST3_smx:INFO: Electrons
14:18:23:ST3_smx:INFO: # loops 0
14:18:25:ST3_smx:INFO: # loops 1
14:18:26:ST3_smx:INFO: # loops 2
14:18:28:ST3_smx:INFO: Total # of broken channels: 0
14:18:28:ST3_smx:INFO: List of broken channels: []
14:18:28:ST3_smx:INFO: Total # of broken channels: 0
14:18:28:ST3_smx:INFO: List of broken channels: []
14:18:29:ST3_smx:INFO: chip: 26-5 31.389742 C 1159.654860 mV
14:18:29:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:29:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:29:ST3_smx:INFO: Electrons
14:18:29:ST3_smx:INFO: # loops 0
14:18:31:ST3_smx:INFO: # loops 1
14:18:33:ST3_smx:INFO: # loops 2
14:18:34:ST3_smx:INFO: Total # of broken channels: 1
14:18:34:ST3_smx:INFO: List of broken channels: [122]
14:18:34:ST3_smx:INFO: Total # of broken channels: 0
14:18:34:ST3_smx:INFO: List of broken channels: []
14:18:36:ST3_smx:INFO: chip: 31-6 40.898880 C 1141.874115 mV
14:18:36:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:36:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:36:ST3_smx:INFO: Electrons
14:18:36:ST3_smx:INFO: # loops 0
14:18:38:ST3_smx:INFO: # loops 1
14:18:39:ST3_smx:INFO: # loops 2
14:18:41:ST3_smx:INFO: Total # of broken channels: 0
14:18:41:ST3_smx:INFO: List of broken channels: []
14:18:41:ST3_smx:INFO: Total # of broken channels: 0
14:18:41:ST3_smx:INFO: List of broken channels: []
14:18:42:ST3_smx:INFO: chip: 27-7 34.556970 C 1153.732915 mV
14:18:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:18:42:ST3_smx:INFO: Electrons
14:18:42:ST3_smx:INFO: # loops 0
14:18:44:ST3_smx:INFO: # loops 1
14:18:46:ST3_smx:INFO: # loops 2
14:18:47:ST3_smx:INFO: Total # of broken channels: 0
14:18:47:ST3_smx:INFO: List of broken channels: []
14:18:47:ST3_smx:INFO: Total # of broken channels: 0
14:18:47:ST3_smx:INFO: List of broken channels: []
14:18:47:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:18:48:febtest:INFO: 28-00 | XA-000-09-004-012-012-010-10 | 15.6 | 1236.2
14:18:48:febtest:INFO: 24-01 | XA-000-09-004-012-009-009-01 | 21.9 | 1212.7
14:18:48:febtest:INFO: 29-02 | XA-000-09-004-012-010-012-15 | 31.4 | 1183.3
14:18:48:febtest:INFO: 25-03 | XA-000-09-004-012-008-009-12 | 40.9 | 1153.7
14:18:49:febtest:INFO: 30-04 | XA-000-09-004-012-010-013-15 | 40.9 | 1165.6
14:18:49:febtest:INFO: 26-05 | XA-000-09-004-012-008-011-12 | 34.6 | 1177.4
14:18:49:febtest:INFO: 31-06 | XA-000-09-004-012-010-016-08 | 40.9 | 1165.6
14:18:49:febtest:INFO: 27-07 | XA-000-09-004-012-009-002-01 | 37.7 | 1171.5
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
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# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_10_31-14_17_26
OPERATOR : Alois Alzheimer
SITE : GSI | SETUP : GSI_TEST_SETUP_2
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| FEB_SN : 265| FEB_TYPE : 8.1| FEB_UPLINKS : 1| FEB_B
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VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0030', '1.849', '2.7000']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0220', '1.850', '2.6210']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9920', '1.850', '0.5294']
14:18:50:ST3_Shared:INFO: Listo of operators:Robert V.;
14:18:50:ST3_Shared:INFO: Listo of operators:Robert V.; Irakli K.;