10:47:15:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:47:15:ST3_Shared:INFO:	                       FEB-Microcable                       
10:47:15:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:47:15:febtest:INFO:	Testing FEB with SN 3088
10:47:17:smx_tester:INFO:	Scanning setup
10:47:17:elinks:INFO:	Disabling clock on downlink 0
10:47:17:elinks:INFO:	Disabling clock on downlink 1
10:47:17:elinks:INFO:	Disabling clock on downlink 2
10:47:17:elinks:INFO:	Disabling clock on downlink 3
10:47:17:elinks:INFO:	Disabling clock on downlink 4
10:47:17:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:47:17:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
10:47:17:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:47:17:elinks:INFO:	Disabling clock on downlink 0
10:47:17:elinks:INFO:	Disabling clock on downlink 1
10:47:17:elinks:INFO:	Disabling clock on downlink 2
10:47:17:elinks:INFO:	Disabling clock on downlink 3
10:47:17:elinks:INFO:	Disabling clock on downlink 4
10:47:17:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:47:17:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
10:47:17:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 8
10:47:17:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 9
10:47:17:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 14
10:47:17:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 15
10:47:17:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:47:17:elinks:INFO:	Disabling clock on downlink 0
10:47:17:elinks:INFO:	Disabling clock on downlink 1
10:47:17:elinks:INFO:	Disabling clock on downlink 2
10:47:17:elinks:INFO:	Disabling clock on downlink 3
10:47:17:elinks:INFO:	Disabling clock on downlink 4
10:47:17:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:47:17:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:47:17:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:47:17:elinks:INFO:	Disabling clock on downlink 0
10:47:17:elinks:INFO:	Disabling clock on downlink 1
10:47:17:elinks:INFO:	Disabling clock on downlink 2
10:47:17:elinks:INFO:	Disabling clock on downlink 3
10:47:17:elinks:INFO:	Disabling clock on downlink 4
10:47:17:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:47:17:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
10:47:17:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:47:17:elinks:INFO:	Disabling clock on downlink 0
10:47:17:elinks:INFO:	Disabling clock on downlink 1
10:47:17:elinks:INFO:	Disabling clock on downlink 2
10:47:17:elinks:INFO:	Disabling clock on downlink 3
10:47:17:elinks:INFO:	Disabling clock on downlink 4
10:47:17:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:47:17:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
10:47:17:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
10:47:18:setup_element:INFO:	Scanning clock phase
10:47:18:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
10:47:18:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:47:18:setup_element:INFO:	Clock phase scan results for group 0, downlink 1
10:47:18:setup_element:INFO:	Eye window for uplink 8 : ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
10:47:18:setup_element:INFO:	Eye window for uplink 9 : ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
10:47:18:setup_element:INFO:	Eye window for uplink 14: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
10:47:18:setup_element:INFO:	Eye window for uplink 15: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
10:47:18:setup_element:INFO:	Setting the clock phase to 31 for group 0, downlink 1
==============================================OOO==============================================
10:47:18:setup_element:INFO:	Scanning data phases
10:47:18:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
10:47:18:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:47:23:setup_element:INFO:	Data phase scan results for group 0, downlink 1
10:47:23:setup_element:INFO:	Eye window for uplink 8 : _____________________________XXXXX______
Data delay found: 11
10:47:23:setup_element:INFO:	Eye window for uplink 9 : X_________________________________XXXXXX
Data delay found: 17
10:47:23:setup_element:INFO:	Eye window for uplink 14: ________________________________XXXXXX__
Data delay found: 14
10:47:23:setup_element:INFO:	Eye window for uplink 15: X_________________________________XXXXX_
Data delay found: 17
10:47:23:setup_element:INFO:	Setting the data phase to 11 for uplink 8
10:47:23:setup_element:INFO:	Setting the data phase to 17 for uplink 9
10:47:23:setup_element:INFO:	Setting the data phase to 14 for uplink 14
10:47:23:setup_element:INFO:	Setting the data phase to 17 for uplink 15
==============================================OOO==============================================
10:47:23:setup_element:INFO:	Beginning SMX ASICs map scan
10:47:23:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
10:47:23:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:47:23:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
10:47:23:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
10:47:23:uplink:INFO:	Setting uplinks mask [8, 9, 14, 15]
10:47:23:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 8
10:47:23:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 9
10:47:24:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 14
10:47:24:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 15
10:47:26:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 1
  Uplinks: [8, 9, 14, 15]
  ASICs Map:
    ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
  Clock Phase Characteristic:
    Optimal Phase: 31
    Window Length: 71
    Eye Windows:
      Uplink  8: ___________________________________________________________________XXXXXXXXX____
      Uplink  9: ___________________________________________________________________XXXXXXXXX____
      Uplink 14: ____________________________________________________________________XXXXXXXX____
      Uplink 15: ____________________________________________________________________XXXXXXXX____
  Data phase characteristics:
    Uplink 8:
      Optimal Phase: 11
      Window Length: 35
      Eye Window: _____________________________XXXXX______
    Uplink 9:
      Optimal Phase: 17
      Window Length: 33
      Eye Window: X_________________________________XXXXXX
    Uplink 14:
      Optimal Phase: 14
      Window Length: 34
      Eye Window: ________________________________XXXXXX__
    Uplink 15:
      Optimal Phase: 17
      Window Length: 33
      Eye Window: X_________________________________XXXXX_

==============================================OOO==============================================
10:47:26:setup_element:INFO:	Performing Elink synchronization
10:47:26:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
10:47:26:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:47:26:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
10:47:26:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
==============================================OOO==============================================
10:47:26:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 1
10:47:26:uplink:INFO:	Enabling uplinks [8, 9, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 1   | [0]  |   1   |  0  |   [8]   |    2    | [(0, 8), (1, 9)]
 7   | [0]  |   1   |  0  |  [14]   |    2    | [(0, 14), (1, 15)]
|_________________________________________________________________________|
10:47:26:febtest:INFO:	Init all SMX (CSA): 30
10:47:30:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:47:30:febtest:INFO:	08-01 | XA-000-09-004-004-008-006-03 |  31.4 | 1171.5
10:47:31:febtest:INFO:	14-07 | XA-000-09-004-004-008-015-03 |  37.7 | 1153.7
10:47:32:febtest:INFO:	Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
10:47:32:febtest:ERROR:	HW addres 1 != 0
10:47:39:ST3_smx:INFO:	chip: 8-1 	 31.389742 C 	 1177.390875 mV
10:47:39:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:47:39:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:47:39:ST3_smx:INFO:		Electrons
10:47:39:ST3_smx:INFO:	# loops 0
10:47:41:ST3_smx:INFO:	# loops 1
10:47:43:ST3_smx:INFO:	# loops 2
10:47:44:ST3_smx:INFO:	Total # of broken channels: 0
10:47:44:ST3_smx:INFO:	List of broken channels: []
10:47:44:ST3_smx:INFO:	Total # of broken channels: 61
10:47:44:ST3_smx:INFO:	List of broken channels: [3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, 97, 99, 101, 103, 105, 107, 109, 111, 113, 115, 117, 119, 121, 123]
10:47:46:ST3_smx:INFO:	chip: 14-7 	 37.726682 C 	 1159.654860 mV
10:47:46:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:47:46:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
10:47:46:ST3_smx:INFO:		Electrons
10:47:46:ST3_smx:INFO:	# loops 0
10:47:48:ST3_smx:INFO:	# loops 1
10:47:49:ST3_smx:INFO:	# loops 2
10:47:51:ST3_smx:INFO:	Total # of broken channels: 0
10:47:51:ST3_smx:INFO:	List of broken channels: []
10:47:51:ST3_smx:INFO:	Total # of broken channels: 0
10:47:51:ST3_smx:INFO:	List of broken channels: []
10:47:51:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:47:51:febtest:INFO:	08-01 | XA-000-09-004-004-008-006-03 |  34.6 | 1201.0
10:47:52:febtest:INFO:	14-07 | XA-000-09-004-004-008-015-03 |  40.9 | 1177.4
############################################################
#                   S U M M A R Y                          #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_11_14-10_47_15
OPERATOR  : Oleksandr S.; Ralf K.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 3088| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['2.450', '0.3486', '1.850', '0.6975', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '0.4835', '1.850', '0.5116', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '0.5007', '1.850', '0.1363', '0.000', '0.0000', '0.000', '0.0000']