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FEB_3088 14.11.24 10:48:07
Info
10:48:07:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:48:07:ST3_Shared:INFO: FEB-Microcable
10:48:07:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:48:07:febtest:INFO: Testing FEB with SN 3088
10:48:09:smx_tester:INFO: Scanning setup
10:48:09:elinks:INFO: Disabling clock on downlink 0
10:48:09:elinks:INFO: Disabling clock on downlink 1
10:48:09:elinks:INFO: Disabling clock on downlink 2
10:48:09:elinks:INFO: Disabling clock on downlink 3
10:48:09:elinks:INFO: Disabling clock on downlink 4
10:48:09:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:48:09:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:48:09:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:48:09:elinks:INFO: Disabling clock on downlink 0
10:48:09:elinks:INFO: Disabling clock on downlink 1
10:48:09:elinks:INFO: Disabling clock on downlink 2
10:48:09:elinks:INFO: Disabling clock on downlink 3
10:48:09:elinks:INFO: Disabling clock on downlink 4
10:48:09:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:48:09:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:48:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
10:48:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
10:48:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
10:48:09:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
10:48:09:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:48:09:elinks:INFO: Disabling clock on downlink 0
10:48:09:elinks:INFO: Disabling clock on downlink 1
10:48:09:elinks:INFO: Disabling clock on downlink 2
10:48:09:elinks:INFO: Disabling clock on downlink 3
10:48:09:elinks:INFO: Disabling clock on downlink 4
10:48:09:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:48:09:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:48:09:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:48:09:elinks:INFO: Disabling clock on downlink 0
10:48:09:elinks:INFO: Disabling clock on downlink 1
10:48:09:elinks:INFO: Disabling clock on downlink 2
10:48:09:elinks:INFO: Disabling clock on downlink 3
10:48:09:elinks:INFO: Disabling clock on downlink 4
10:48:09:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:48:09:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:48:10:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:48:10:elinks:INFO: Disabling clock on downlink 0
10:48:10:elinks:INFO: Disabling clock on downlink 1
10:48:10:elinks:INFO: Disabling clock on downlink 2
10:48:10:elinks:INFO: Disabling clock on downlink 3
10:48:10:elinks:INFO: Disabling clock on downlink 4
10:48:10:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:48:10:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
10:48:10:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
10:48:10:setup_element:INFO: Scanning clock phase
10:48:10:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:48:10:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:48:10:setup_element:INFO: Clock phase scan results for group 0, downlink 1
10:48:10:setup_element:INFO: Eye window for uplink 8 : ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
10:48:10:setup_element:INFO: Eye window for uplink 9 : ___________________________________________________________________XXXXXXXXX____
Clock Delay: 31
10:48:10:setup_element:INFO: Eye window for uplink 14: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
10:48:10:setup_element:INFO: Eye window for uplink 15: ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
10:48:10:setup_element:INFO: Setting the clock phase to 31 for group 0, downlink 1
==============================================OOO==============================================
10:48:10:setup_element:INFO: Scanning data phases
10:48:10:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:48:10:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:48:15:setup_element:INFO: Data phase scan results for group 0, downlink 1
10:48:15:setup_element:INFO: Eye window for uplink 8 : _____________________________XXXXXX_____
Data delay found: 11
10:48:15:setup_element:INFO: Eye window for uplink 9 : __________________________________XXXXXX
Data delay found: 16
10:48:15:setup_element:INFO: Eye window for uplink 14: ________________________________XXXXXX__
Data delay found: 14
10:48:15:setup_element:INFO: Eye window for uplink 15: _________________________________XXXXXXX
Data delay found: 16
10:48:15:setup_element:INFO: Setting the data phase to 11 for uplink 8
10:48:15:setup_element:INFO: Setting the data phase to 16 for uplink 9
10:48:15:setup_element:INFO: Setting the data phase to 14 for uplink 14
10:48:15:setup_element:INFO: Setting the data phase to 16 for uplink 15
==============================================OOO==============================================
10:48:15:setup_element:INFO: Beginning SMX ASICs map scan
10:48:15:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:48:15:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:48:15:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
10:48:15:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
10:48:15:uplink:INFO: Setting uplinks mask [8, 9, 14, 15]
10:48:16:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
10:48:16:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
10:48:17:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
10:48:17:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
10:48:18:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 1
Uplinks: [8, 9, 14, 15]
ASICs Map:
ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
Clock Phase Characteristic:
Optimal Phase: 31
Window Length: 71
Eye Windows:
Uplink 8: ___________________________________________________________________XXXXXXXXX____
Uplink 9: ___________________________________________________________________XXXXXXXXX____
Uplink 14: ____________________________________________________________________XXXXXXX_____
Uplink 15: ____________________________________________________________________XXXXXXX_____
Data phase characteristics:
Uplink 8:
Optimal Phase: 11
Window Length: 34
Eye Window: _____________________________XXXXXX_____
Uplink 9:
Optimal Phase: 16
Window Length: 34
Eye Window: __________________________________XXXXXX
Uplink 14:
Optimal Phase: 14
Window Length: 34
Eye Window: ________________________________XXXXXX__
Uplink 15:
Optimal Phase: 16
Window Length: 33
Eye Window: _________________________________XXXXXXX
==============================================OOO==============================================
10:48:18:setup_element:INFO: Performing Elink synchronization
10:48:18:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:48:18:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
10:48:18:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
10:48:18:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
==============================================OOO==============================================
10:48:18:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
10:48:18:uplink:INFO: Enabling uplinks [8, 9, 14, 15]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
1 | [0] | 1 | 0 | [8] | 2 | [(0, 8), (1, 9)]
7 | [0] | 1 | 0 | [14] | 2 | [(0, 14), (1, 15)]
|_________________________________________________________________________|
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_1_8 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_1__upli_8
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_7_14 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_7_14 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_7__upli_14
10:48:18:febtest:INFO: Init all SMX (CSA): 30
10:48:22:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:48:23:febtest:INFO: 08-01 | XA-000-09-004-004-008-006-03 | 34.6 | 1177.4
10:48:23:febtest:INFO: 14-07 | XA-000-09-004-004-008-015-03 | 37.7 | 1159.7
10:48:24:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
10:48:24:febtest:ERROR: HW addres 1 != 0
10:48:27:ST3_smx:INFO: chip: 8-1 31.389742 C 1177.390875 mV
10:48:27:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:48:27:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:48:27:ST3_smx:INFO: Electrons
10:48:27:ST3_smx:INFO: # loops 0
10:48:29:ST3_smx:INFO: # loops 1
10:48:31:ST3_smx:INFO: # loops 2
10:48:32:ST3_smx:INFO: Total # of broken channels: 0
10:48:32:ST3_smx:INFO: List of broken channels: []
10:48:32:ST3_smx:INFO: Total # of broken channels: 0
10:48:32:ST3_smx:INFO: List of broken channels: []
10:48:34:ST3_smx:INFO: chip: 14-7 37.726682 C 1159.654860 mV
10:48:34:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:48:34:ST3_discr_histo:WARNING: Not enough entries for fit!!!
10:48:34:ST3_smx:INFO: Electrons
10:48:34:ST3_smx:INFO: # loops 0
10:48:36:ST3_smx:INFO: # loops 1
10:48:37:ST3_smx:INFO: # loops 2
10:48:39:ST3_smx:INFO: Total # of broken channels: 0
10:48:39:ST3_smx:INFO: List of broken channels: []
10:48:39:ST3_smx:INFO: Total # of broken channels: 0
10:48:39:ST3_smx:INFO: List of broken channels: []
10:48:39:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:48:40:febtest:INFO: 08-01 | XA-000-09-004-004-008-006-03 | 34.6 | 1201.0
10:48:40:febtest:INFO: 14-07 | XA-000-09-004-004-008-015-03 | 40.9 | 1177.4
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_11_14-10_48_07
OPERATOR : Oleksandr S.; Ralf K.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 3088| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['2.449', '0.4512', '1.850', '0.7016', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '0.4724', '1.850', '0.3994', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '0.5019', '1.850', '0.1363', '0.000', '0.0000', '0.000', '0.0000']