14:37:19:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:37:19:ST3_Shared:INFO:	                         FEB-Sensor                         
14:37:19:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:37:23:ST3_ModuleSelector:DEBUG:	M7UL5T2010402B2
14:37:23:ST3_ModuleSelector:DEBUG:	L7UL501040
14:37:23:ST3_ModuleSelector:DEBUG:	20364
14:37:23:ST3_ModuleSelector:DEBUG:	62x124
14:37:23:ST3_ModuleSelector:DEBUG:	A
14:37:23:ST3_ModuleSelector:DEBUG:	M7UL5T2010402B2
14:37:23:ST3_ModuleSelector:DEBUG:	L7UL501040
14:37:23:ST3_ModuleSelector:DEBUG:	20364
14:37:23:ST3_ModuleSelector:DEBUG:	62x124
14:37:23:ST3_ModuleSelector:DEBUG:	A
14:37:26:ST3_ModuleSelector:INFO:	M7UL5T2010402B2
14:37:26:ST3_ModuleSelector:INFO:	20364
14:37:26:febtest:INFO:	Testing FEB with SN 4062
14:37:27:smx_tester:INFO:	Scanning setup
14:37:27:elinks:INFO:	Disabling clock on downlink 0
14:37:27:elinks:INFO:	Disabling clock on downlink 1
14:37:27:elinks:INFO:	Disabling clock on downlink 2
14:37:27:elinks:INFO:	Disabling clock on downlink 3
14:37:27:elinks:INFO:	Disabling clock on downlink 4
14:37:27:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:37:27:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
14:37:28:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:37:28:elinks:INFO:	Disabling clock on downlink 0
14:37:28:elinks:INFO:	Disabling clock on downlink 1
14:37:28:elinks:INFO:	Disabling clock on downlink 2
14:37:28:elinks:INFO:	Disabling clock on downlink 3
14:37:28:elinks:INFO:	Disabling clock on downlink 4
14:37:28:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:37:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:37:28:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:37:28:elinks:INFO:	Disabling clock on downlink 0
14:37:28:elinks:INFO:	Disabling clock on downlink 1
14:37:28:elinks:INFO:	Disabling clock on downlink 2
14:37:28:elinks:INFO:	Disabling clock on downlink 3
14:37:28:elinks:INFO:	Disabling clock on downlink 4
14:37:28:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:37:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:37:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 16
14:37:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 17
14:37:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 18
14:37:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 19
14:37:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 20
14:37:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 21
14:37:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 22
14:37:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 23
14:37:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
14:37:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
14:37:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
14:37:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
14:37:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
14:37:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
14:37:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
14:37:28:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
14:37:28:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:37:28:elinks:INFO:	Disabling clock on downlink 0
14:37:28:elinks:INFO:	Disabling clock on downlink 1
14:37:28:elinks:INFO:	Disabling clock on downlink 2
14:37:28:elinks:INFO:	Disabling clock on downlink 3
14:37:28:elinks:INFO:	Disabling clock on downlink 4
14:37:28:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:37:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
14:37:28:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:37:28:elinks:INFO:	Disabling clock on downlink 0
14:37:28:elinks:INFO:	Disabling clock on downlink 1
14:37:28:elinks:INFO:	Disabling clock on downlink 2
14:37:28:elinks:INFO:	Disabling clock on downlink 3
14:37:28:elinks:INFO:	Disabling clock on downlink 4
14:37:28:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:37:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
14:37:28:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
14:37:28:setup_element:INFO:	Scanning clock phase
14:37:28:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:37:28:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:37:28:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
14:37:28:setup_element:INFO:	Eye window for uplink 16: ________________________________________________________________XXXXXXXXX_______
Clock Delay: 28
14:37:28:setup_element:INFO:	Eye window for uplink 17: ________________________________________________________________XXXXXXXXX_______
Clock Delay: 28
14:37:28:setup_element:INFO:	Eye window for uplink 18: ______________________________________________________________XXXXXXXXXX________
Clock Delay: 26
14:37:28:setup_element:INFO:	Eye window for uplink 19: ______________________________________________________________XXXXXXXXXX________
Clock Delay: 26
14:37:28:setup_element:INFO:	Eye window for uplink 20: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
14:37:28:setup_element:INFO:	Eye window for uplink 21: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
14:37:28:setup_element:INFO:	Eye window for uplink 22: ________________________________________________________________XXXXXXXXX_______
Clock Delay: 28
14:37:28:setup_element:INFO:	Eye window for uplink 23: ________________________________________________________________XXXXXXXXX_______
Clock Delay: 28
14:37:28:setup_element:INFO:	Eye window for uplink 24: ________________________________________________________________XXXXXXXXX_______
Clock Delay: 28
14:37:28:setup_element:INFO:	Eye window for uplink 25: ________________________________________________________________XXXXXXXXX_______
Clock Delay: 28
14:37:28:setup_element:INFO:	Eye window for uplink 26: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
14:37:28:setup_element:INFO:	Eye window for uplink 27: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
14:37:28:setup_element:INFO:	Eye window for uplink 28: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
14:37:28:setup_element:INFO:	Eye window for uplink 29: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
14:37:29:setup_element:INFO:	Eye window for uplink 30: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
14:37:29:setup_element:INFO:	Eye window for uplink 31: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
14:37:29:setup_element:INFO:	Setting the clock phase to 28 for group 0, downlink 2
==============================================OOO==============================================
14:37:29:setup_element:INFO:	Scanning data phases
14:37:29:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:37:29:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:37:34:setup_element:INFO:	Data phase scan results for group 0, downlink 2
14:37:34:setup_element:INFO:	Eye window for uplink 16: XX______________________________XXXXXXXX
Data delay found: 16
14:37:34:setup_element:INFO:	Eye window for uplink 17: _______________________________XXXXXXXX_
Data delay found: 14
14:37:34:setup_element:INFO:	Eye window for uplink 18: XX_______________________________XXXXXXX
Data delay found: 17
14:37:34:setup_element:INFO:	Eye window for uplink 19: ________________________________XXXXXX__
Data delay found: 14
14:37:34:setup_element:INFO:	Eye window for uplink 20: XX_______________________________XXXXXXX
Data delay found: 17
14:37:34:setup_element:INFO:	Eye window for uplink 21: XX______________________________XXXXXXXX
Data delay found: 16
14:37:34:setup_element:INFO:	Eye window for uplink 22: XXXXX________________________________XXX
Data delay found: 20
14:37:34:setup_element:INFO:	Eye window for uplink 23: XXXXXXX___________________________XXXXXX
Data delay found: 20
14:37:34:setup_element:INFO:	Eye window for uplink 24: ___X_XXXXXXXX___________________________
Data delay found: 27
14:37:34:setup_element:INFO:	Eye window for uplink 25: ______XXXXXXXXX_________________________
Data delay found: 30
14:37:34:setup_element:INFO:	Eye window for uplink 26: _______XXXXXXXX_________________________
Data delay found: 30
14:37:34:setup_element:INFO:	Eye window for uplink 27: ___________XXXXXXX______________________
Data delay found: 34
14:37:34:setup_element:INFO:	Eye window for uplink 28: ___________XXXXXXXX_____________________
Data delay found: 34
14:37:34:setup_element:INFO:	Eye window for uplink 29: ______________XXXXXXXX__________________
Data delay found: 37
14:37:34:setup_element:INFO:	Eye window for uplink 30: ________________XXXXXXXXX_______________
Data delay found: 0
14:37:34:setup_element:INFO:	Eye window for uplink 31: _______________XXXXXXXXXXX______________
Data delay found: 0
14:37:34:setup_element:INFO:	Setting the data phase to 16 for uplink 16
14:37:34:setup_element:INFO:	Setting the data phase to 14 for uplink 17
14:37:34:setup_element:INFO:	Setting the data phase to 17 for uplink 18
14:37:34:setup_element:INFO:	Setting the data phase to 14 for uplink 19
14:37:34:setup_element:INFO:	Setting the data phase to 17 for uplink 20
14:37:34:setup_element:INFO:	Setting the data phase to 16 for uplink 21
14:37:34:setup_element:INFO:	Setting the data phase to 20 for uplink 22
14:37:34:setup_element:INFO:	Setting the data phase to 20 for uplink 23
14:37:34:setup_element:INFO:	Setting the data phase to 27 for uplink 24
14:37:34:setup_element:INFO:	Setting the data phase to 30 for uplink 25
14:37:34:setup_element:INFO:	Setting the data phase to 30 for uplink 26
14:37:34:setup_element:INFO:	Setting the data phase to 34 for uplink 27
14:37:34:setup_element:INFO:	Setting the data phase to 34 for uplink 28
14:37:34:setup_element:INFO:	Setting the data phase to 37 for uplink 29
14:37:34:setup_element:INFO:	Setting the data phase to 0 for uplink 30
14:37:34:setup_element:INFO:	Setting the data phase to 0 for uplink 31
==============================================OOO==============================================
14:37:34:setup_element:INFO:	Beginning SMX ASICs map scan
14:37:34:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:37:34:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:37:34:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
14:37:34:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
14:37:34:uplink:INFO:	Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
14:37:34:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 23
14:37:34:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 22
14:37:34:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
14:37:34:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
14:37:34:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 21
14:37:34:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 20
14:37:34:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
14:37:34:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
14:37:35:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 19
14:37:35:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 18
14:37:35:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
14:37:35:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
14:37:35:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 17
14:37:35:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 16
14:37:35:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
14:37:35:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
14:37:36:ST3_emu:INFO:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 28
    Window Length: 66
    Eye Windows:
      Uplink 16: ________________________________________________________________XXXXXXXXX_______
      Uplink 17: ________________________________________________________________XXXXXXXXX_______
      Uplink 18: ______________________________________________________________XXXXXXXXXX________
      Uplink 19: ______________________________________________________________XXXXXXXXXX________
      Uplink 20: _________________________________________________________________XXXXXXXXX______
      Uplink 21: _________________________________________________________________XXXXXXXXX______
      Uplink 22: ________________________________________________________________XXXXXXXXX_______
      Uplink 23: ________________________________________________________________XXXXXXXXX_______
      Uplink 24: ________________________________________________________________XXXXXXXXX_______
      Uplink 25: ________________________________________________________________XXXXXXXXX_______
      Uplink 26: _________________________________________________________________XXXXXXXXX______
      Uplink 27: _________________________________________________________________XXXXXXXXX______
      Uplink 28: _________________________________________________________________XXXXXXXXX______
      Uplink 29: _________________________________________________________________XXXXXXXXX______
      Uplink 30: ____________________________________________________________________XXXXXXXX____
      Uplink 31: ____________________________________________________________________XXXXXXXX____
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 16
      Window Length: 30
      Eye Window: XX______________________________XXXXXXXX
    Uplink 17:
      Optimal Phase: 14
      Window Length: 32
      Eye Window: _______________________________XXXXXXXX_
    Uplink 18:
      Optimal Phase: 17
      Window Length: 31
      Eye Window: XX_______________________________XXXXXXX
    Uplink 19:
      Optimal Phase: 14
      Window Length: 34
      Eye Window: ________________________________XXXXXX__
    Uplink 20:
      Optimal Phase: 17
      Window Length: 31
      Eye Window: XX_______________________________XXXXXXX
    Uplink 21:
      Optimal Phase: 16
      Window Length: 30
      Eye Window: XX______________________________XXXXXXXX
    Uplink 22:
      Optimal Phase: 20
      Window Length: 32
      Eye Window: XXXXX________________________________XXX
    Uplink 23:
      Optimal Phase: 20
      Window Length: 27
      Eye Window: XXXXXXX___________________________XXXXXX
    Uplink 24:
      Optimal Phase: 27
      Window Length: 30
      Eye Window: ___X_XXXXXXXX___________________________
    Uplink 25:
      Optimal Phase: 30
      Window Length: 31
      Eye Window: ______XXXXXXXXX_________________________
    Uplink 26:
      Optimal Phase: 30
      Window Length: 32
      Eye Window: _______XXXXXXXX_________________________
    Uplink 27:
      Optimal Phase: 34
      Window Length: 33
      Eye Window: ___________XXXXXXX______________________
    Uplink 28:
      Optimal Phase: 34
      Window Length: 32
      Eye Window: ___________XXXXXXXX_____________________
    Uplink 29:
      Optimal Phase: 37
      Window Length: 32
      Eye Window: ______________XXXXXXXX__________________
    Uplink 30:
      Optimal Phase: 0
      Window Length: 31
      Eye Window: ________________XXXXXXXXX_______________
    Uplink 31:
      Optimal Phase: 0
      Window Length: 29
      Eye Window: _______________XXXXXXXXXXX______________

==============================================OOO==============================================
14:37:36:setup_element:INFO:	Performing Elink synchronization
14:37:36:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:37:36:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:37:36:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
14:37:36:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
14:37:36:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
14:37:36:uplink:INFO:	Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 0   | [0]  |   2   |  0  |  [23]   |    2    | [(0, 23), (1, 22)]
 1   | [0]  |   2   |  0  |  [30]   |    2    | [(0, 30), (1, 31)]
 2   | [0]  |   2   |  0  |  [21]   |    2    | [(0, 21), (1, 20)]
 3   | [0]  |   2   |  0  |  [28]   |    2    | [(0, 28), (1, 29)]
 4   | [0]  |   2   |  0  |  [19]   |    2    | [(0, 19), (1, 18)]
 5   | [0]  |   2   |  0  |  [26]   |    2    | [(0, 26), (1, 27)]
 6   | [0]  |   2   |  0  |  [17]   |    2    | [(0, 17), (1, 16)]
 7   | [0]  |   2   |  0  |  [24]   |    2    | [(0, 24), (1, 25)]
|_________________________________________________________________________|
14:37:37:febtest:INFO:	Init all SMX (CSA): 30
14:37:53:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:37:53:febtest:INFO:	23-00 | XA-000-08-003-000-004-208-10 |  28.2 | 1171.5
14:37:53:febtest:INFO:	30-01 | XA-000-08-003-000-004-211-10 |  21.9 | 1201.0
14:37:53:febtest:INFO:	21-02 | XA-000-08-003-000-004-204-13 |  37.7 | 1135.9
14:37:54:febtest:INFO:	28-03 | XA-000-08-003-000-004-210-10 |  31.4 | 1159.7
14:37:54:febtest:INFO:	19-04 | XA-000-08-003-000-004-203-13 |  18.7 | 1206.9
14:37:54:febtest:INFO:	26-05 | XA-000-08-003-000-004-209-10 |  21.9 | 1189.2
14:37:54:febtest:INFO:	17-06 | XA-000-08-003-000-004-201-13 |  37.7 | 1153.7
14:37:54:febtest:INFO:	24-07 | XA-000-08-003-000-004-206-13 |  21.9 | 1189.2
14:37:55:febtest:INFO:	Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
14:37:58:ST3_smx:INFO:	chip: 23-0 	 31.389742 C 	 1183.292940 mV
14:37:58:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:37:58:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:37:58:ST3_smx:INFO:		Electrons
14:37:58:ST3_smx:INFO:	# loops 0
14:37:59:ST3_smx:INFO:	# loops 1
14:38:01:ST3_smx:INFO:	# loops 2
14:38:02:ST3_smx:INFO:	# loops 3
14:38:04:ST3_smx:INFO:	# loops 4
14:38:06:ST3_smx:INFO:	Total # of broken channels: 0
14:38:06:ST3_smx:INFO:	List of broken channels: []
14:38:06:ST3_smx:INFO:	Total # of broken channels: 1
14:38:06:ST3_smx:INFO:	List of broken channels: [118]
14:38:08:ST3_smx:INFO:	chip: 30-1 	 21.902970 C 	 1212.728715 mV
14:38:08:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:38:08:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:38:08:ST3_smx:INFO:		Electrons
14:38:08:ST3_smx:INFO:	# loops 0
14:38:09:ST3_smx:INFO:	# loops 1
14:38:11:ST3_smx:INFO:	# loops 2
14:38:12:ST3_smx:INFO:	# loops 3
14:38:14:ST3_smx:INFO:	# loops 4
14:38:16:ST3_smx:INFO:	Total # of broken channels: 0
14:38:16:ST3_smx:INFO:	List of broken channels: []
14:38:16:ST3_smx:INFO:	Total # of broken channels: 0
14:38:16:ST3_smx:INFO:	List of broken channels: []
14:38:17:ST3_smx:INFO:	chip: 21-2 	 37.726682 C 	 1141.874115 mV
14:38:17:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:38:17:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:38:17:ST3_smx:INFO:		Electrons
14:38:17:ST3_smx:INFO:	# loops 0
14:38:19:ST3_smx:INFO:	# loops 1
14:38:21:ST3_smx:INFO:	# loops 2
14:38:23:ST3_smx:INFO:	# loops 3
14:38:24:ST3_smx:INFO:	# loops 4
14:38:26:ST3_smx:INFO:	Total # of broken channels: 0
14:38:26:ST3_smx:INFO:	List of broken channels: []
14:38:26:ST3_smx:INFO:	Total # of broken channels: 1
14:38:26:ST3_smx:INFO:	List of broken channels: [23]
14:38:28:ST3_smx:INFO:	chip: 28-3 	 34.556970 C 	 1165.571835 mV
14:38:28:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:38:28:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:38:28:ST3_smx:INFO:		Electrons
14:38:28:ST3_smx:INFO:	# loops 0
14:38:29:ST3_smx:INFO:	# loops 1
14:38:31:ST3_smx:INFO:	# loops 2
14:38:33:ST3_smx:INFO:	# loops 3
14:38:34:ST3_smx:INFO:	# loops 4
14:38:36:ST3_smx:INFO:	Total # of broken channels: 0
14:38:36:ST3_smx:INFO:	List of broken channels: []
14:38:36:ST3_smx:INFO:	Total # of broken channels: 1
14:38:36:ST3_smx:INFO:	List of broken channels: [41]
14:38:38:ST3_smx:INFO:	chip: 19-4 	 21.902970 C 	 1218.600960 mV
14:38:38:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:38:38:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:38:38:ST3_smx:INFO:		Electrons
14:38:38:ST3_smx:INFO:	# loops 0
14:38:39:ST3_smx:INFO:	# loops 1
14:38:41:ST3_smx:INFO:	# loops 2
14:38:43:ST3_smx:INFO:	# loops 3
14:38:44:ST3_smx:INFO:	# loops 4
14:38:46:ST3_smx:INFO:	Total # of broken channels: 0
14:38:46:ST3_smx:INFO:	List of broken channels: []
14:38:46:ST3_smx:INFO:	Total # of broken channels: 0
14:38:46:ST3_smx:INFO:	List of broken channels: []
14:38:47:ST3_smx:INFO:	chip: 26-5 	 21.902970 C 	 1200.969315 mV
14:38:47:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:38:47:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:38:47:ST3_smx:INFO:		Electrons
14:38:48:ST3_smx:INFO:	# loops 0
14:38:49:ST3_smx:INFO:	# loops 1
14:38:51:ST3_smx:INFO:	# loops 2
14:38:53:ST3_smx:INFO:	# loops 3
14:38:54:ST3_smx:INFO:	# loops 4
14:38:56:ST3_smx:INFO:	Total # of broken channels: 0
14:38:56:ST3_smx:INFO:	List of broken channels: []
14:38:56:ST3_smx:INFO:	Total # of broken channels: 0
14:38:56:ST3_smx:INFO:	List of broken channels: []
14:38:58:ST3_smx:INFO:	chip: 17-6 	 37.726682 C 	 1159.654860 mV
14:38:58:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:38:58:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:38:58:ST3_smx:INFO:		Electrons
14:38:58:ST3_smx:INFO:	# loops 0
14:38:59:ST3_smx:INFO:	# loops 1
14:39:01:ST3_smx:INFO:	# loops 2
14:39:03:ST3_smx:INFO:	# loops 3
14:39:05:ST3_smx:INFO:	# loops 4
14:39:06:ST3_smx:INFO:	Total # of broken channels: 0
14:39:06:ST3_smx:INFO:	List of broken channels: []
14:39:06:ST3_smx:INFO:	Total # of broken channels: 0
14:39:06:ST3_smx:INFO:	List of broken channels: []
14:39:08:ST3_smx:INFO:	chip: 24-7 	 25.062742 C 	 1200.969315 mV
14:39:08:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:39:08:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:39:08:ST3_smx:INFO:		Electrons
14:39:08:ST3_smx:INFO:	# loops 0
14:39:10:ST3_smx:INFO:	# loops 1
14:39:11:ST3_smx:INFO:	# loops 2
14:39:13:ST3_smx:INFO:	# loops 3
14:39:15:ST3_smx:INFO:	# loops 4
14:39:16:ST3_smx:INFO:	Total # of broken channels: 0
14:39:16:ST3_smx:INFO:	List of broken channels: []
14:39:16:ST3_smx:INFO:	Total # of broken channels: 0
14:39:16:ST3_smx:INFO:	List of broken channels: []
14:39:17:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:39:17:febtest:INFO:	23-00 | XA-000-08-003-000-004-208-10 |  31.4 | 1201.0
14:39:17:febtest:INFO:	30-01 | XA-000-08-003-000-004-211-10 |  21.9 | 1242.0
14:39:17:febtest:INFO:	21-02 | XA-000-08-003-000-004-204-13 |  40.9 | 1159.7
14:39:18:febtest:INFO:	28-03 | XA-000-08-003-000-004-210-10 |  34.6 | 1189.2
14:39:18:febtest:INFO:	19-04 | XA-000-08-003-000-004-203-13 |  21.9 | 1236.2
14:39:18:febtest:INFO:	26-05 | XA-000-08-003-000-004-209-10 |  25.1 | 1218.6
14:39:18:febtest:INFO:	17-06 | XA-000-08-003-000-004-201-13 |  37.7 | 1177.4
14:39:19:febtest:INFO:	24-07 | XA-000-08-003-000-004-206-13 |  25.1 | 1218.6
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 25_01_22-14_37_19
OPERATOR  : Oleksandr S.; 
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 4062| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
SENSOR_NAME: 20364 | SIZE: 62x124 | GRADE: A
MODULE_NAME: M7UL5T2010402B2
LADDER_NAME: L7UL501040
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.4320', '1.848', '2.3080']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0530', '1.850', '2.4910']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9550', '1.850', '0.5199']