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FEB_4062 29.01.25 14:50:37
Info
14:50:37:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:50:37:ST3_Shared:INFO: FEB-Sensor
14:50:37:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:50:42:ST3_ModuleSelector:DEBUG: M7UL5T2010402B2
14:50:42:ST3_ModuleSelector:DEBUG: L7UL501040
14:50:42:ST3_ModuleSelector:DEBUG: 20364
14:50:42:ST3_ModuleSelector:DEBUG: 62x124
14:50:42:ST3_ModuleSelector:DEBUG: A
14:50:42:ST3_ModuleSelector:DEBUG: M7UL5T2010402B2
14:50:42:ST3_ModuleSelector:DEBUG: L7UL501040
14:50:42:ST3_ModuleSelector:DEBUG: 20364
14:50:42:ST3_ModuleSelector:DEBUG: 62x124
14:50:42:ST3_ModuleSelector:DEBUG: A
14:50:49:ST3_ModuleSelector:INFO: M7UL5T2010402B2
14:50:49:ST3_ModuleSelector:INFO: 20364
14:50:49:febtest:INFO: Testing FEB with SN 4062
14:50:51:smx_tester:INFO: Scanning setup
14:50:51:elinks:INFO: Disabling clock on downlink 0
14:50:51:elinks:INFO: Disabling clock on downlink 1
14:50:51:elinks:INFO: Disabling clock on downlink 2
14:50:51:elinks:INFO: Disabling clock on downlink 3
14:50:51:elinks:INFO: Disabling clock on downlink 4
14:50:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:50:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:50:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:50:51:elinks:INFO: Disabling clock on downlink 0
14:50:51:elinks:INFO: Disabling clock on downlink 1
14:50:51:elinks:INFO: Disabling clock on downlink 2
14:50:51:elinks:INFO: Disabling clock on downlink 3
14:50:51:elinks:INFO: Disabling clock on downlink 4
14:50:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:50:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:50:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:50:51:elinks:INFO: Disabling clock on downlink 0
14:50:51:elinks:INFO: Disabling clock on downlink 1
14:50:51:elinks:INFO: Disabling clock on downlink 2
14:50:51:elinks:INFO: Disabling clock on downlink 3
14:50:51:elinks:INFO: Disabling clock on downlink 4
14:50:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:50:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:50:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
14:50:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
14:50:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
14:50:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
14:50:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
14:50:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
14:50:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
14:50:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
14:50:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
14:50:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
14:50:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
14:50:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
14:50:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
14:50:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
14:50:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
14:50:51:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
14:50:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:50:51:elinks:INFO: Disabling clock on downlink 0
14:50:51:elinks:INFO: Disabling clock on downlink 1
14:50:51:elinks:INFO: Disabling clock on downlink 2
14:50:51:elinks:INFO: Disabling clock on downlink 3
14:50:51:elinks:INFO: Disabling clock on downlink 4
14:50:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:50:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:50:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:50:51:elinks:INFO: Disabling clock on downlink 0
14:50:51:elinks:INFO: Disabling clock on downlink 1
14:50:51:elinks:INFO: Disabling clock on downlink 2
14:50:51:elinks:INFO: Disabling clock on downlink 3
14:50:51:elinks:INFO: Disabling clock on downlink 4
14:50:51:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:50:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:50:51:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
14:50:51:setup_element:INFO: Scanning clock phase
14:50:51:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:50:51:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:50:52:setup_element:INFO: Clock phase scan results for group 0, downlink 2
14:50:52:setup_element:INFO: Eye window for uplink 16: ________________________________________________________________XXXXXXXXX_______
Clock Delay: 28
14:50:52:setup_element:INFO: Eye window for uplink 17: ________________________________________________________________XXXXXXXXX_______
Clock Delay: 28
14:50:52:setup_element:INFO: Eye window for uplink 18: ______________________________________________________________XXXXXXXXX_________
Clock Delay: 26
14:50:52:setup_element:INFO: Eye window for uplink 19: ______________________________________________________________XXXXXXXXX_________
Clock Delay: 26
14:50:52:setup_element:INFO: Eye window for uplink 20: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
14:50:52:setup_element:INFO: Eye window for uplink 21: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
14:50:52:setup_element:INFO: Eye window for uplink 22: ________________________________________________________________XXXXXXXXX_______
Clock Delay: 28
14:50:52:setup_element:INFO: Eye window for uplink 23: ________________________________________________________________XXXXXXXXX_______
Clock Delay: 28
14:50:52:setup_element:INFO: Eye window for uplink 24: _________________________________________________________________XXXXXXXX_______
Clock Delay: 28
14:50:52:setup_element:INFO: Eye window for uplink 25: _________________________________________________________________XXXXXXXX_______
Clock Delay: 28
14:50:52:setup_element:INFO: Eye window for uplink 26: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
14:50:52:setup_element:INFO: Eye window for uplink 27: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
14:50:52:setup_element:INFO: Eye window for uplink 28: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
14:50:52:setup_element:INFO: Eye window for uplink 29: _________________________________________________________________XXXXXXXXX______
Clock Delay: 29
14:50:52:setup_element:INFO: Eye window for uplink 30: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
14:50:52:setup_element:INFO: Eye window for uplink 31: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
14:50:52:setup_element:INFO: Setting the clock phase to 28 for group 0, downlink 2
==============================================OOO==============================================
14:50:52:setup_element:INFO: Scanning data phases
14:50:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:50:52:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:50:57:setup_element:INFO: Data phase scan results for group 0, downlink 2
14:50:57:setup_element:INFO: Eye window for uplink 16: XX_______________________________XXXXXXX
Data delay found: 17
14:50:57:setup_element:INFO: Eye window for uplink 17: ________________________________XXXXXXXX
Data delay found: 15
14:50:57:setup_element:INFO: Eye window for uplink 18: XXX______________________________XXXXXXX
Data delay found: 17
14:50:57:setup_element:INFO: Eye window for uplink 19: ______________________________XXXXXXXX__
Data delay found: 13
14:50:57:setup_element:INFO: Eye window for uplink 20: XX_______________________________XXXXXXX
Data delay found: 17
14:50:57:setup_element:INFO: Eye window for uplink 21: X_______________________________XXXXXXXX
Data delay found: 16
14:50:57:setup_element:INFO: Eye window for uplink 22: XXX__________________________________XXX
Data delay found: 19
14:50:57:setup_element:INFO: Eye window for uplink 23: XXXXXX____________________________XXXXXX
Data delay found: 19
14:50:57:setup_element:INFO: Eye window for uplink 24: ___XXXXXXXXXX___________________________
Data delay found: 27
14:50:57:setup_element:INFO: Eye window for uplink 25: ______XXXXXXXX__________________________
Data delay found: 29
14:50:57:setup_element:INFO: Eye window for uplink 26: _______XXXXXXX__________________________
Data delay found: 30
14:50:57:setup_element:INFO: Eye window for uplink 27: ___________XXXXXXXX_____________________
Data delay found: 34
14:50:57:setup_element:INFO: Eye window for uplink 28: ___________XXXXXXXX_____________________
Data delay found: 34
14:50:57:setup_element:INFO: Eye window for uplink 29: _____________XXXXXXXXX__________________
Data delay found: 37
14:50:57:setup_element:INFO: Eye window for uplink 30: ______________XXXXXXXXXXXX______________
Data delay found: 39
14:50:57:setup_element:INFO: Eye window for uplink 31: ______________X_XXXXXXXXXX______________
Data delay found: 39
14:50:57:setup_element:INFO: Setting the data phase to 17 for uplink 16
14:50:57:setup_element:INFO: Setting the data phase to 15 for uplink 17
14:50:57:setup_element:INFO: Setting the data phase to 17 for uplink 18
14:50:57:setup_element:INFO: Setting the data phase to 13 for uplink 19
14:50:57:setup_element:INFO: Setting the data phase to 17 for uplink 20
14:50:57:setup_element:INFO: Setting the data phase to 16 for uplink 21
14:50:57:setup_element:INFO: Setting the data phase to 19 for uplink 22
14:50:57:setup_element:INFO: Setting the data phase to 19 for uplink 23
14:50:57:setup_element:INFO: Setting the data phase to 27 for uplink 24
14:50:57:setup_element:INFO: Setting the data phase to 29 for uplink 25
14:50:57:setup_element:INFO: Setting the data phase to 30 for uplink 26
14:50:57:setup_element:INFO: Setting the data phase to 34 for uplink 27
14:50:57:setup_element:INFO: Setting the data phase to 34 for uplink 28
14:50:57:setup_element:INFO: Setting the data phase to 37 for uplink 29
14:50:57:setup_element:INFO: Setting the data phase to 39 for uplink 30
14:50:57:setup_element:INFO: Setting the data phase to 39 for uplink 31
==============================================OOO==============================================
14:50:57:setup_element:INFO: Beginning SMX ASICs map scan
14:50:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:50:57:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:50:57:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
14:50:57:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
14:50:57:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
14:50:57:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
14:50:57:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
14:50:57:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
14:50:57:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
14:50:57:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
14:50:57:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
14:50:58:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
14:50:58:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
14:50:58:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
14:50:58:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
14:50:58:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
14:50:58:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
14:50:58:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
14:50:58:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
14:50:58:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
14:50:58:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
14:51:00:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 28
Window Length: 66
Eye Windows:
Uplink 16: ________________________________________________________________XXXXXXXXX_______
Uplink 17: ________________________________________________________________XXXXXXXXX_______
Uplink 18: ______________________________________________________________XXXXXXXXX_________
Uplink 19: ______________________________________________________________XXXXXXXXX_________
Uplink 20: _________________________________________________________________XXXXXXXXX______
Uplink 21: _________________________________________________________________XXXXXXXXX______
Uplink 22: ________________________________________________________________XXXXXXXXX_______
Uplink 23: ________________________________________________________________XXXXXXXXX_______
Uplink 24: _________________________________________________________________XXXXXXXX_______
Uplink 25: _________________________________________________________________XXXXXXXX_______
Uplink 26: _________________________________________________________________XXXXXXXXX______
Uplink 27: _________________________________________________________________XXXXXXXXX______
Uplink 28: _________________________________________________________________XXXXXXXXX______
Uplink 29: _________________________________________________________________XXXXXXXXX______
Uplink 30: ____________________________________________________________________XXXXXXXX____
Uplink 31: ____________________________________________________________________XXXXXXXX____
Data phase characteristics:
Uplink 16:
Optimal Phase: 17
Window Length: 31
Eye Window: XX_______________________________XXXXXXX
Uplink 17:
Optimal Phase: 15
Window Length: 32
Eye Window: ________________________________XXXXXXXX
Uplink 18:
Optimal Phase: 17
Window Length: 30
Eye Window: XXX______________________________XXXXXXX
Uplink 19:
Optimal Phase: 13
Window Length: 32
Eye Window: ______________________________XXXXXXXX__
Uplink 20:
Optimal Phase: 17
Window Length: 31
Eye Window: XX_______________________________XXXXXXX
Uplink 21:
Optimal Phase: 16
Window Length: 31
Eye Window: X_______________________________XXXXXXXX
Uplink 22:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 23:
Optimal Phase: 19
Window Length: 28
Eye Window: XXXXXX____________________________XXXXXX
Uplink 24:
Optimal Phase: 27
Window Length: 30
Eye Window: ___XXXXXXXXXX___________________________
Uplink 25:
Optimal Phase: 29
Window Length: 32
Eye Window: ______XXXXXXXX__________________________
Uplink 26:
Optimal Phase: 30
Window Length: 33
Eye Window: _______XXXXXXX__________________________
Uplink 27:
Optimal Phase: 34
Window Length: 32
Eye Window: ___________XXXXXXXX_____________________
Uplink 28:
Optimal Phase: 34
Window Length: 32
Eye Window: ___________XXXXXXXX_____________________
Uplink 29:
Optimal Phase: 37
Window Length: 31
Eye Window: _____________XXXXXXXXX__________________
Uplink 30:
Optimal Phase: 39
Window Length: 28
Eye Window: ______________XXXXXXXXXXXX______________
Uplink 31:
Optimal Phase: 39
Window Length: 28
Eye Window: ______________X_XXXXXXXXXX______________
==============================================OOO==============================================
14:51:00:setup_element:INFO: Performing Elink synchronization
14:51:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:51:00:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:51:00:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
14:51:00:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
14:51:00:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
14:51:00:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 2 | 0 | [23] | 2 | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | 2 | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | 2 | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | 2 | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)]
|_________________________________________________________________________|
14:51:00:febtest:INFO: Init all SMX (CSA): 30
14:51:15:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:51:15:febtest:INFO: 23-00 | XA-000-08-003-000-004-208-10 | 31.4 | 1171.5
14:51:15:febtest:INFO: 30-01 | XA-000-08-003-000-004-211-10 | 25.1 | 1201.0
14:51:15:febtest:INFO: 21-02 | XA-000-08-003-000-004-204-13 | 44.1 | 1130.0
14:51:15:febtest:INFO: 28-03 | XA-000-08-003-000-004-210-10 | 37.7 | 1153.7
14:51:16:febtest:INFO: 19-04 | XA-000-08-003-000-004-203-13 | 21.9 | 1206.9
14:51:16:febtest:INFO: 26-05 | XA-000-08-003-000-004-209-10 | 28.2 | 1183.3
14:51:16:febtest:INFO: 17-06 | XA-000-08-003-000-004-201-13 | 37.7 | 1153.7
14:51:16:febtest:INFO: 24-07 | XA-000-08-003-000-004-206-13 | 28.2 | 1189.2
14:51:17:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
14:51:19:ST3_smx:INFO: chip: 23-0 31.389742 C 1183.292940 mV
14:51:19:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:51:19:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:51:19:ST3_smx:INFO: Electrons
14:51:19:ST3_smx:INFO: # loops 0
14:51:21:ST3_smx:INFO: # loops 1
14:51:22:ST3_smx:INFO: # loops 2
14:51:24:ST3_smx:INFO: # loops 3
14:51:26:ST3_smx:INFO: # loops 4
14:51:27:ST3_smx:INFO: Total # of broken channels: 0
14:51:27:ST3_smx:INFO: List of broken channels: []
14:51:27:ST3_smx:INFO: Total # of broken channels: 1
14:51:27:ST3_smx:INFO: List of broken channels: [118]
14:51:29:ST3_smx:INFO: chip: 30-1 25.062742 C 1212.728715 mV
14:51:29:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:51:29:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:51:29:ST3_smx:INFO: Electrons
14:51:29:ST3_smx:INFO: # loops 0
14:51:31:ST3_smx:INFO: # loops 1
14:51:32:ST3_smx:INFO: # loops 2
14:51:34:ST3_smx:INFO: # loops 3
14:51:35:ST3_smx:INFO: # loops 4
14:51:37:ST3_smx:INFO: Total # of broken channels: 0
14:51:37:ST3_smx:INFO: List of broken channels: []
14:51:37:ST3_smx:INFO: Total # of broken channels: 0
14:51:37:ST3_smx:INFO: List of broken channels: []
14:51:39:ST3_smx:INFO: chip: 21-2 44.073563 C 1141.874115 mV
14:51:39:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:51:39:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:51:39:ST3_smx:INFO: Electrons
14:51:39:ST3_smx:INFO: # loops 0
14:51:40:ST3_smx:INFO: # loops 1
14:51:42:ST3_smx:INFO: # loops 2
14:51:43:ST3_smx:INFO: # loops 3
14:51:45:ST3_smx:INFO: # loops 4
14:51:47:ST3_smx:INFO: Total # of broken channels: 0
14:51:47:ST3_smx:INFO: List of broken channels: []
14:51:47:ST3_smx:INFO: Total # of broken channels: 1
14:51:47:ST3_smx:INFO: List of broken channels: [23]
14:51:48:ST3_smx:INFO: chip: 28-3 37.726682 C 1165.571835 mV
14:51:48:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:51:48:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:51:48:ST3_smx:INFO: Electrons
14:51:48:ST3_smx:INFO: # loops 0
14:51:50:ST3_smx:INFO: # loops 1
14:51:52:ST3_smx:INFO: # loops 2
14:51:53:ST3_smx:INFO: # loops 3
14:51:55:ST3_smx:INFO: # loops 4
14:51:56:ST3_smx:INFO: Total # of broken channels: 0
14:51:56:ST3_smx:INFO: List of broken channels: []
14:51:56:ST3_smx:INFO: Total # of broken channels: 1
14:51:56:ST3_smx:INFO: List of broken channels: [41]
14:51:58:ST3_smx:INFO: chip: 19-4 25.062742 C 1218.600960 mV
14:51:58:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:51:58:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:51:58:ST3_smx:INFO: Electrons
14:51:58:ST3_smx:INFO: # loops 0
14:52:00:ST3_smx:INFO: # loops 1
14:52:01:ST3_smx:INFO: # loops 2
14:52:03:ST3_smx:INFO: # loops 3
14:52:04:ST3_smx:INFO: # loops 4
14:52:06:ST3_smx:INFO: Total # of broken channels: 0
14:52:06:ST3_smx:INFO: List of broken channels: []
14:52:06:ST3_smx:INFO: Total # of broken channels: 0
14:52:06:ST3_smx:INFO: List of broken channels: []
14:52:08:ST3_smx:INFO: chip: 26-5 28.225000 C 1200.969315 mV
14:52:08:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:52:08:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:52:08:ST3_smx:INFO: Electrons
14:52:08:ST3_smx:INFO: # loops 0
14:52:09:ST3_smx:INFO: # loops 1
14:52:11:ST3_smx:INFO: # loops 2
14:52:12:ST3_smx:INFO: # loops 3
14:52:14:ST3_smx:INFO: # loops 4
14:52:16:ST3_smx:INFO: Total # of broken channels: 0
14:52:16:ST3_smx:INFO: List of broken channels: []
14:52:16:ST3_smx:INFO: Total # of broken channels: 1
14:52:16:ST3_smx:INFO: List of broken channels: [10]
14:52:17:ST3_smx:INFO: chip: 17-6 40.898880 C 1159.654860 mV
14:52:17:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:52:17:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:52:17:ST3_smx:INFO: Electrons
14:52:17:ST3_smx:INFO: # loops 0
14:52:19:ST3_smx:INFO: # loops 1
14:52:20:ST3_smx:INFO: # loops 2
14:52:22:ST3_smx:INFO: # loops 3
14:52:23:ST3_smx:INFO: # loops 4
14:52:25:ST3_smx:INFO: Total # of broken channels: 0
14:52:25:ST3_smx:INFO: List of broken channels: []
14:52:25:ST3_smx:INFO: Total # of broken channels: 0
14:52:25:ST3_smx:INFO: List of broken channels: []
14:52:27:ST3_smx:INFO: chip: 24-7 28.225000 C 1200.969315 mV
14:52:27:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:52:27:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:52:27:ST3_smx:INFO: Electrons
14:52:27:ST3_smx:INFO: # loops 0
14:52:28:ST3_smx:INFO: # loops 1
14:52:30:ST3_smx:INFO: # loops 2
14:52:32:ST3_smx:INFO: # loops 3
14:52:33:ST3_smx:INFO: # loops 4
14:52:35:ST3_smx:INFO: Total # of broken channels: 0
14:52:35:ST3_smx:INFO: List of broken channels: []
14:52:35:ST3_smx:INFO: Total # of broken channels: 1
14:52:35:ST3_smx:INFO: List of broken channels: [127]
14:52:35:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:52:35:febtest:INFO: 23-00 | XA-000-08-003-000-004-208-10 | 34.6 | 1206.9
14:52:36:febtest:INFO: 30-01 | XA-000-08-003-000-004-211-10 | 25.1 | 1247.9
14:52:36:febtest:INFO: 21-02 | XA-000-08-003-000-004-204-13 | 44.1 | 1159.7
14:52:36:febtest:INFO: 28-03 | XA-000-08-003-000-004-210-10 | 40.9 | 1183.3
14:52:36:febtest:INFO: 19-04 | XA-000-08-003-000-004-203-13 | 25.1 | 1236.2
14:52:36:febtest:INFO: 26-05 | XA-000-08-003-000-004-209-10 | 31.4 | 1218.6
14:52:37:febtest:INFO: 17-06 | XA-000-08-003-000-004-201-13 | 40.9 | 1177.4
14:52:37:febtest:INFO: 24-07 | XA-000-08-003-000-004-206-13 | 28.2 | 1218.6
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 25_01_29-14_50_37
OPERATOR : Carmen S.; Oleksandr S.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 4062| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
AMP_MODE : STS
------------------------------------------------------------
SENSOR_NAME: 20364 | SIZE: 62x124 | GRADE: A
MODULE_NAME: M7UL5T2010402B2
LADDER_NAME: L7UL501040
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.8310', '1.848', '2.3570']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '2.0570', '1.850', '2.4670']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9580', '1.850', '0.5216']