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FEB_4088 15.11.24 13:26:19
Info
13:26:19:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:26:19:ST3_Shared:INFO: FEB-Microcable
13:26:19:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:26:19:febtest:INFO: Testing FEB with SN 4088
13:26:20:smx_tester:INFO: Scanning setup
13:26:20:elinks:INFO: Disabling clock on downlink 0
13:26:20:elinks:INFO: Disabling clock on downlink 1
13:26:20:elinks:INFO: Disabling clock on downlink 2
13:26:20:elinks:INFO: Disabling clock on downlink 3
13:26:20:elinks:INFO: Disabling clock on downlink 4
13:26:20:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:26:20:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
13:26:21:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:26:21:elinks:INFO: Disabling clock on downlink 0
13:26:21:elinks:INFO: Disabling clock on downlink 1
13:26:21:elinks:INFO: Disabling clock on downlink 2
13:26:21:elinks:INFO: Disabling clock on downlink 3
13:26:21:elinks:INFO: Disabling clock on downlink 4
13:26:21:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:26:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
13:26:21:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:26:21:elinks:INFO: Disabling clock on downlink 0
13:26:21:elinks:INFO: Disabling clock on downlink 1
13:26:21:elinks:INFO: Disabling clock on downlink 2
13:26:21:elinks:INFO: Disabling clock on downlink 3
13:26:21:elinks:INFO: Disabling clock on downlink 4
13:26:21:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:26:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:26:21:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
13:26:21:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
13:26:21:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
13:26:21:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
13:26:21:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
13:26:21:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
13:26:21:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
13:26:21:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
13:26:21:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
13:26:21:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
13:26:21:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
13:26:21:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
13:26:21:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
13:26:21:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
13:26:21:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
13:26:21:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
13:26:21:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:26:21:elinks:INFO: Disabling clock on downlink 0
13:26:21:elinks:INFO: Disabling clock on downlink 1
13:26:21:elinks:INFO: Disabling clock on downlink 2
13:26:21:elinks:INFO: Disabling clock on downlink 3
13:26:21:elinks:INFO: Disabling clock on downlink 4
13:26:21:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:26:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
13:26:21:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
13:26:21:elinks:INFO: Disabling clock on downlink 0
13:26:21:elinks:INFO: Disabling clock on downlink 1
13:26:21:elinks:INFO: Disabling clock on downlink 2
13:26:21:elinks:INFO: Disabling clock on downlink 3
13:26:21:elinks:INFO: Disabling clock on downlink 4
13:26:21:setup_element:INFO: Checking SOS, encoding_mode: SOS
13:26:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
13:26:21:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
==============================================OOO==============================================
13:26:21:setup_element:INFO: Scanning clock phase
13:26:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:26:21:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:26:21:setup_element:INFO: Clock phase scan results for group 0, downlink 2
13:26:21:setup_element:INFO: Eye window for uplink 16: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:26:21:setup_element:INFO: Eye window for uplink 17: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:26:21:setup_element:INFO: Eye window for uplink 18: ________________________________________________________________________________
Clock Delay: 40
13:26:21:setup_element:INFO: Eye window for uplink 19: ________________________________________________________________________________
Clock Delay: 40
13:26:21:setup_element:INFO: Eye window for uplink 20: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
13:26:21:setup_element:INFO: Eye window for uplink 21: _____________________________________________________________________XXXXXXXXX__
Clock Delay: 33
13:26:21:setup_element:INFO: Eye window for uplink 22: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:26:21:setup_element:INFO: Eye window for uplink 23: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:26:21:setup_element:INFO: Eye window for uplink 24: ________________________________________________________________________________
Clock Delay: 40
13:26:21:setup_element:INFO: Eye window for uplink 25: ________________________________________________________________________________
Clock Delay: 40
13:26:21:setup_element:INFO: Eye window for uplink 26: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:26:21:setup_element:INFO: Eye window for uplink 27: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:26:21:setup_element:INFO: Eye window for uplink 28: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
13:26:21:setup_element:INFO: Eye window for uplink 29: ____________________________________________________________________XXXXXXXX____
Clock Delay: 31
13:26:21:setup_element:INFO: Eye window for uplink 30: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:26:21:setup_element:INFO: Eye window for uplink 31: _____________________________________________________________________XXXXXXXX___
Clock Delay: 32
13:26:21:setup_element:INFO: Setting the clock phase to 32 for group 0, downlink 2
==============================================OOO==============================================
13:26:21:setup_element:INFO: Scanning data phases
13:26:21:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:26:22:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:26:27:setup_element:INFO: Data phase scan results for group 0, downlink 2
13:26:27:setup_element:INFO: Eye window for uplink 16: XXX__________________________________XXX
Data delay found: 19
13:26:27:setup_element:INFO: Eye window for uplink 17: X__________________________________XXXXX
Data delay found: 17
13:26:27:setup_element:INFO: Eye window for uplink 18: XXXX_________________________________XXX
Data delay found: 20
13:26:27:setup_element:INFO: Eye window for uplink 19: XX_________________________________XXXXX
Data delay found: 18
13:26:27:setup_element:INFO: Eye window for uplink 20: XX_____________________________________X
Data delay found: 20
13:26:27:setup_element:INFO: Eye window for uplink 21: XX___________________________________XXX
Data delay found: 19
13:26:27:setup_element:INFO: Eye window for uplink 22: XXXX_______________________________XXXXX
Data delay found: 19
13:26:27:setup_element:INFO: Eye window for uplink 23: XXXXXX_____________________________XXXXX
Data delay found: 20
13:26:27:setup_element:INFO: Eye window for uplink 24: _________XXXXX__________________________
Data delay found: 31
13:26:27:setup_element:INFO: Eye window for uplink 25: ___________XXXXX________________________
Data delay found: 33
13:26:27:setup_element:INFO: Eye window for uplink 26: ________XXXXXX__________________________
Data delay found: 30
13:26:27:setup_element:INFO: Eye window for uplink 27: ___________XXXXXX_______________________
Data delay found: 33
13:26:27:setup_element:INFO: Eye window for uplink 28: _____________XXXXX______________________
Data delay found: 35
13:26:27:setup_element:INFO: Eye window for uplink 29: ______________XXXXXXX___________________
Data delay found: 37
13:26:27:setup_element:INFO: Eye window for uplink 30: _______________XXXXXX___________________
Data delay found: 37
13:26:27:setup_element:INFO: Eye window for uplink 31: _______________XXXXXX___________________
Data delay found: 37
13:26:27:setup_element:INFO: Setting the data phase to 19 for uplink 16
13:26:27:setup_element:INFO: Setting the data phase to 17 for uplink 17
13:26:27:setup_element:INFO: Setting the data phase to 20 for uplink 18
13:26:27:setup_element:INFO: Setting the data phase to 18 for uplink 19
13:26:27:setup_element:INFO: Setting the data phase to 20 for uplink 20
13:26:27:setup_element:INFO: Setting the data phase to 19 for uplink 21
13:26:27:setup_element:INFO: Setting the data phase to 19 for uplink 22
13:26:27:setup_element:INFO: Setting the data phase to 20 for uplink 23
13:26:27:setup_element:INFO: Setting the data phase to 31 for uplink 24
13:26:27:setup_element:INFO: Setting the data phase to 33 for uplink 25
13:26:27:setup_element:INFO: Setting the data phase to 30 for uplink 26
13:26:27:setup_element:INFO: Setting the data phase to 33 for uplink 27
13:26:27:setup_element:INFO: Setting the data phase to 35 for uplink 28
13:26:27:setup_element:INFO: Setting the data phase to 37 for uplink 29
13:26:27:setup_element:INFO: Setting the data phase to 37 for uplink 30
13:26:27:setup_element:INFO: Setting the data phase to 37 for uplink 31
==============================================OOO==============================================
13:26:27:setup_element:INFO: Beginning SMX ASICs map scan
13:26:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:26:27:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:26:27:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
13:26:27:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
13:26:27:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
13:26:27:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
13:26:27:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
13:26:27:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
13:26:27:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
13:26:27:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
13:26:27:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
13:26:28:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
13:26:28:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
13:26:28:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
13:26:28:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
13:26:28:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
13:26:28:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
13:26:28:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
13:26:28:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
13:26:28:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
13:26:28:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
13:26:30:ST3_emu:INFO:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 32
Window Length: 70
Eye Windows:
Uplink 16: _____________________________________________________________________XXXXXXXX___
Uplink 17: _____________________________________________________________________XXXXXXXX___
Uplink 18: ________________________________________________________________________________
Uplink 19: ________________________________________________________________________________
Uplink 20: _____________________________________________________________________XXXXXXXXX__
Uplink 21: _____________________________________________________________________XXXXXXXXX__
Uplink 22: _____________________________________________________________________XXXXXXXX___
Uplink 23: _____________________________________________________________________XXXXXXXX___
Uplink 24: ________________________________________________________________________________
Uplink 25: ________________________________________________________________________________
Uplink 26: _____________________________________________________________________XXXXXXXX___
Uplink 27: _____________________________________________________________________XXXXXXXX___
Uplink 28: ____________________________________________________________________XXXXXXXX____
Uplink 29: ____________________________________________________________________XXXXXXXX____
Uplink 30: _____________________________________________________________________XXXXXXXX___
Uplink 31: _____________________________________________________________________XXXXXXXX___
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 17:
Optimal Phase: 17
Window Length: 34
Eye Window: X__________________________________XXXXX
Uplink 18:
Optimal Phase: 20
Window Length: 33
Eye Window: XXXX_________________________________XXX
Uplink 19:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 20:
Optimal Phase: 20
Window Length: 37
Eye Window: XX_____________________________________X
Uplink 21:
Optimal Phase: 19
Window Length: 35
Eye Window: XX___________________________________XXX
Uplink 22:
Optimal Phase: 19
Window Length: 31
Eye Window: XXXX_______________________________XXXXX
Uplink 23:
Optimal Phase: 20
Window Length: 29
Eye Window: XXXXXX_____________________________XXXXX
Uplink 24:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 25:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 26:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 27:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 28:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 29:
Optimal Phase: 37
Window Length: 33
Eye Window: ______________XXXXXXX___________________
Uplink 30:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 31:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
==============================================OOO==============================================
13:26:30:setup_element:INFO: Performing Elink synchronization
13:26:30:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
13:26:30:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:26:30:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
13:26:30:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
==============================================OOO==============================================
13:26:30:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
13:26:30:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
==============================================OOO==============================================
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 2 | 0 | [23] | 2 | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | 2 | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | 2 | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | 2 | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | 2 | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | 2 | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | 2 | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | 2 | [(0, 24), (1, 25)]
|_________________________________________________________________________|
13:26:30:febtest:INFO: Init all SMX (CSA): 5
13:26:44:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
13:26:44:febtest:INFO: 23-00 | XA-000-09-004-004-008-002-03 | 40.9 | 1171.5
13:26:44:febtest:INFO: 30-01 | XA-000-09-004-004-007-009-07 | 40.9 | 1177.4
13:26:45:febtest:INFO: 21-02 | XA-000-09-004-004-007-004-07 | 44.1 | 1165.6
13:26:45:febtest:INFO: 28-03 | XA-000-09-004-004-007-006-07 | 44.1 | 1165.6
13:26:45:febtest:INFO: 19-04 | XA-000-09-004-004-007-007-07 | 37.7 | 1177.4
13:26:45:febtest:INFO: 26-05 | XA-000-09-004-004-007-003-07 | 34.6 | 1189.2
13:26:46:febtest:INFO: 17-06 | XA-000-09-004-004-007-011-07 | 44.1 | 1183.3
13:26:46:febtest:INFO: 24-07 | XA-000-09-004-004-008-004-03 | 44.1 | 1165.6
13:26:47:febtest:INFO: Set all CSA to ZERO
FEB type: B FEB_A: 0 FEB_B: 1
13:26:49:ST3_smx:INFO: chip: 23-0 40.898880 C 1177.390875 mV
13:26:49:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:26:49:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:26:49:ST3_smx:INFO: Electrons
13:26:49:ST3_smx:INFO: # loops 0
13:26:51:ST3_smx:INFO: # loops 1
13:26:52:ST3_smx:INFO: # loops 2
13:26:54:ST3_smx:INFO: Total # of broken channels: 0
13:26:54:ST3_smx:INFO: List of broken channels: []
13:26:54:ST3_smx:INFO: Total # of broken channels: 44
13:26:54:ST3_smx:INFO: List of broken channels: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 71, 73, 75, 77, 79, 81, 83, 85, 87, 93]
13:26:55:ST3_smx:INFO: chip: 30-1 40.898880 C 1177.390875 mV
13:26:55:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:26:55:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:26:55:ST3_smx:INFO: Electrons
13:26:55:ST3_smx:INFO: # loops 0
13:26:57:ST3_smx:INFO: # loops 1
13:26:59:ST3_smx:INFO: # loops 2
13:27:00:ST3_smx:INFO: Total # of broken channels: 0
13:27:00:ST3_smx:INFO: List of broken channels: []
13:27:00:ST3_smx:INFO: Total # of broken channels: 40
13:27:00:ST3_smx:INFO: List of broken channels: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 67, 69, 71, 73, 75, 77, 83]
13:27:02:ST3_smx:INFO: chip: 21-2 44.073563 C 1165.571835 mV
13:27:02:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:27:02:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:27:02:ST3_smx:INFO: Electrons
13:27:02:ST3_smx:INFO: # loops 0
13:27:04:ST3_smx:INFO: # loops 1
13:27:05:ST3_smx:INFO: # loops 2
13:27:07:ST3_smx:INFO: Total # of broken channels: 0
13:27:07:ST3_smx:INFO: List of broken channels: []
13:27:07:ST3_smx:INFO: Total # of broken channels: 37
13:27:07:ST3_smx:INFO: List of broken channels: [3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 61, 63, 65, 69, 73, 75, 81, 83]
13:27:08:ST3_smx:INFO: chip: 28-3 44.073563 C 1165.571835 mV
13:27:08:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:27:08:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:27:08:ST3_smx:INFO: Electrons
13:27:08:ST3_smx:INFO: # loops 0
13:27:10:ST3_smx:INFO: # loops 1
13:27:11:ST3_smx:INFO: # loops 2
13:27:13:ST3_smx:INFO: Total # of broken channels: 0
13:27:13:ST3_smx:INFO: List of broken channels: []
13:27:13:ST3_smx:INFO: Total # of broken channels: 48
13:27:13:ST3_smx:INFO: List of broken channels: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 37, 39, 41, 43, 45, 47, 49, 51, 53, 55, 57, 59, 63, 65, 67, 69, 71, 73, 75, 77, 79, 81, 83, 85, 87, 89, 91, 93, 95, 109]
13:27:15:ST3_smx:INFO: chip: 19-4 40.898880 C 1177.390875 mV
13:27:15:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:27:15:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:27:15:ST3_smx:INFO: Electrons
13:27:15:ST3_smx:INFO: # loops 0
13:27:17:ST3_smx:INFO: # loops 1
13:27:18:ST3_smx:INFO: # loops 2
13:27:20:ST3_smx:INFO: Total # of broken channels: 0
13:27:20:ST3_smx:INFO: List of broken channels: []
13:27:20:ST3_smx:INFO: Total # of broken channels: 16
13:27:20:ST3_smx:INFO: List of broken channels: [3, 9, 11, 15, 17, 19, 21, 23, 25, 27, 29, 31, 33, 35, 49, 65]
13:27:21:ST3_smx:INFO: chip: 26-5 37.726682 C 1195.082160 mV
13:27:21:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:27:21:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:27:21:ST3_smx:INFO: Electrons
13:27:21:ST3_smx:INFO: # loops 0
13:27:23:ST3_smx:INFO: # loops 1
13:27:24:ST3_smx:INFO: # loops 2
13:27:26:ST3_smx:INFO: Total # of broken channels: 0
13:27:26:ST3_smx:INFO: List of broken channels: []
13:27:26:ST3_smx:INFO: Total # of broken channels: 8
13:27:26:ST3_smx:INFO: List of broken channels: [3, 5, 7, 17, 19, 29, 33, 89]
13:27:28:ST3_smx:INFO: chip: 17-6 44.073563 C 1183.292940 mV
13:27:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:27:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:27:28:ST3_smx:INFO: Electrons
13:27:28:ST3_smx:INFO: # loops 0
13:27:29:ST3_smx:INFO: # loops 1
13:27:31:ST3_smx:INFO: # loops 2
13:27:32:ST3_smx:INFO: Total # of broken channels: 0
13:27:32:ST3_smx:INFO: List of broken channels: []
13:27:32:ST3_smx:INFO: Total # of broken channels: 10
13:27:32:ST3_smx:INFO: List of broken channels: [13, 15, 19, 21, 23, 27, 29, 31, 33, 63]
13:27:34:ST3_smx:INFO: chip: 24-7 44.073563 C 1171.483840 mV
13:27:34:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:27:34:ST3_discr_histo:WARNING: Not enough entries for fit!!!
13:27:34:ST3_smx:INFO: Electrons
13:27:34:ST3_smx:INFO: # loops 0
13:27:36:ST3_smx:INFO: # loops 1
13:27:37:ST3_smx:INFO: # loops 2
13:27:39:ST3_smx:INFO: Total # of broken channels: 0
13:27:39:ST3_smx:INFO: List of broken channels: []
13:27:39:ST3_smx:INFO: Total # of broken channels: 10
13:27:39:ST3_smx:INFO: List of broken channels: [5, 7, 9, 11, 13, 15, 17, 19, 27, 29]
13:27:39:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
13:27:39:febtest:INFO: 23-00 | XA-000-09-004-004-008-002-03 | 40.9 | 1183.3
13:27:40:febtest:INFO: 30-01 | XA-000-09-004-004-007-009-07 | 40.9 | 1183.3
13:27:40:febtest:INFO: 21-02 | XA-000-09-004-004-007-004-07 | 44.1 | 1171.5
13:27:40:febtest:INFO: 28-03 | XA-000-09-004-004-007-006-07 | 44.1 | 1171.5
13:27:40:febtest:INFO: 19-04 | XA-000-09-004-004-007-007-07 | 40.9 | 1183.3
13:27:40:febtest:INFO: 26-05 | XA-000-09-004-004-007-003-07 | 37.7 | 1201.0
13:27:41:febtest:INFO: 17-06 | XA-000-09-004-004-007-011-07 | 44.1 | 1189.2
13:27:41:febtest:INFO: 24-07 | XA-000-09-004-004-008-004-03 | 44.1 | 1171.5
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_11_15-13_26_19
OPERATOR : Oleksandr S.; Irakli K.;
SITE : GSI | SETUP : GSI_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 4088| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_B
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.4650', '1.848', '2.1890']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9930', '1.850', '0.6625']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.9870', '1.850', '0.2838']
Comment
CSA 5