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FEB_5003 17.08.23 11:29:37
TextEdit.txt
11:28:39:ST3_hmp4040:INFO: HAMEG,HMP2030,017836163,HW50010002/SW2.30
11:28:39:febtest:INFO: FEB8.2 selected
11:28:39:smx_tester:INFO: Setting Elink clock mode to 160 MHz
11:28:39:febtest:INFO: FEB8.2 selected
11:28:39:smx_tester:INFO: Setting Elink clock mode to 160 MHz
11:29:03:smx_tester:INFO: Setting Elink clock mode to 160 MHz
11:29:05:febtest:INFO: FEB8.2 selected
11:29:05:smx_tester:INFO: Setting Elink clock mode to 160 MHz
11:29:07:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:29:07:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
11:29:07:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:29:07:febtest:INFO: Tsting FEB with SN 2011
11:29:08:smx_tester:INFO: Scanning setup
11:29:08:elinks:INFO: Disabling clock on downlink 0
11:29:08:elinks:INFO: Disabling clock on downlink 1
11:29:08:elinks:INFO: Disabling clock on downlink 2
11:29:08:elinks:INFO: Disabling clock on downlink 3
11:29:08:elinks:INFO: Disabling clock on downlink 4
11:29:08:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:29:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:29:08:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:29:08:elinks:INFO: Disabling clock on downlink 0
11:29:08:elinks:INFO: Disabling clock on downlink 1
11:29:08:elinks:INFO: Disabling clock on downlink 2
11:29:08:elinks:INFO: Disabling clock on downlink 3
11:29:08:elinks:INFO: Disabling clock on downlink 4
11:29:08:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:29:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:29:08:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:29:08:elinks:INFO: Disabling clock on downlink 0
11:29:08:elinks:INFO: Disabling clock on downlink 1
11:29:08:elinks:INFO: Disabling clock on downlink 2
11:29:08:elinks:INFO: Disabling clock on downlink 3
11:29:08:elinks:INFO: Disabling clock on downlink 4
11:29:09:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:29:09:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:29:09:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:29:09:elinks:INFO: Disabling clock on downlink 0
11:29:09:elinks:INFO: Disabling clock on downlink 1
11:29:09:elinks:INFO: Disabling clock on downlink 2
11:29:09:elinks:INFO: Disabling clock on downlink 3
11:29:09:elinks:INFO: Disabling clock on downlink 4
11:29:09:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:29:09:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:29:09:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:29:09:elinks:INFO: Disabling clock on downlink 0
11:29:09:elinks:INFO: Disabling clock on downlink 1
11:29:09:elinks:INFO: Disabling clock on downlink 2
11:29:09:elinks:INFO: Disabling clock on downlink 3
11:29:09:elinks:INFO: Disabling clock on downlink 4
11:29:09:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:29:09:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:29:09:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:29:09:ST3_emu:ERROR: # of setup_elements is ZERO!
11:29:34:febtest:INFO: FEB8.5 selected
11:29:34:smx_tester:INFO: Setting Elink clock mode to 160 MHz
11:29:37:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:29:37:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
11:29:37:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:29:37:febtest:INFO: Tsting FEB with SN 5013
11:29:39:smx_tester:INFO: Scanning setup
11:29:39:elinks:INFO: Disabling clock on downlink 0
11:29:39:elinks:INFO: Disabling clock on downlink 1
11:29:39:elinks:INFO: Disabling clock on downlink 2
11:29:39:elinks:INFO: Disabling clock on downlink 3
11:29:39:elinks:INFO: Disabling clock on downlink 4
11:29:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:29:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:29:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:29:39:elinks:INFO: Disabling clock on downlink 0
11:29:39:elinks:INFO: Disabling clock on downlink 1
11:29:39:elinks:INFO: Disabling clock on downlink 2
11:29:39:elinks:INFO: Disabling clock on downlink 3
11:29:39:elinks:INFO: Disabling clock on downlink 4
11:29:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:29:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:29:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:29:39:elinks:INFO: Disabling clock on downlink 0
11:29:39:elinks:INFO: Disabling clock on downlink 1
11:29:39:elinks:INFO: Disabling clock on downlink 2
11:29:39:elinks:INFO: Disabling clock on downlink 3
11:29:39:elinks:INFO: Disabling clock on downlink 4
11:29:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:29:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 0
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 1
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 2
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 3
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 4
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 5
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 6
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 7
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 9
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 11
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 13
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 14
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 15
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 32
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 33
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 34
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 35
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 36
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 37
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 38
11:29:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 39
11:29:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:29:39:elinks:INFO: Disabling clock on downlink 0
11:29:39:elinks:INFO: Disabling clock on downlink 1
11:29:39:elinks:INFO: Disabling clock on downlink 2
11:29:39:elinks:INFO: Disabling clock on downlink 3
11:29:39:elinks:INFO: Disabling clock on downlink 4
11:29:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:29:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:29:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:29:39:elinks:INFO: Disabling clock on downlink 0
11:29:39:elinks:INFO: Disabling clock on downlink 1
11:29:39:elinks:INFO: Disabling clock on downlink 2
11:29:39:elinks:INFO: Disabling clock on downlink 3
11:29:39:elinks:INFO: Disabling clock on downlink 4
11:29:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:29:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:29:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:29:39:setup_element:INFO: Scanning clock phase
11:29:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:29:39:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:29:40:setup_element:INFO: Clock phase scan results for group 0, downlink 2
11:29:40:setup_element:INFO: Eye window for uplink 0 : ____________XXXXXX______________________________________________________________
Clock Delay: 54
11:29:40:setup_element:INFO: Eye window for uplink 1 : __________XXXX__________________________________________________________________
Clock Delay: 51
11:29:40:setup_element:INFO: Eye window for uplink 2 : ____________XXXXXX______________________________________________________________
Clock Delay: 54
11:29:40:setup_element:INFO: Eye window for uplink 3 : __________XXXX__________________________________________________________________
Clock Delay: 51
11:29:40:setup_element:INFO: Eye window for uplink 4 : ____________XXXXXX______________________________________________________________
Clock Delay: 54
11:29:40:setup_element:INFO: Eye window for uplink 5 : __________XXXX__________________________________________________________________
Clock Delay: 51
11:29:40:setup_element:INFO: Eye window for uplink 6 : ____________XXXXXX______________________________________________________________
Clock Delay: 54
11:29:40:setup_element:INFO: Eye window for uplink 7 : _______________XXX_X____________________________________________________________
Clock Delay: 57
11:29:40:setup_element:INFO: Eye window for uplink 9 : _____XXXXX______________________________________________________________________
Clock Delay: 47
11:29:40:setup_element:INFO: Eye window for uplink 11: _____XXXXX______________________________________________________________________
Clock Delay: 47
11:29:40:setup_element:INFO: Eye window for uplink 13: _____XXXXX______________________________________________________________________
Clock Delay: 47
11:29:40:setup_element:INFO: Eye window for uplink 14: ____________XXXXXX______________________________________________________________
Clock Delay: 54
11:29:40:setup_element:INFO: Eye window for uplink 15: __________XXXX__________________________________________________________________
Clock Delay: 51
11:29:40:setup_element:INFO: Eye window for uplink 16: ____XXXXXX______________________________________________________________________
Clock Delay: 46
11:29:40:setup_element:INFO: Eye window for uplink 17: ___XXXXX________________________________________________________________________
Clock Delay: 45
11:29:40:setup_element:INFO: Eye window for uplink 18: ____XXXXXX______________________________________________________________________
Clock Delay: 46
11:29:40:setup_element:INFO: Eye window for uplink 19: ___XXXXX________________________________________________________________________
Clock Delay: 45
11:29:40:setup_element:INFO: Eye window for uplink 21: _____XXXXX______________________________________________________________________
Clock Delay: 47
11:29:40:setup_element:INFO: Eye window for uplink 23: _____XXXXX______________________________________________________________________
Clock Delay: 47
11:29:40:setup_element:INFO: Eye window for uplink 24: ____________XXXXXX______________________________________________________________
Clock Delay: 54
11:29:40:setup_element:INFO: Eye window for uplink 25: _______________XXX_X____________________________________________________________
Clock Delay: 57
11:29:40:setup_element:INFO: Eye window for uplink 26: ____XXXXXX______________________________________________________________________
Clock Delay: 46
11:29:40:setup_element:INFO: Eye window for uplink 27: ___XXXXX________________________________________________________________________
Clock Delay: 45
11:29:40:setup_element:INFO: Eye window for uplink 28: ____XXXXXX______________________________________________________________________
Clock Delay: 46
11:29:40:setup_element:INFO: Eye window for uplink 29: ___XXXXX________________________________________________________________________
Clock Delay: 45
11:29:40:setup_element:INFO: Eye window for uplink 30: ____XXXXXX______________________________________________________________________
Clock Delay: 46
11:29:40:setup_element:INFO: Eye window for uplink 31: ___XXXXX________________________________________________________________________
Clock Delay: 45
11:29:40:setup_element:INFO: Eye window for uplink 32: ____________XXXXXX______________________________________________________________
Clock Delay: 54
11:29:40:setup_element:INFO: Eye window for uplink 33: __________XXXX__________________________________________________________________
Clock Delay: 51
11:29:40:setup_element:INFO: Eye window for uplink 34: ____________XXXXXX______________________________________________________________
Clock Delay: 54
11:29:40:setup_element:INFO: Eye window for uplink 35: _______________XXX_X____________________________________________________________
Clock Delay: 57
11:29:40:setup_element:INFO: Eye window for uplink 36: ____________XXXXXX______________________________________________________________
Clock Delay: 54
11:29:40:setup_element:INFO: Eye window for uplink 37: _______________XXX_X____________________________________________________________
Clock Delay: 57
11:29:40:setup_element:INFO: Eye window for uplink 38: ____________XXXXXX______________________________________________________________
Clock Delay: 54
11:29:40:setup_element:INFO: Eye window for uplink 39: _______________XXX_X____________________________________________________________
Clock Delay: 57
11:29:40:setup_element:INFO: Setting the clock phase to 51 for group 0, downlink 2
11:29:40:setup_element:INFO: Scanning data phases
11:29:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:29:40:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:29:45:setup_element:INFO: Data phase scan results for group 0, downlink 2
11:29:45:setup_element:INFO: Eye window for uplink 0 : __________________XXXXXX________________
Data delay found: 0
11:29:45:setup_element:INFO: Eye window for uplink 1 : _______XXXXX____________________________
Data delay found: 29
11:29:45:setup_element:INFO: Eye window for uplink 2 : _________________XXXXXX_________________
Data delay found: 39
11:29:45:setup_element:INFO: Eye window for uplink 3 : ________XXXX_X__________________________
Data delay found: 30
11:29:45:setup_element:INFO: Eye window for uplink 4 : ___________________XXXX_________________
Data delay found: 0
11:29:45:setup_element:INFO: Eye window for uplink 5 : _______XXXXXXX__________________________
Data delay found: 30
11:29:45:setup_element:INFO: Eye window for uplink 6 : ___________XXXXX________________________
Data delay found: 33
11:29:45:setup_element:INFO: Eye window for uplink 7 : ______________________XXXX______________
Data delay found: 3
11:29:45:setup_element:INFO: Eye window for uplink 9 : ___XXXXX________________________________
Data delay found: 25
11:29:45:setup_element:INFO: Eye window for uplink 11: ___XXXXX________________________________
Data delay found: 25
11:29:45:setup_element:INFO: Eye window for uplink 13: ____XXXXX_______________________________
Data delay found: 26
11:29:45:setup_element:INFO: Eye window for uplink 14: ___________________XXXX_________________
Data delay found: 0
11:29:45:setup_element:INFO: Eye window for uplink 15: ________XXXXXX__________________________
Data delay found: 30
11:29:45:setup_element:INFO: Eye window for uplink 16: ________XXXX____________________________
Data delay found: 29
11:29:45:setup_element:INFO: Eye window for uplink 17: _______XXXXX____________________________
Data delay found: 29
11:29:45:setup_element:INFO: Eye window for uplink 18: ________XXXX____________________________
Data delay found: 29
11:29:45:setup_element:INFO: Eye window for uplink 19: _________XXXX___________________________
Data delay found: 30
11:29:45:setup_element:INFO: Eye window for uplink 21: ____XXXXX_______________________________
Data delay found: 26
11:29:45:setup_element:INFO: Eye window for uplink 23: ___XXXXXX_______________________________
Data delay found: 25
11:29:45:setup_element:INFO: Eye window for uplink 24: ________________X_XXXX__________________
Data delay found: 38
11:29:45:setup_element:INFO: Eye window for uplink 25: ____________________________XXXXX_______
Data delay found: 10
11:29:45:setup_element:INFO: Eye window for uplink 26: ________XXXX____________________________
Data delay found: 29
11:29:45:setup_element:INFO: Eye window for uplink 27: __________XXXXXX________________________
Data delay found: 32
11:29:45:setup_element:INFO: Eye window for uplink 28: __________XXX___________________________
Data delay found: 31
11:29:45:setup_element:INFO: Eye window for uplink 29: ___________XXXXX________________________
Data delay found: 33
11:29:45:setup_element:INFO: Eye window for uplink 30: __________XXXX__________________________
Data delay found: 31
11:29:45:setup_element:INFO: Eye window for uplink 31: ________XXXXX___________________________
Data delay found: 30
11:29:45:setup_element:INFO: Eye window for uplink 32: ____________________XXXXX_______________
Data delay found: 2
11:29:45:setup_element:INFO: Eye window for uplink 33: _________XXXXXX_________________________
Data delay found: 31
11:29:45:setup_element:INFO: Eye window for uplink 34: _______________XXXXXX___________________
Data delay found: 37
11:29:45:setup_element:INFO: Eye window for uplink 35: __________________________XXXX__________
Data delay found: 7
11:29:45:setup_element:INFO: Eye window for uplink 36: ______________XXXXX_____________________
Data delay found: 36
11:29:45:setup_element:INFO: Eye window for uplink 37: __________________________XXXX__________
Data delay found: 7
11:29:45:setup_element:INFO: Eye window for uplink 38: ________________XXX_____________________
Data delay found: 37
11:29:45:setup_element:INFO: Eye window for uplink 39: ___________________________XXXXX________
Data delay found: 9
11:29:45:setup_element:INFO: Setting the data phase to 0 for uplink 0
11:29:45:setup_element:INFO: Setting the data phase to 29 for uplink 1
11:29:45:setup_element:INFO: Setting the data phase to 39 for uplink 2
11:29:45:setup_element:INFO: Setting the data phase to 30 for uplink 3
11:29:45:setup_element:INFO: Setting the data phase to 0 for uplink 4
11:29:45:setup_element:INFO: Setting the data phase to 30 for uplink 5
11:29:45:setup_element:INFO: Setting the data phase to 33 for uplink 6
11:29:45:setup_element:INFO: Setting the data phase to 3 for uplink 7
11:29:45:setup_element:INFO: Setting the data phase to 25 for uplink 9
11:29:45:setup_element:INFO: Setting the data phase to 25 for uplink 11
11:29:45:setup_element:INFO: Setting the data phase to 26 for uplink 13
11:29:45:setup_element:INFO: Setting the data phase to 0 for uplink 14
11:29:45:setup_element:INFO: Setting the data phase to 30 for uplink 15
11:29:45:setup_element:INFO: Setting the data phase to 29 for uplink 16
11:29:45:setup_element:INFO: Setting the data phase to 29 for uplink 17
11:29:45:setup_element:INFO: Setting the data phase to 29 for uplink 18
11:29:45:setup_element:INFO: Setting the data phase to 30 for uplink 19
11:29:45:setup_element:INFO: Setting the data phase to 26 for uplink 21
11:29:45:setup_element:INFO: Setting the data phase to 25 for uplink 23
11:29:45:setup_element:INFO: Setting the data phase to 38 for uplink 24
11:29:45:setup_element:INFO: Setting the data phase to 10 for uplink 25
11:29:45:setup_element:INFO: Setting the data phase to 29 for uplink 26
11:29:45:setup_element:INFO: Setting the data phase to 32 for uplink 27
11:29:45:setup_element:INFO: Setting the data phase to 31 for uplink 28
11:29:45:setup_element:INFO: Setting the data phase to 33 for uplink 29
11:29:45:setup_element:INFO: Setting the data phase to 31 for uplink 30
11:29:45:setup_element:INFO: Setting the data phase to 30 for uplink 31
11:29:45:setup_element:INFO: Setting the data phase to 2 for uplink 32
11:29:45:setup_element:INFO: Setting the data phase to 31 for uplink 33
11:29:45:setup_element:INFO: Setting the data phase to 37 for uplink 34
11:29:45:setup_element:INFO: Setting the data phase to 7 for uplink 35
11:29:45:setup_element:INFO: Setting the data phase to 36 for uplink 36
11:29:45:setup_element:INFO: Setting the data phase to 7 for uplink 37
11:29:45:setup_element:INFO: Setting the data phase to 37 for uplink 38
11:29:45:setup_element:INFO: Setting the data phase to 9 for uplink 39
11:29:45:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 9, 11, 13, 14, 15, 16, 17, 18, 19, 21, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 51
Window Length: 63
Eye Windows:
Uplink 0: ____________XXXXXX______________________________________________________________
Uplink 1: __________XXXX__________________________________________________________________
Uplink 2: ____________XXXXXX______________________________________________________________
Uplink 3: __________XXXX__________________________________________________________________
Uplink 4: ____________XXXXXX______________________________________________________________
Uplink 5: __________XXXX__________________________________________________________________
Uplink 6: ____________XXXXXX______________________________________________________________
Uplink 7: _______________XXX_X____________________________________________________________
Uplink 9: _____XXXXX______________________________________________________________________
Uplink 11: _____XXXXX______________________________________________________________________
Uplink 13: _____XXXXX______________________________________________________________________
Uplink 14: ____________XXXXXX______________________________________________________________
Uplink 15: __________XXXX__________________________________________________________________
Uplink 16: ____XXXXXX______________________________________________________________________
Uplink 17: ___XXXXX________________________________________________________________________
Uplink 18: ____XXXXXX______________________________________________________________________
Uplink 19: ___XXXXX________________________________________________________________________
Uplink 21: _____XXXXX______________________________________________________________________
Uplink 23: _____XXXXX______________________________________________________________________
Uplink 24: ____________XXXXXX______________________________________________________________
Uplink 25: _______________XXX_X____________________________________________________________
Uplink 26: ____XXXXXX______________________________________________________________________
Uplink 27: ___XXXXX________________________________________________________________________
Uplink 28: ____XXXXXX______________________________________________________________________
Uplink 29: ___XXXXX________________________________________________________________________
Uplink 30: ____XXXXXX______________________________________________________________________
Uplink 31: ___XXXXX________________________________________________________________________
Uplink 32: ____________XXXXXX______________________________________________________________
Uplink 33: __________XXXX__________________________________________________________________
Uplink 34: ____________XXXXXX______________________________________________________________
Uplink 35: _______________XXX_X____________________________________________________________
Uplink 36: ____________XXXXXX______________________________________________________________
Uplink 37: _______________XXX_X____________________________________________________________
Uplink 38: ____________XXXXXX______________________________________________________________
Uplink 39: _______________XXX_X____________________________________________________________
Data phase characteristics:
Uplink 0:
Optimal Phase: 0
Window Length: 34
Eye Window: __________________XXXXXX________________
Uplink 1:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 2:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
Uplink 3:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXX_X__________________________
Uplink 4:
Optimal Phase: 0
Window Length: 36
Eye Window: ___________________XXXX_________________
Uplink 5:
Optimal Phase: 30
Window Length: 33
Eye Window: _______XXXXXXX__________________________
Uplink 6:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 7:
Optimal Phase: 3
Window Length: 36
Eye Window: ______________________XXXX______________
Uplink 9:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 11:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 13:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 14:
Optimal Phase: 0
Window Length: 36
Eye Window: ___________________XXXX_________________
Uplink 15:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 16:
Optimal Phase: 29
Window Length: 36
Eye Window: ________XXXX____________________________
Uplink 17:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 18:
Optimal Phase: 29
Window Length: 36
Eye Window: ________XXXX____________________________
Uplink 19:
Optimal Phase: 30
Window Length: 36
Eye Window: _________XXXX___________________________
Uplink 21:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 23:
Optimal Phase: 25
Window Length: 34
Eye Window: ___XXXXXX_______________________________
Uplink 24:
Optimal Phase: 38
Window Length: 34
Eye Window: ________________X_XXXX__________________
Uplink 25:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 26:
Optimal Phase: 29
Window Length: 36
Eye Window: ________XXXX____________________________
Uplink 27:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 28:
Optimal Phase: 31
Window Length: 37
Eye Window: __________XXX___________________________
Uplink 29:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 30:
Optimal Phase: 31
Window Length: 36
Eye Window: __________XXXX__________________________
Uplink 31:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 32:
Optimal Phase: 2
Window Length: 35
Eye Window: ____________________XXXXX_______________
Uplink 33:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 34:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 35:
Optimal Phase: 7
Window Length: 36
Eye Window: __________________________XXXX__________
Uplink 36:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 37:
Optimal Phase: 7
Window Length: 36
Eye Window: __________________________XXXX__________
Uplink 38:
Optimal Phase: 37
Window Length: 37
Eye Window: ________________XXX_____________________
Uplink 39:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
]
11:29:45:setup_element:INFO: Beginning SMX ASICs map scan
11:29:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:29:45:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:29:45:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
11:29:45:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
11:29:45:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 9, 11, 13, 14, 15, 16, 17, 18, 19, 21, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39]
11:29:45:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 7
11:29:45:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 37
11:29:46:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 2, uplink 39
11:29:46:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 3, uplink 35
11:29:46:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 4, uplink 25
11:29:46:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 27
11:29:46:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 29
11:29:46:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 2, uplink 31
11:29:46:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 3, uplink 17
11:29:46:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 4, uplink 19
11:29:46:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 32
11:29:46:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 4
11:29:46:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 2, uplink 0
11:29:46:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 3, uplink 2
11:29:46:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 4, uplink 14
11:29:46:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 6
11:29:46:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 38
11:29:46:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 2, uplink 36
11:29:46:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 3, uplink 34
11:29:46:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 4, uplink 24
11:29:46:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
11:29:46:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 30
11:29:46:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 2, uplink 28
11:29:47:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 3, uplink 18
11:29:47:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 4, uplink 16
11:29:47:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 33
11:29:47:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 5
11:29:47:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 2, uplink 1
11:29:47:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 3, uplink 3
11:29:47:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 4, uplink 15
11:29:47:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 13
11:29:47:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 9
11:29:47:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 2, uplink 11
11:29:47:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 3, uplink 21
11:29:47:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 4, uplink 23
11:29:48:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 9, 11, 13, 14, 15, 16, 17, 18, 19, 21, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 7), (1, 37), (2, 39), (3, 35), (4, 25)
ASIC address 0x1: (ASIC uplink, uplink): (0, 27), (1, 29), (2, 31), (3, 17), (4, 19)
ASIC address 0x2: (ASIC uplink, uplink): (0, 32), (1, 4), (2, 0), (3, 2), (4, 14)
ASIC address 0x4: (ASIC uplink, uplink): (0, 6), (1, 38), (2, 36), (3, 34), (4, 24)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 30), (2, 28), (3, 18), (4, 16)
ASIC address 0x6: (ASIC uplink, uplink): (0, 33), (1, 5), (2, 1), (3, 3), (4, 15)
ASIC address 0x7: (ASIC uplink, uplink): (0, 13), (1, 9), (2, 11), (3, 21), (4, 23)
Clock Phase Characteristic:
Optimal Phase: 51
Window Length: 63
Eye Windows:
Uplink 0: ____________XXXXXX______________________________________________________________
Uplink 1: __________XXXX__________________________________________________________________
Uplink 2: ____________XXXXXX______________________________________________________________
Uplink 3: __________XXXX__________________________________________________________________
Uplink 4: ____________XXXXXX______________________________________________________________
Uplink 5: __________XXXX__________________________________________________________________
Uplink 6: ____________XXXXXX______________________________________________________________
Uplink 7: _______________XXX_X____________________________________________________________
Uplink 9: _____XXXXX______________________________________________________________________
Uplink 11: _____XXXXX______________________________________________________________________
Uplink 13: _____XXXXX______________________________________________________________________
Uplink 14: ____________XXXXXX______________________________________________________________
Uplink 15: __________XXXX__________________________________________________________________
Uplink 16: ____XXXXXX______________________________________________________________________
Uplink 17: ___XXXXX________________________________________________________________________
Uplink 18: ____XXXXXX______________________________________________________________________
Uplink 19: ___XXXXX________________________________________________________________________
Uplink 21: _____XXXXX______________________________________________________________________
Uplink 23: _____XXXXX______________________________________________________________________
Uplink 24: ____________XXXXXX______________________________________________________________
Uplink 25: _______________XXX_X____________________________________________________________
Uplink 26: ____XXXXXX______________________________________________________________________
Uplink 27: ___XXXXX________________________________________________________________________
Uplink 28: ____XXXXXX______________________________________________________________________
Uplink 29: ___XXXXX________________________________________________________________________
Uplink 30: ____XXXXXX______________________________________________________________________
Uplink 31: ___XXXXX________________________________________________________________________
Uplink 32: ____________XXXXXX______________________________________________________________
Uplink 33: __________XXXX__________________________________________________________________
Uplink 34: ____________XXXXXX______________________________________________________________
Uplink 35: _______________XXX_X____________________________________________________________
Uplink 36: ____________XXXXXX______________________________________________________________
Uplink 37: _______________XXX_X____________________________________________________________
Uplink 38: ____________XXXXXX______________________________________________________________
Uplink 39: _______________XXX_X____________________________________________________________
Data phase characteristics:
Uplink 0:
Optimal Phase: 0
Window Length: 34
Eye Window: __________________XXXXXX________________
Uplink 1:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 2:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
Uplink 3:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXX_X__________________________
Uplink 4:
Optimal Phase: 0
Window Length: 36
Eye Window: ___________________XXXX_________________
Uplink 5:
Optimal Phase: 30
Window Length: 33
Eye Window: _______XXXXXXX__________________________
Uplink 6:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 7:
Optimal Phase: 3
Window Length: 36
Eye Window: ______________________XXXX______________
Uplink 9:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 11:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 13:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 14:
Optimal Phase: 0
Window Length: 36
Eye Window: ___________________XXXX_________________
Uplink 15:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 16:
Optimal Phase: 29
Window Length: 36
Eye Window: ________XXXX____________________________
Uplink 17:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 18:
Optimal Phase: 29
Window Length: 36
Eye Window: ________XXXX____________________________
Uplink 19:
Optimal Phase: 30
Window Length: 36
Eye Window: _________XXXX___________________________
Uplink 21:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 23:
Optimal Phase: 25
Window Length: 34
Eye Window: ___XXXXXX_______________________________
Uplink 24:
Optimal Phase: 38
Window Length: 34
Eye Window: ________________X_XXXX__________________
Uplink 25:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 26:
Optimal Phase: 29
Window Length: 36
Eye Window: ________XXXX____________________________
Uplink 27:
Optimal Phase: 32
Window Length: 34
Eye Window: __________XXXXXX________________________
Uplink 28:
Optimal Phase: 31
Window Length: 37
Eye Window: __________XXX___________________________
Uplink 29:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 30:
Optimal Phase: 31
Window Length: 36
Eye Window: __________XXXX__________________________
Uplink 31:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 32:
Optimal Phase: 2
Window Length: 35
Eye Window: ____________________XXXXX_______________
Uplink 33:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 34:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 35:
Optimal Phase: 7
Window Length: 36
Eye Window: __________________________XXXX__________
Uplink 36:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 37:
Optimal Phase: 7
Window Length: 36
Eye Window: __________________________XXXX__________
Uplink 38:
Optimal Phase: 37
Window Length: 37
Eye Window: ________________XXX_____________________
Uplink 39:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
11:29:48:setup_element:INFO: Performing Elink synchronization
11:29:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:29:48:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:29:48:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
11:29:48:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
11:29:48:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
11:29:48:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 9, 11, 13, 14, 15, 16, 17, 18, 19, 21, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39]
11:29:48:ST3_emu:INFO: Number of chips: 7
11:29:48:ST3_emu:INFO: Chip address: 0x0
11:29:48:ST3_emu:INFO: Chip address: 0x1
11:29:48:ST3_emu:INFO: Chip address: 0x2
11:29:48:ST3_emu:INFO: Chip address: 0x4
11:29:48:ST3_emu:INFO: Chip address: 0x5
11:29:48:ST3_emu:INFO: Chip address: 0x6
11:29:48:ST3_emu:INFO: Chip address: 0x7
11:29:49:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:29:50:febtest:INFO: 0-0 | XA-000-00-002-000-000-039-11 | 9.3 | 1277.1
11:29:50:febtest:INFO: 0-1 | XA-000-00-002-000-000-033-11 | 15.6 | 1230.3
11:29:50:febtest:INFO: 0-2 | XA-000-00-002-000-000-040-11 | 9.3 | 1277.1
11:29:50:febtest:INFO: 0-4 | XA-000-00-002-000-000-041-11 | 12.4 | 1282.9
11:29:51:febtest:INFO: 0-5 | XA-000-00-002-000-000-037-11 | 15.6 | 1247.9
11:29:51:febtest:INFO: 0-6 | XA-000-00-002-000-000-042-11 | 12.4 | 1259.6
11:29:51:febtest:INFO: 0-7 | XA-000-00-002-000-000-038-11 | 6.1 | 1277.1
11:29:51:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:29:55:ST3_smx:ERROR: Wrong readback, reg. (130, 17) in 0 out 91
11:29:55:ST3_smx:ERROR: Wrong readback, reg. (130, 18) in 122 out 91
11:29:55:ST3_smx:INFO: chip: 0-0 12.438562 C 1242.040240 mV
11:29:55:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:29:55:ST3_smx:INFO: Electrons
11:29:55:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:29:57:ST3_smx:INFO: ----> Checking Analog response
11:29:57:ST3_smx:INFO: ----> Checking broken channels
11:29:57:ST3_smx:INFO: Total # broken ch: 0
11:29:57:ST3_smx:INFO: List FAST: []
11:29:57:ST3_smx:INFO: List SLOW: []
11:29:57:ST3_smx:INFO: Holes
11:29:57:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:29:59:ST3_smx:INFO: ----> Checking Analog response
11:29:59:ST3_smx:INFO: ----> Checking broken channels
11:29:59:ST3_smx:INFO: Total # broken ch: 0
11:29:59:ST3_smx:INFO: List FAST: []
11:29:59:ST3_smx:INFO: List SLOW: []
11:29:59:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:30:00:febtest:INFO: 0-0 | XA-000-00-002-000-000-039-11 | 15.6 | 1236.2
11:30:00:febtest:INFO: 0-1 | XA-000-00-002-000-000-033-11 | 15.6 | 1230.3
11:30:00:febtest:INFO: 0-2 | XA-000-00-002-000-000-040-11 | 9.3 | 1271.2
11:30:00:febtest:INFO: 0-4 | XA-000-00-002-000-000-041-11 | 12.4 | 1277.1
11:30:01:febtest:INFO: 0-5 | XA-000-00-002-000-000-037-11 | 15.6 | 1247.9
11:30:01:febtest:INFO: 0-6 | XA-000-00-002-000-000-042-11 | 12.4 | 1253.7
11:30:01:febtest:INFO: 0-7 | XA-000-00-002-000-000-038-11 | 6.1 | 1277.1
11:30:01:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:30:05:ST3_smx:ERROR: Wrong readback, reg. (130, 17) in 0 out 91
11:30:05:ST3_smx:ERROR: Wrong readback, reg. (130, 18) in 122 out 91
11:30:05:ST3_smx:INFO: chip: 0-1 25.062742 C 1189.190035 mV
11:30:05:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:30:05:ST3_smx:INFO: Electrons
11:30:05:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:30:07:ST3_smx:INFO: ----> Checking Analog response
11:30:07:ST3_smx:INFO: ----> Checking broken channels
11:30:07:ST3_smx:INFO: Total # broken ch: 0
11:30:07:ST3_smx:INFO: List FAST: []
11:30:07:ST3_smx:INFO: List SLOW: []
11:30:07:ST3_smx:INFO: Holes
11:30:07:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:30:09:ST3_smx:INFO: ----> Checking Analog response
11:30:09:ST3_smx:INFO: ----> Checking broken channels
11:30:09:ST3_smx:INFO: Total # broken ch: 0
11:30:09:ST3_smx:INFO: List FAST: []
11:30:09:ST3_smx:INFO: List SLOW: []
11:30:09:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:30:10:febtest:INFO: 0-0 | XA-000-00-002-000-000-039-11 | 15.6 | 1236.2
11:30:10:febtest:INFO: 0-1 | XA-000-00-002-000-000-033-11 | 25.1 | 1183.3
11:30:10:febtest:INFO: 0-2 | XA-000-00-002-000-000-040-11 | 12.4 | 1271.2
11:30:10:febtest:INFO: 0-4 | XA-000-00-002-000-000-041-11 | 12.4 | 1277.1
11:30:10:febtest:INFO: 0-5 | XA-000-00-002-000-000-037-11 | 15.6 | 1247.9
11:30:11:febtest:INFO: 0-6 | XA-000-00-002-000-000-042-11 | 15.6 | 1253.7
11:30:11:febtest:INFO: 0-7 | XA-000-00-002-000-000-038-11 | 6.1 | 1277.1
11:30:11:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:30:15:ST3_smx:ERROR: Wrong readback, reg. (130, 17) in 0 out 91
11:30:15:ST3_smx:ERROR: Wrong readback, reg. (130, 18) in 122 out 91
11:30:15:ST3_smx:INFO: chip: 0-2 15.590880 C 1247.887635 mV
11:30:15:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:30:15:ST3_smx:INFO: Electrons
11:30:15:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:30:17:ST3_smx:INFO: ----> Checking Analog response
11:30:17:ST3_smx:INFO: ----> Checking broken channels
11:30:17:ST3_smx:INFO: Total # broken ch: 0
11:30:17:ST3_smx:INFO: List FAST: []
11:30:17:ST3_smx:INFO: List SLOW: []
11:30:17:ST3_smx:INFO: Holes
11:30:17:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:30:19:ST3_smx:INFO: ----> Checking Analog response
11:30:19:ST3_smx:INFO: ----> Checking broken channels
11:30:19:ST3_smx:INFO: Total # broken ch: 0
11:30:19:ST3_smx:INFO: List FAST: []
11:30:19:ST3_smx:INFO: List SLOW: []
11:30:19:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:30:20:febtest:INFO: 0-0 | XA-000-00-002-000-000-039-11 | 18.7 | 1236.2
11:30:20:febtest:INFO: 0-1 | XA-000-00-002-000-000-033-11 | 28.2 | 1183.3
11:30:20:febtest:INFO: 0-2 | XA-000-00-002-000-000-040-11 | 15.6 | 1242.0
11:30:20:febtest:INFO: 0-4 | XA-000-00-002-000-000-041-11 | 12.4 | 1277.1
11:30:20:febtest:INFO: 0-5 | XA-000-00-002-000-000-037-11 | 15.6 | 1247.9
11:30:21:febtest:INFO: 0-6 | XA-000-00-002-000-000-042-11 | 15.6 | 1253.7
11:30:21:febtest:INFO: 0-7 | XA-000-00-002-000-000-038-11 | 9.3 | 1271.2
11:30:21:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:30:25:ST3_smx:ERROR: Wrong readback, reg. (130, 17) in 0 out 91
11:30:25:ST3_smx:ERROR: Wrong readback, reg. (130, 18) in 122 out 91
11:30:25:ST3_smx:INFO: chip: 0-4 25.062742 C 1224.468235 mV
11:30:25:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:30:25:ST3_smx:INFO: Electrons
11:30:25:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:30:27:ST3_smx:INFO: ----> Checking Analog response
11:30:27:ST3_smx:INFO: ----> Checking broken channels
11:30:27:ST3_smx:INFO: Total # broken ch: 0
11:30:27:ST3_smx:INFO: List FAST: []
11:30:27:ST3_smx:INFO: List SLOW: []
11:30:27:ST3_smx:INFO: Holes
11:30:27:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:30:30:ST3_smx:INFO: ----> Checking Analog response
11:30:30:ST3_smx:INFO: ----> Checking broken channels
11:30:30:ST3_smx:INFO: Total # broken ch: 0
11:30:30:ST3_smx:INFO: List FAST: []
11:30:30:ST3_smx:INFO: List SLOW: []
11:30:30:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:30:30:febtest:INFO: 0-0 | XA-000-00-002-000-000-039-11 | 18.7 | 1230.3
11:30:30:febtest:INFO: 0-1 | XA-000-00-002-000-000-033-11 | 28.2 | 1183.3
11:30:31:febtest:INFO: 0-2 | XA-000-00-002-000-000-040-11 | 18.7 | 1242.0
11:30:31:febtest:INFO: 0-4 | XA-000-00-002-000-000-041-11 | 25.1 | 1224.5
11:30:31:febtest:INFO: 0-5 | XA-000-00-002-000-000-037-11 | 18.7 | 1247.9
11:30:31:febtest:INFO: 0-6 | XA-000-00-002-000-000-042-11 | 15.6 | 1247.9
11:30:31:febtest:INFO: 0-7 | XA-000-00-002-000-000-038-11 | 9.3 | 1277.1
11:30:32:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:30:36:ST3_smx:ERROR: Wrong readback, reg. (130, 17) in 0 out 91
11:30:36:ST3_smx:ERROR: Wrong readback, reg. (130, 18) in 122 out 91
11:30:36:ST3_smx:INFO: chip: 0-5 21.902970 C 1218.600960 mV
11:30:36:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:30:36:ST3_smx:INFO: Electrons
11:30:36:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:30:38:ST3_smx:INFO: ----> Checking Analog response
11:30:38:ST3_smx:INFO: ----> Checking broken channels
11:30:38:ST3_smx:INFO: Total # broken ch: 0
11:30:38:ST3_smx:INFO: List FAST: []
11:30:38:ST3_smx:INFO: List SLOW: []
11:30:38:ST3_smx:INFO: Holes
11:30:38:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:30:40:ST3_smx:INFO: ----> Checking Analog response
11:30:40:ST3_smx:INFO: ----> Checking broken channels
11:30:41:ST3_smx:INFO: Total # broken ch: 0
11:30:41:ST3_smx:INFO: List FAST: []
11:30:41:ST3_smx:INFO: List SLOW: []
11:30:41:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:30:41:febtest:INFO: 0-0 | XA-000-00-002-000-000-039-11 | 18.7 | 1236.2
11:30:41:febtest:INFO: 0-1 | XA-000-00-002-000-000-033-11 | 28.2 | 1183.3
11:30:41:febtest:INFO: 0-2 | XA-000-00-002-000-000-040-11 | 18.7 | 1242.0
11:30:41:febtest:INFO: 0-4 | XA-000-00-002-000-000-041-11 | 25.1 | 1224.5
11:30:42:febtest:INFO: 0-5 | XA-000-00-002-000-000-037-11 | 25.1 | 1212.7
11:30:42:febtest:INFO: 0-6 | XA-000-00-002-000-000-042-11 | 18.7 | 1253.7
11:30:42:febtest:INFO: 0-7 | XA-000-00-002-000-000-038-11 | 9.3 | 1271.2
11:30:42:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:30:46:ST3_smx:ERROR: Wrong readback, reg. (130, 17) in 0 out 91
11:30:46:ST3_smx:ERROR: Wrong readback, reg. (130, 18) in 122 out 91
11:30:46:ST3_smx:INFO: chip: 0-6 21.902970 C 1218.600960 mV
11:30:46:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:30:46:ST3_smx:INFO: Electrons
11:30:46:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:30:49:ST3_smx:INFO: ----> Checking Analog response
11:30:49:ST3_smx:INFO: ----> Checking broken channels
11:30:49:ST3_smx:INFO: Total # broken ch: 0
11:30:49:ST3_smx:INFO: List FAST: []
11:30:49:ST3_smx:INFO: List SLOW: []
11:30:49:ST3_smx:INFO: Holes
11:30:49:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:30:51:ST3_smx:INFO: ----> Checking Analog response
11:30:51:ST3_smx:INFO: ----> Checking broken channels
11:30:51:ST3_smx:INFO: Total # broken ch: 0
11:30:51:ST3_smx:INFO: List FAST: []
11:30:51:ST3_smx:INFO: List SLOW: []
11:30:51:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:30:51:febtest:INFO: 0-0 | XA-000-00-002-000-000-039-11 | 18.7 | 1230.3
11:30:52:febtest:INFO: 0-1 | XA-000-00-002-000-000-033-11 | 28.2 | 1183.3
11:30:52:febtest:INFO: 0-2 | XA-000-00-002-000-000-040-11 | 18.7 | 1242.0
11:30:52:febtest:INFO: 0-4 | XA-000-00-002-000-000-041-11 | 25.1 | 1224.5
11:30:52:febtest:INFO: 0-5 | XA-000-00-002-000-000-037-11 | 25.1 | 1212.7
11:30:53:febtest:INFO: 0-6 | XA-000-00-002-000-000-042-11 | 25.1 | 1218.6
11:30:53:febtest:INFO: 0-7 | XA-000-00-002-000-000-038-11 | 9.3 | 1271.2
11:30:53:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:30:57:ST3_smx:ERROR: Wrong readback, reg. (130, 17) in 0 out 91
11:30:57:ST3_smx:ERROR: Wrong readback, reg. (130, 18) in 122 out 91
11:30:57:ST3_smx:INFO: chip: 0-7 15.590880 C 1242.040240 mV
11:30:57:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:30:57:ST3_smx:INFO: Electrons
11:30:57:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:30:59:ST3_smx:INFO: ----> Checking Analog response
11:30:59:ST3_smx:INFO: ----> Checking broken channels
11:31:00:ST3_smx:INFO: Total # broken ch: 0
11:31:00:ST3_smx:INFO: List FAST: []
11:31:00:ST3_smx:INFO: List SLOW: []
11:31:00:ST3_smx:INFO: Holes
11:31:00:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:31:02:ST3_smx:INFO: ----> Checking Analog response
11:31:02:ST3_smx:INFO: ----> Checking broken channels
11:31:02:ST3_smx:INFO: Total # broken ch: 0
11:31:02:ST3_smx:INFO: List FAST: []
11:31:02:ST3_smx:INFO: List SLOW: []
11:31:02:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:31:02:febtest:INFO: 0-0 | XA-000-00-002-000-000-039-11 | 18.7 | 1230.3
11:31:02:febtest:INFO: 0-1 | XA-000-00-002-000-000-033-11 | 28.2 | 1183.3
11:31:03:febtest:INFO: 0-2 | XA-000-00-002-000-000-040-11 | 18.7 | 1242.0
11:31:03:febtest:INFO: 0-4 | XA-000-00-002-000-000-041-11 | 28.2 | 1224.5
11:31:03:febtest:INFO: 0-5 | XA-000-00-002-000-000-037-11 | 25.1 | 1212.7
11:31:03:febtest:INFO: 0-6 | XA-000-00-002-000-000-042-11 | 25.1 | 1218.6
11:31:03:febtest:INFO: 0-7 | XA-000-00-002-000-000-038-11 | 18.7 | 1236.2
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_08_17-11_29_37', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-00-002-000-000-038-11', 'FUSED_ID': 6359364149360722539, 'HW_ADDR': 7, 'VERS_NO': '2.1', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.448', '1.5520', '1.847', '1.8350', '7.001', '1.5470', '7.001', '1.5460'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
11:31:46:ST3_Shared:INFO: Listo of operators:Oleksandr S.;
11:31:47:ST3_Shared:INFO: Listo of operators:Oleksandr S.; Irakli K.;
11:31:57:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_5003/A//TestDate_2023_08_17-11_29_37/