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FEB_5009 10.11.23 10:49:32
Info
10:49:25:febtest:INFO: FEB 8-5 A @ GSI
10:49:28:smx_tester:INFO: Setting Elink clock mode to 160 MHz
10:49:32:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:49:32:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
10:49:32:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:49:32:febtest:INFO: Tsting FEB with SN 5009
10:49:33:smx_tester:INFO: Scanning setup
10:49:33:elinks:INFO: Disabling clock on downlink 0
10:49:33:elinks:INFO: Disabling clock on downlink 1
10:49:33:elinks:INFO: Disabling clock on downlink 2
10:49:33:elinks:INFO: Disabling clock on downlink 3
10:49:33:elinks:INFO: Disabling clock on downlink 4
10:49:33:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:49:33:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:49:34:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:49:34:elinks:INFO: Disabling clock on downlink 0
10:49:34:elinks:INFO: Disabling clock on downlink 1
10:49:34:elinks:INFO: Disabling clock on downlink 2
10:49:34:elinks:INFO: Disabling clock on downlink 3
10:49:34:elinks:INFO: Disabling clock on downlink 4
10:49:34:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:49:34:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:49:34:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:49:34:elinks:INFO: Disabling clock on downlink 0
10:49:34:elinks:INFO: Disabling clock on downlink 1
10:49:34:elinks:INFO: Disabling clock on downlink 2
10:49:34:elinks:INFO: Disabling clock on downlink 3
10:49:34:elinks:INFO: Disabling clock on downlink 4
10:49:34:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:49:34:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 0
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 1
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 2
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 3
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 4
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 5
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 6
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 7
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 8
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 9
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 10
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 11
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 12
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 13
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 14
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 15
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 32
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 33
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 34
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 35
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 36
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 37
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 38
10:49:34:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 39
10:49:34:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:49:34:elinks:INFO: Disabling clock on downlink 0
10:49:34:elinks:INFO: Disabling clock on downlink 1
10:49:34:elinks:INFO: Disabling clock on downlink 2
10:49:34:elinks:INFO: Disabling clock on downlink 3
10:49:34:elinks:INFO: Disabling clock on downlink 4
10:49:34:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:49:34:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:49:34:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:49:34:elinks:INFO: Disabling clock on downlink 0
10:49:34:elinks:INFO: Disabling clock on downlink 1
10:49:34:elinks:INFO: Disabling clock on downlink 2
10:49:34:elinks:INFO: Disabling clock on downlink 3
10:49:34:elinks:INFO: Disabling clock on downlink 4
10:49:34:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:49:34:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
10:49:34:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:49:34:setup_element:INFO: Scanning clock phase
10:49:34:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:49:34:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:49:35:setup_element:INFO: Clock phase scan results for group 0, downlink 2
10:49:35:setup_element:INFO: Eye window for uplink 0 : _______XXXXXX___________________________________________________________________
Clock Delay: 49
10:49:35:setup_element:INFO: Eye window for uplink 1 : _______XXXXX____________________________________________________________________
Clock Delay: 49
10:49:35:setup_element:INFO: Eye window for uplink 2 : _______XXXXXX___________________________________________________________________
Clock Delay: 49
10:49:35:setup_element:INFO: Eye window for uplink 3 : _______XXXXX____________________________________________________________________
Clock Delay: 49
10:49:35:setup_element:INFO: Eye window for uplink 4 : _______XXXXXX___________________________________________________________________
Clock Delay: 49
10:49:35:setup_element:INFO: Eye window for uplink 5 : _______XXXXX____________________________________________________________________
Clock Delay: 49
10:49:35:setup_element:INFO: Eye window for uplink 6 : _______XXXXXX___________________________________________________________________
Clock Delay: 49
10:49:35:setup_element:INFO: Eye window for uplink 7 : _______XXXXX____________________________________________________________________
Clock Delay: 49
10:49:35:setup_element:INFO: Eye window for uplink 8 : ______XXXXXX____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 9 : ______XXXXXX____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 10: ______XXXXXX____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 11: ______XXXXXX____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 12: ______XXXXXX____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 13: ______XXXXXX____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 14: _______XXXXXX___________________________________________________________________
Clock Delay: 49
10:49:35:setup_element:INFO: Eye window for uplink 15: _______XXXXX____________________________________________________________________
Clock Delay: 49
10:49:35:setup_element:INFO: Eye window for uplink 16: ______XXXXXXX___________________________________________________________________
Clock Delay: 49
10:49:35:setup_element:INFO: Eye window for uplink 17: ________XXXXX___________________________________________________________________
Clock Delay: 50
10:49:35:setup_element:INFO: Eye window for uplink 18: ______XXXXXXX___________________________________________________________________
Clock Delay: 49
10:49:35:setup_element:INFO: Eye window for uplink 19: ________XXXXX___________________________________________________________________
Clock Delay: 50
10:49:35:setup_element:INFO: Eye window for uplink 20: ______XXXXXX____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 21: ______XXXXXX____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 22: ______XXXXXX____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 23: ______XXXXXX____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 24: ______XXXXXX____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 25: ______XXXXX_____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 26: ______XXXXXXX___________________________________________________________________
Clock Delay: 49
10:49:35:setup_element:INFO: Eye window for uplink 27: ________XXXXX___________________________________________________________________
Clock Delay: 50
10:49:35:setup_element:INFO: Eye window for uplink 28: ______XXXXXXX___________________________________________________________________
Clock Delay: 49
10:49:35:setup_element:INFO: Eye window for uplink 29: ________XXXXX___________________________________________________________________
Clock Delay: 50
10:49:35:setup_element:INFO: Eye window for uplink 30: ______XXXXXXX___________________________________________________________________
Clock Delay: 49
10:49:35:setup_element:INFO: Eye window for uplink 31: ________XXXXX___________________________________________________________________
Clock Delay: 50
10:49:35:setup_element:INFO: Eye window for uplink 32: ______XXXXXX____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 33: ______XXXXX_____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 34: ______XXXXXX____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 35: ______XXXXX_____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 36: ______XXXXXX____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 37: ______XXXXX_____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 38: ______XXXXXX____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Eye window for uplink 39: ______XXXXX_____________________________________________________________________
Clock Delay: 48
10:49:35:setup_element:INFO: Setting the clock phase to 49 for group 0, downlink 2
10:49:35:setup_element:INFO: Scanning data phases
10:49:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:49:35:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:49:41:setup_element:INFO: Data phase scan results for group 0, downlink 2
10:49:41:setup_element:INFO: Eye window for uplink 0 : _______________________XXXX_____________
Data delay found: 4
10:49:41:setup_element:INFO: Eye window for uplink 1 : __________________________XXXXX_________
Data delay found: 8
10:49:41:setup_element:INFO: Eye window for uplink 2 : _____________________XXXXXX_____________
Data delay found: 3
10:49:41:setup_element:INFO: Eye window for uplink 3 : ___________________________XXXXX________
Data delay found: 9
10:49:41:setup_element:INFO: Eye window for uplink 4 : ______________________X_XXXX____________
Data delay found: 4
10:49:41:setup_element:INFO: Eye window for uplink 5 : ____________________________XXXXX_______
Data delay found: 10
10:49:41:setup_element:INFO: Eye window for uplink 6 : ___________________X_XXXX_______________
Data delay found: 1
10:49:41:setup_element:INFO: Eye window for uplink 7 : _________________________XXXX___________
Data delay found: 6
10:49:41:setup_element:INFO: Eye window for uplink 8 : _________XXXXX__________________________
Data delay found: 31
10:49:41:setup_element:INFO: Eye window for uplink 9 : ____________XXXXX_______________________
Data delay found: 34
10:49:41:setup_element:INFO: Eye window for uplink 10: _______XXXXXX___________________________
Data delay found: 29
10:49:41:setup_element:INFO: Eye window for uplink 11: ___________XXXXX________________________
Data delay found: 33
10:49:41:setup_element:INFO: Eye window for uplink 12: _________XXXXX__________________________
Data delay found: 31
10:49:41:setup_element:INFO: Eye window for uplink 13: ___________XXXXX________________________
Data delay found: 33
10:49:41:setup_element:INFO: Eye window for uplink 14: ____________________XXXXX_______________
Data delay found: 2
10:49:41:setup_element:INFO: Eye window for uplink 15: __________________________XXXXX_________
Data delay found: 8
10:49:41:setup_element:INFO: Eye window for uplink 16: ______________XXXXX_____________________
Data delay found: 36
10:49:41:setup_element:INFO: Eye window for uplink 17: _________________XXXXXX_________________
Data delay found: 39
10:49:41:setup_element:INFO: Eye window for uplink 18: ______________XXXXX_____________________
Data delay found: 36
10:49:41:setup_element:INFO: Eye window for uplink 19: ________________XXXXX___________________
Data delay found: 38
10:49:41:setup_element:INFO: Eye window for uplink 20: ______________XXXX______________________
Data delay found: 35
10:49:41:setup_element:INFO: Eye window for uplink 21: ______________XXXXX_____________________
Data delay found: 36
10:49:41:setup_element:INFO: Eye window for uplink 22: _______________XXXX_____________________
Data delay found: 36
10:49:41:setup_element:INFO: Eye window for uplink 23: ____________XXXXX_______________________
Data delay found: 34
10:49:41:setup_element:INFO: Eye window for uplink 24: __________________________XXXXXX________
Data delay found: 8
10:49:41:setup_element:INFO: Eye window for uplink 25: __________________XXXXX_________________
Data delay found: 0
10:49:41:setup_element:INFO: Eye window for uplink 26: ___________XXXXXX_______________________
Data delay found: 33
10:49:41:setup_element:INFO: Eye window for uplink 27: _________________XXXXXX_________________
Data delay found: 39
10:49:41:setup_element:INFO: Eye window for uplink 28: _____________XXXXX______________________
Data delay found: 35
10:49:41:setup_element:INFO: Eye window for uplink 29: __________________XXXXX_________________
Data delay found: 0
10:49:41:setup_element:INFO: Eye window for uplink 30: _______________XXXXXX___________________
Data delay found: 37
10:49:41:setup_element:INFO: Eye window for uplink 31: ___________________XXXX_________________
Data delay found: 0
10:49:41:setup_element:INFO: Eye window for uplink 32: ___________________________XXXXX________
Data delay found: 9
10:49:41:setup_element:INFO: Eye window for uplink 33: ___________________XXXXX________________
Data delay found: 1
10:49:41:setup_element:INFO: Eye window for uplink 34: ___________________________XXXXX________
Data delay found: 9
10:49:41:setup_element:INFO: Eye window for uplink 35: ___________________XXXX_________________
Data delay found: 0
10:49:41:setup_element:INFO: Eye window for uplink 36: _________________________XXXXX__________
Data delay found: 7
10:49:41:setup_element:INFO: Eye window for uplink 37: __________________XXXX__________________
Data delay found: 39
10:49:41:setup_element:INFO: Eye window for uplink 38: ___________________________XXXX_________
Data delay found: 8
10:49:41:setup_element:INFO: Eye window for uplink 39: ___________________XXXXX________________
Data delay found: 1
10:49:41:setup_element:INFO: Setting the data phase to 4 for uplink 0
10:49:41:setup_element:INFO: Setting the data phase to 8 for uplink 1
10:49:41:setup_element:INFO: Setting the data phase to 3 for uplink 2
10:49:41:setup_element:INFO: Setting the data phase to 9 for uplink 3
10:49:41:setup_element:INFO: Setting the data phase to 4 for uplink 4
10:49:41:setup_element:INFO: Setting the data phase to 10 for uplink 5
10:49:41:setup_element:INFO: Setting the data phase to 1 for uplink 6
10:49:41:setup_element:INFO: Setting the data phase to 6 for uplink 7
10:49:41:setup_element:INFO: Setting the data phase to 31 for uplink 8
10:49:41:setup_element:INFO: Setting the data phase to 34 for uplink 9
10:49:41:setup_element:INFO: Setting the data phase to 29 for uplink 10
10:49:41:setup_element:INFO: Setting the data phase to 33 for uplink 11
10:49:41:setup_element:INFO: Setting the data phase to 31 for uplink 12
10:49:41:setup_element:INFO: Setting the data phase to 33 for uplink 13
10:49:41:setup_element:INFO: Setting the data phase to 2 for uplink 14
10:49:42:setup_element:INFO: Setting the data phase to 8 for uplink 15
10:49:42:setup_element:INFO: Setting the data phase to 36 for uplink 16
10:49:42:setup_element:INFO: Setting the data phase to 39 for uplink 17
10:49:42:setup_element:INFO: Setting the data phase to 36 for uplink 18
10:49:42:setup_element:INFO: Setting the data phase to 38 for uplink 19
10:49:42:setup_element:INFO: Setting the data phase to 35 for uplink 20
10:49:42:setup_element:INFO: Setting the data phase to 36 for uplink 21
10:49:42:setup_element:INFO: Setting the data phase to 36 for uplink 22
10:49:42:setup_element:INFO: Setting the data phase to 34 for uplink 23
10:49:42:setup_element:INFO: Setting the data phase to 8 for uplink 24
10:49:42:setup_element:INFO: Setting the data phase to 0 for uplink 25
10:49:42:setup_element:INFO: Setting the data phase to 33 for uplink 26
10:49:42:setup_element:INFO: Setting the data phase to 39 for uplink 27
10:49:42:setup_element:INFO: Setting the data phase to 35 for uplink 28
10:49:42:setup_element:INFO: Setting the data phase to 0 for uplink 29
10:49:42:setup_element:INFO: Setting the data phase to 37 for uplink 30
10:49:42:setup_element:INFO: Setting the data phase to 0 for uplink 31
10:49:42:setup_element:INFO: Setting the data phase to 9 for uplink 32
10:49:42:setup_element:INFO: Setting the data phase to 1 for uplink 33
10:49:42:setup_element:INFO: Setting the data phase to 9 for uplink 34
10:49:42:setup_element:INFO: Setting the data phase to 0 for uplink 35
10:49:42:setup_element:INFO: Setting the data phase to 7 for uplink 36
10:49:42:setup_element:INFO: Setting the data phase to 39 for uplink 37
10:49:42:setup_element:INFO: Setting the data phase to 8 for uplink 38
10:49:42:setup_element:INFO: Setting the data phase to 1 for uplink 39
10:49:42:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 49
Window Length: 73
Eye Windows:
Uplink 0: _______XXXXXX___________________________________________________________________
Uplink 1: _______XXXXX____________________________________________________________________
Uplink 2: _______XXXXXX___________________________________________________________________
Uplink 3: _______XXXXX____________________________________________________________________
Uplink 4: _______XXXXXX___________________________________________________________________
Uplink 5: _______XXXXX____________________________________________________________________
Uplink 6: _______XXXXXX___________________________________________________________________
Uplink 7: _______XXXXX____________________________________________________________________
Uplink 8: ______XXXXXX____________________________________________________________________
Uplink 9: ______XXXXXX____________________________________________________________________
Uplink 10: ______XXXXXX____________________________________________________________________
Uplink 11: ______XXXXXX____________________________________________________________________
Uplink 12: ______XXXXXX____________________________________________________________________
Uplink 13: ______XXXXXX____________________________________________________________________
Uplink 14: _______XXXXXX___________________________________________________________________
Uplink 15: _______XXXXX____________________________________________________________________
Uplink 16: ______XXXXXXX___________________________________________________________________
Uplink 17: ________XXXXX___________________________________________________________________
Uplink 18: ______XXXXXXX___________________________________________________________________
Uplink 19: ________XXXXX___________________________________________________________________
Uplink 20: ______XXXXXX____________________________________________________________________
Uplink 21: ______XXXXXX____________________________________________________________________
Uplink 22: ______XXXXXX____________________________________________________________________
Uplink 23: ______XXXXXX____________________________________________________________________
Uplink 24: ______XXXXXX____________________________________________________________________
Uplink 25: ______XXXXX_____________________________________________________________________
Uplink 26: ______XXXXXXX___________________________________________________________________
Uplink 27: ________XXXXX___________________________________________________________________
Uplink 28: ______XXXXXXX___________________________________________________________________
Uplink 29: ________XXXXX___________________________________________________________________
Uplink 30: ______XXXXXXX___________________________________________________________________
Uplink 31: ________XXXXX___________________________________________________________________
Uplink 32: ______XXXXXX____________________________________________________________________
Uplink 33: ______XXXXX_____________________________________________________________________
Uplink 34: ______XXXXXX____________________________________________________________________
Uplink 35: ______XXXXX_____________________________________________________________________
Uplink 36: ______XXXXXX____________________________________________________________________
Uplink 37: ______XXXXX_____________________________________________________________________
Uplink 38: ______XXXXXX____________________________________________________________________
Uplink 39: ______XXXXX_____________________________________________________________________
Data phase characteristics:
Uplink 0:
Optimal Phase: 4
Window Length: 36
Eye Window: _______________________XXXX_____________
Uplink 1:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 2:
Optimal Phase: 3
Window Length: 34
Eye Window: _____________________XXXXXX_____________
Uplink 3:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 4:
Optimal Phase: 4
Window Length: 34
Eye Window: ______________________X_XXXX____________
Uplink 5:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 6:
Optimal Phase: 1
Window Length: 34
Eye Window: ___________________X_XXXX_______________
Uplink 7:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 8:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 9:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 10:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 11:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 12:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 13:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 14:
Optimal Phase: 2
Window Length: 35
Eye Window: ____________________XXXXX_______________
Uplink 15:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 16:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 17:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
Uplink 18:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 19:
Optimal Phase: 38
Window Length: 35
Eye Window: ________________XXXXX___________________
Uplink 20:
Optimal Phase: 35
Window Length: 36
Eye Window: ______________XXXX______________________
Uplink 21:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 22:
Optimal Phase: 36
Window Length: 36
Eye Window: _______________XXXX_____________________
Uplink 23:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 24:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 25:
Optimal Phase: 0
Window Length: 35
Eye Window: __________________XXXXX_________________
Uplink 26:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 27:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
Uplink 28:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 29:
Optimal Phase: 0
Window Length: 35
Eye Window: __________________XXXXX_________________
Uplink 30:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 31:
Optimal Phase: 0
Window Length: 36
Eye Window: ___________________XXXX_________________
Uplink 32:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 33:
Optimal Phase: 1
Window Length: 35
Eye Window: ___________________XXXXX________________
Uplink 34:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 35:
Optimal Phase: 0
Window Length: 36
Eye Window: ___________________XXXX_________________
Uplink 36:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 37:
Optimal Phase: 39
Window Length: 36
Eye Window: __________________XXXX__________________
Uplink 38:
Optimal Phase: 8
Window Length: 36
Eye Window: ___________________________XXXX_________
Uplink 39:
Optimal Phase: 1
Window Length: 35
Eye Window: ___________________XXXXX________________
]
10:49:42:setup_element:INFO: Beginning SMX ASICs map scan
10:49:42:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:49:42:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:49:42:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
10:49:42:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
10:49:42:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39]
10:49:42:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 15
10:49:42:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 1
10:49:42:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 2, uplink 3
10:49:42:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 3, uplink 5
10:49:42:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 4, uplink 7
10:49:42:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 11
10:49:42:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 13
10:49:42:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 2, uplink 21
10:49:42:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 3, uplink 23
10:49:42:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 4, uplink 9
10:49:42:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 24
10:49:42:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 38
10:49:42:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 2, uplink 36
10:49:42:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 3, uplink 34
10:49:42:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 4, uplink 32
10:49:42:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
10:49:42:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 26
10:49:42:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 2, uplink 18
10:49:42:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 3, uplink 16
10:49:42:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 4, uplink 30
10:49:42:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 14
10:49:42:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 0
10:49:43:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 2, uplink 2
10:49:43:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 3, uplink 4
10:49:43:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 4, uplink 6
10:49:43:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 10
10:49:43:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 12
10:49:43:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 2, uplink 20
10:49:43:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 3, uplink 22
10:49:43:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 4, uplink 8
10:49:43:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 25
10:49:43:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 39
10:49:43:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 2, uplink 37
10:49:43:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 3, uplink 35
10:49:43:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 4, uplink 33
10:49:43:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 29
10:49:43:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 27
10:49:43:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 2, uplink 19
10:49:43:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 3, uplink 17
10:49:43:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 4, uplink 31
10:49:44:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 15), (1, 1), (2, 3), (3, 5), (4, 7)
ASIC address 0x1: (ASIC uplink, uplink): (0, 11), (1, 13), (2, 21), (3, 23), (4, 9)
ASIC address 0x2: (ASIC uplink, uplink): (0, 24), (1, 38), (2, 36), (3, 34), (4, 32)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 26), (2, 18), (3, 16), (4, 30)
ASIC address 0x4: (ASIC uplink, uplink): (0, 14), (1, 0), (2, 2), (3, 4), (4, 6)
ASIC address 0x5: (ASIC uplink, uplink): (0, 10), (1, 12), (2, 20), (3, 22), (4, 8)
ASIC address 0x6: (ASIC uplink, uplink): (0, 25), (1, 39), (2, 37), (3, 35), (4, 33)
ASIC address 0x7: (ASIC uplink, uplink): (0, 29), (1, 27), (2, 19), (3, 17), (4, 31)
Clock Phase Characteristic:
Optimal Phase: 49
Window Length: 73
Eye Windows:
Uplink 0: _______XXXXXX___________________________________________________________________
Uplink 1: _______XXXXX____________________________________________________________________
Uplink 2: _______XXXXXX___________________________________________________________________
Uplink 3: _______XXXXX____________________________________________________________________
Uplink 4: _______XXXXXX___________________________________________________________________
Uplink 5: _______XXXXX____________________________________________________________________
Uplink 6: _______XXXXXX___________________________________________________________________
Uplink 7: _______XXXXX____________________________________________________________________
Uplink 8: ______XXXXXX____________________________________________________________________
Uplink 9: ______XXXXXX____________________________________________________________________
Uplink 10: ______XXXXXX____________________________________________________________________
Uplink 11: ______XXXXXX____________________________________________________________________
Uplink 12: ______XXXXXX____________________________________________________________________
Uplink 13: ______XXXXXX____________________________________________________________________
Uplink 14: _______XXXXXX___________________________________________________________________
Uplink 15: _______XXXXX____________________________________________________________________
Uplink 16: ______XXXXXXX___________________________________________________________________
Uplink 17: ________XXXXX___________________________________________________________________
Uplink 18: ______XXXXXXX___________________________________________________________________
Uplink 19: ________XXXXX___________________________________________________________________
Uplink 20: ______XXXXXX____________________________________________________________________
Uplink 21: ______XXXXXX____________________________________________________________________
Uplink 22: ______XXXXXX____________________________________________________________________
Uplink 23: ______XXXXXX____________________________________________________________________
Uplink 24: ______XXXXXX____________________________________________________________________
Uplink 25: ______XXXXX_____________________________________________________________________
Uplink 26: ______XXXXXXX___________________________________________________________________
Uplink 27: ________XXXXX___________________________________________________________________
Uplink 28: ______XXXXXXX___________________________________________________________________
Uplink 29: ________XXXXX___________________________________________________________________
Uplink 30: ______XXXXXXX___________________________________________________________________
Uplink 31: ________XXXXX___________________________________________________________________
Uplink 32: ______XXXXXX____________________________________________________________________
Uplink 33: ______XXXXX_____________________________________________________________________
Uplink 34: ______XXXXXX____________________________________________________________________
Uplink 35: ______XXXXX_____________________________________________________________________
Uplink 36: ______XXXXXX____________________________________________________________________
Uplink 37: ______XXXXX_____________________________________________________________________
Uplink 38: ______XXXXXX____________________________________________________________________
Uplink 39: ______XXXXX_____________________________________________________________________
Data phase characteristics:
Uplink 0:
Optimal Phase: 4
Window Length: 36
Eye Window: _______________________XXXX_____________
Uplink 1:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 2:
Optimal Phase: 3
Window Length: 34
Eye Window: _____________________XXXXXX_____________
Uplink 3:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 4:
Optimal Phase: 4
Window Length: 34
Eye Window: ______________________X_XXXX____________
Uplink 5:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 6:
Optimal Phase: 1
Window Length: 34
Eye Window: ___________________X_XXXX_______________
Uplink 7:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 8:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 9:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 10:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 11:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 12:
Optimal Phase: 31
Window Length: 35
Eye Window: _________XXXXX__________________________
Uplink 13:
Optimal Phase: 33
Window Length: 35
Eye Window: ___________XXXXX________________________
Uplink 14:
Optimal Phase: 2
Window Length: 35
Eye Window: ____________________XXXXX_______________
Uplink 15:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 16:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 17:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
Uplink 18:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 19:
Optimal Phase: 38
Window Length: 35
Eye Window: ________________XXXXX___________________
Uplink 20:
Optimal Phase: 35
Window Length: 36
Eye Window: ______________XXXX______________________
Uplink 21:
Optimal Phase: 36
Window Length: 35
Eye Window: ______________XXXXX_____________________
Uplink 22:
Optimal Phase: 36
Window Length: 36
Eye Window: _______________XXXX_____________________
Uplink 23:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 24:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 25:
Optimal Phase: 0
Window Length: 35
Eye Window: __________________XXXXX_________________
Uplink 26:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 27:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
Uplink 28:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 29:
Optimal Phase: 0
Window Length: 35
Eye Window: __________________XXXXX_________________
Uplink 30:
Optimal Phase: 37
Window Length: 34
Eye Window: _______________XXXXXX___________________
Uplink 31:
Optimal Phase: 0
Window Length: 36
Eye Window: ___________________XXXX_________________
Uplink 32:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 33:
Optimal Phase: 1
Window Length: 35
Eye Window: ___________________XXXXX________________
Uplink 34:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 35:
Optimal Phase: 0
Window Length: 36
Eye Window: ___________________XXXX_________________
Uplink 36:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 37:
Optimal Phase: 39
Window Length: 36
Eye Window: __________________XXXX__________________
Uplink 38:
Optimal Phase: 8
Window Length: 36
Eye Window: ___________________________XXXX_________
Uplink 39:
Optimal Phase: 1
Window Length: 35
Eye Window: ___________________XXXXX________________
10:49:44:setup_element:INFO: Performing Elink synchronization
10:49:44:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:49:44:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:49:44:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
10:49:44:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
10:49:44:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
10:49:44:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39]
10:49:45:ST3_emu:INFO: Number of chips: 8
10:49:45:ST3_emu:INFO: Chip address: 0x0
10:49:45:ST3_emu:INFO: Chip address: 0x1
10:49:45:ST3_emu:INFO: Chip address: 0x2
10:49:45:ST3_emu:INFO: Chip address: 0x3
10:49:45:ST3_emu:INFO: Chip address: 0x4
10:49:45:ST3_emu:INFO: Chip address: 0x5
10:49:45:ST3_emu:INFO: Chip address: 0x6
10:49:45:ST3_emu:INFO: Chip address: 0x7
10:49:45:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:49:45:febtest:INFO: 0-0 | XA-000-08-002-000-002-171-09 | 21.9 | 1224.5
10:49:46:febtest:INFO: 0-1 | XA-000-08-002-000-003-056-09 | 31.4 | 1201.0
10:49:46:febtest:INFO: 0-2 | XA-000-08-002-000-003-141-10 | 34.6 | 1195.1
10:49:46:febtest:INFO: 0-3 | XA-000-08-002-000-006-131-01 | 40.9 | 1159.7
10:49:46:febtest:INFO: 0-4 | XA-000-08-002-000-003-075-05 | 34.6 | 1189.2
10:49:46:febtest:INFO: 0-5 | XA-000-08-002-002-007-137-05 | 31.4 | 1201.0
10:49:47:febtest:INFO: 0-6 | XA-000-08-002-000-002-209-05 | 37.7 | 1171.5
10:49:47:febtest:INFO: 0-7 | XA-000-08-002-000-006-086-09 | 31.4 | 1195.1
10:49:47:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:49:51:ST3_smx:INFO: chip: 0-0 31.389742 C 1171.483840 mV
10:49:51:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:49:51:ST3_smx:INFO: Electrons
10:49:51:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:49:53:ST3_smx:INFO: ----> Checking Analog response
10:49:53:ST3_smx:INFO: ----> Checking broken channels
10:49:53:ST3_smx:INFO: Total # broken ch: 0
10:49:53:ST3_smx:INFO: List FAST: []
10:49:53:ST3_smx:INFO: List SLOW: []
10:49:53:ST3_smx:INFO: Holes
10:49:53:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:49:55:ST3_smx:INFO: ----> Checking Analog response
10:49:55:ST3_smx:INFO: ----> Checking broken channels
10:49:55:ST3_smx:INFO: Total # broken ch: 0
10:49:55:ST3_smx:INFO: List FAST: []
10:49:55:ST3_smx:INFO: List SLOW: []
10:49:55:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:49:55:febtest:INFO: 0-0 | XA-000-08-002-000-002-171-09 | 34.6 | 1171.5
10:49:56:febtest:INFO: 0-1 | XA-000-08-002-000-003-056-09 | 31.4 | 1195.1
10:49:56:febtest:INFO: 0-2 | XA-000-08-002-000-003-141-10 | 34.6 | 1195.1
10:49:56:febtest:INFO: 0-3 | XA-000-08-002-000-006-131-01 | 40.9 | 1159.7
10:49:56:febtest:INFO: 0-4 | XA-000-08-002-000-003-075-05 | 34.6 | 1189.2
10:49:56:febtest:INFO: 0-5 | XA-000-08-002-002-007-137-05 | 31.4 | 1201.0
10:49:57:febtest:INFO: 0-6 | XA-000-08-002-000-002-209-05 | 37.7 | 1171.5
10:49:57:febtest:INFO: 0-7 | XA-000-08-002-000-006-086-09 | 31.4 | 1195.1
10:49:57:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:50:01:ST3_smx:INFO: chip: 0-1 37.726682 C 1159.654860 mV
10:50:01:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:50:01:ST3_smx:INFO: Electrons
10:50:01:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:50:03:ST3_smx:INFO: ----> Checking Analog response
10:50:03:ST3_smx:INFO: ----> Checking broken channels
10:50:03:ST3_smx:INFO: Total # broken ch: 0
10:50:03:ST3_smx:INFO: List FAST: []
10:50:03:ST3_smx:INFO: List SLOW: []
10:50:03:ST3_smx:INFO: Holes
10:50:03:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:50:05:ST3_smx:INFO: ----> Checking Analog response
10:50:05:ST3_smx:INFO: ----> Checking broken channels
10:50:05:ST3_smx:INFO: Total # broken ch: 0
10:50:05:ST3_smx:INFO: List FAST: []
10:50:05:ST3_smx:INFO: List SLOW: []
10:50:05:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:50:06:febtest:INFO: 0-0 | XA-000-08-002-000-002-171-09 | 34.6 | 1171.5
10:50:06:febtest:INFO: 0-1 | XA-000-08-002-000-003-056-09 | 40.9 | 1153.7
10:50:06:febtest:INFO: 0-2 | XA-000-08-002-000-003-141-10 | 34.6 | 1195.1
10:50:06:febtest:INFO: 0-3 | XA-000-08-002-000-006-131-01 | 40.9 | 1159.7
10:50:07:febtest:INFO: 0-4 | XA-000-08-002-000-003-075-05 | 34.6 | 1189.2
10:50:07:febtest:INFO: 0-5 | XA-000-08-002-002-007-137-05 | 31.4 | 1201.0
10:50:07:febtest:INFO: 0-6 | XA-000-08-002-000-002-209-05 | 37.7 | 1171.5
10:50:07:febtest:INFO: 0-7 | XA-000-08-002-000-006-086-09 | 31.4 | 1195.1
10:50:07:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:50:11:ST3_smx:INFO: chip: 0-2 37.726682 C 1171.483840 mV
10:50:11:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:50:11:ST3_smx:INFO: Electrons
10:50:11:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:50:13:ST3_smx:INFO: ----> Checking Analog response
10:50:13:ST3_smx:INFO: ----> Checking broken channels
10:50:13:ST3_smx:INFO: Total # broken ch: 0
10:50:13:ST3_smx:INFO: List FAST: []
10:50:13:ST3_smx:INFO: List SLOW: []
10:50:13:ST3_smx:INFO: Holes
10:50:13:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:50:15:ST3_smx:INFO: ----> Checking Analog response
10:50:15:ST3_smx:INFO: ----> Checking broken channels
10:50:16:ST3_smx:INFO: Total # broken ch: 0
10:50:16:ST3_smx:INFO: List FAST: []
10:50:16:ST3_smx:INFO: List SLOW: []
10:50:16:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:50:16:febtest:INFO: 0-0 | XA-000-08-002-000-002-171-09 | 34.6 | 1171.5
10:50:16:febtest:INFO: 0-1 | XA-000-08-002-000-003-056-09 | 40.9 | 1159.7
10:50:16:febtest:INFO: 0-2 | XA-000-08-002-000-003-141-10 | 40.9 | 1171.5
10:50:17:febtest:INFO: 0-3 | XA-000-08-002-000-006-131-01 | 44.1 | 1159.7
10:50:17:febtest:INFO: 0-4 | XA-000-08-002-000-003-075-05 | 34.6 | 1189.2
10:50:17:febtest:INFO: 0-5 | XA-000-08-002-002-007-137-05 | 31.4 | 1201.0
10:50:17:febtest:INFO: 0-6 | XA-000-08-002-000-002-209-05 | 37.7 | 1171.5
10:50:17:febtest:INFO: 0-7 | XA-000-08-002-000-006-086-09 | 31.4 | 1195.1
10:50:18:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:50:21:ST3_smx:INFO: chip: 0-3 44.073563 C 1147.806000 mV
10:50:21:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:50:21:ST3_smx:INFO: Electrons
10:50:21:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:50:23:ST3_smx:INFO: ----> Checking Analog response
10:50:23:ST3_smx:INFO: ----> Checking broken channels
10:50:24:ST3_smx:INFO: Total # broken ch: 5
10:50:24:ST3_smx:INFO: List FAST: [69, 88, 92, 122, 127]
10:50:24:ST3_smx:INFO: List SLOW: []
10:50:24:ST3_smx:INFO: Holes
10:50:24:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:50:26:ST3_smx:INFO: ----> Checking Analog response
10:50:26:ST3_smx:INFO: ----> Checking broken channels
10:50:26:ST3_smx:INFO: Total # broken ch: 5
10:50:26:ST3_smx:INFO: List FAST: [69, 88, 92, 122, 127]
10:50:26:ST3_smx:INFO: List SLOW: []
10:50:26:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:50:26:febtest:INFO: 0-0 | XA-000-08-002-000-002-171-09 | 34.6 | 1165.6
10:50:27:febtest:INFO: 0-1 | XA-000-08-002-000-003-056-09 | 40.9 | 1153.7
10:50:27:febtest:INFO: 0-2 | XA-000-08-002-000-003-141-10 | 37.7 | 1171.5
10:50:27:febtest:INFO: 0-3 | XA-000-08-002-000-006-131-01 | 44.1 | 1141.9
10:50:27:febtest:INFO: 0-4 | XA-000-08-002-000-003-075-05 | 34.6 | 1189.2
10:50:28:febtest:INFO: 0-5 | XA-000-08-002-002-007-137-05 | 31.4 | 1201.0
10:50:28:febtest:INFO: 0-6 | XA-000-08-002-000-002-209-05 | 37.7 | 1171.5
10:50:28:febtest:INFO: 0-7 | XA-000-08-002-000-006-086-09 | 31.4 | 1195.1
10:50:28:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:50:32:ST3_smx:INFO: chip: 0-4 37.726682 C 1165.571835 mV
10:50:32:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:50:32:ST3_smx:INFO: Electrons
10:50:32:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:50:34:ST3_smx:INFO: ----> Checking Analog response
10:50:34:ST3_smx:INFO: ----> Checking broken channels
10:50:34:ST3_smx:INFO: Total # broken ch: 0
10:50:34:ST3_smx:INFO: List FAST: []
10:50:34:ST3_smx:INFO: List SLOW: []
10:50:34:ST3_smx:INFO: Holes
10:50:34:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:50:36:ST3_smx:INFO: ----> Checking Analog response
10:50:36:ST3_smx:INFO: ----> Checking broken channels
10:50:37:ST3_smx:INFO: Total # broken ch: 0
10:50:37:ST3_smx:INFO: List FAST: []
10:50:37:ST3_smx:INFO: List SLOW: []
10:50:37:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:50:37:febtest:INFO: 0-0 | XA-000-08-002-000-002-171-09 | 34.6 | 1165.6
10:50:37:febtest:INFO: 0-1 | XA-000-08-002-000-003-056-09 | 40.9 | 1159.7
10:50:37:febtest:INFO: 0-2 | XA-000-08-002-000-003-141-10 | 40.9 | 1165.6
10:50:37:febtest:INFO: 0-3 | XA-000-08-002-000-006-131-01 | 44.1 | 1141.9
10:50:38:febtest:INFO: 0-4 | XA-000-08-002-000-003-075-05 | 37.7 | 1159.7
10:50:38:febtest:INFO: 0-5 | XA-000-08-002-002-007-137-05 | 31.4 | 1201.0
10:50:38:febtest:INFO: 0-6 | XA-000-08-002-000-002-209-05 | 37.7 | 1171.5
10:50:38:febtest:INFO: 0-7 | XA-000-08-002-000-006-086-09 | 31.4 | 1195.1
10:50:39:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:50:42:ST3_smx:INFO: chip: 0-5 40.898880 C 1165.571835 mV
10:50:42:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:50:42:ST3_smx:INFO: Electrons
10:50:42:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:50:44:ST3_smx:INFO: ----> Checking Analog response
10:50:44:ST3_smx:INFO: ----> Checking broken channels
10:50:45:ST3_smx:INFO: Total # broken ch: 2
10:50:45:ST3_smx:INFO: List FAST: [86, 95]
10:50:45:ST3_smx:INFO: List SLOW: []
10:50:45:ST3_smx:INFO: Holes
10:50:45:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:50:47:ST3_smx:INFO: ----> Checking Analog response
10:50:47:ST3_smx:INFO: ----> Checking broken channels
10:50:47:ST3_smx:INFO: Total # broken ch: 2
10:50:47:ST3_smx:INFO: List FAST: [86, 95]
10:50:47:ST3_smx:INFO: List SLOW: []
10:50:47:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:50:47:febtest:INFO: 0-0 | XA-000-08-002-000-002-171-09 | 37.7 | 1165.6
10:50:47:febtest:INFO: 0-1 | XA-000-08-002-000-003-056-09 | 40.9 | 1153.7
10:50:48:febtest:INFO: 0-2 | XA-000-08-002-000-003-141-10 | 40.9 | 1165.6
10:50:48:febtest:INFO: 0-3 | XA-000-08-002-000-006-131-01 | 44.1 | 1141.9
10:50:48:febtest:INFO: 0-4 | XA-000-08-002-000-003-075-05 | 40.9 | 1159.7
10:50:48:febtest:INFO: 0-5 | XA-000-08-002-002-007-137-05 | 40.9 | 1159.7
10:50:48:febtest:INFO: 0-6 | XA-000-08-002-000-002-209-05 | 40.9 | 1171.5
10:50:49:febtest:INFO: 0-7 | XA-000-08-002-000-006-086-09 | 31.4 | 1195.1
10:50:49:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:50:53:ST3_smx:INFO: chip: 0-6 37.726682 C 1171.483840 mV
10:50:53:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:50:53:ST3_smx:INFO: Electrons
10:50:53:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:50:55:ST3_smx:INFO: ----> Checking Analog response
10:50:55:ST3_smx:INFO: ----> Checking broken channels
10:50:55:ST3_smx:INFO: Total # broken ch: 0
10:50:55:ST3_smx:INFO: List FAST: []
10:50:55:ST3_smx:INFO: List SLOW: []
10:50:55:ST3_smx:INFO: Holes
10:50:55:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:50:57:ST3_smx:INFO: ----> Checking Analog response
10:50:57:ST3_smx:INFO: ----> Checking broken channels
10:50:57:ST3_smx:INFO: Total # broken ch: 0
10:50:57:ST3_smx:INFO: List FAST: []
10:50:57:ST3_smx:INFO: List SLOW: []
10:50:57:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:50:57:febtest:INFO: 0-0 | XA-000-08-002-000-002-171-09 | 37.7 | 1165.6
10:50:57:febtest:INFO: 0-1 | XA-000-08-002-000-003-056-09 | 40.9 | 1153.7
10:50:58:febtest:INFO: 0-2 | XA-000-08-002-000-003-141-10 | 40.9 | 1165.6
10:50:58:febtest:INFO: 0-3 | XA-000-08-002-000-006-131-01 | 47.3 | 1141.9
10:50:58:febtest:INFO: 0-4 | XA-000-08-002-000-003-075-05 | 40.9 | 1159.7
10:50:58:febtest:INFO: 0-5 | XA-000-08-002-002-007-137-05 | 44.1 | 1159.7
10:50:59:febtest:INFO: 0-6 | XA-000-08-002-000-002-209-05 | 40.9 | 1165.6
10:50:59:febtest:INFO: 0-7 | XA-000-08-002-000-006-086-09 | 31.4 | 1195.1
10:50:59:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:51:03:ST3_smx:INFO: chip: 0-7 34.556970 C 1177.390875 mV
10:51:03:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:51:03:ST3_smx:INFO: Electrons
10:51:03:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:51:05:ST3_smx:INFO: ----> Checking Analog response
10:51:05:ST3_smx:INFO: ----> Checking broken channels
10:51:05:ST3_smx:INFO: Total # broken ch: 2
10:51:05:ST3_smx:INFO: List FAST: [19, 76]
10:51:05:ST3_smx:INFO: List SLOW: []
10:51:05:ST3_smx:INFO: Holes
10:51:05:ST3_smx:INFO: Injected pulses: 125LSB, amp_cal 7.000000 fC
10:51:07:ST3_smx:INFO: ----> Checking Analog response
10:51:07:ST3_smx:INFO: ----> Checking broken channels
10:51:07:ST3_smx:INFO: Total # broken ch: 2
10:51:07:ST3_smx:INFO: List FAST: [19, 76]
10:51:07:ST3_smx:INFO: List SLOW: []
10:51:07:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:51:08:febtest:INFO: 0-0 | XA-000-08-002-000-002-171-09 | 37.7 | 1165.6
10:51:08:febtest:INFO: 0-1 | XA-000-08-002-000-003-056-09 | 40.9 | 1153.7
10:51:08:febtest:INFO: 0-2 | XA-000-08-002-000-003-141-10 | 40.9 | 1165.6
10:51:08:febtest:INFO: 0-3 | XA-000-08-002-000-006-131-01 | 47.3 | 1141.9
10:51:08:febtest:INFO: 0-4 | XA-000-08-002-000-003-075-05 | 40.9 | 1159.7
10:51:09:febtest:INFO: 0-5 | XA-000-08-002-002-007-137-05 | 44.1 | 1159.7
10:51:09:febtest:INFO: 0-6 | XA-000-08-002-000-002-209-05 | 37.7 | 1165.6
10:51:09:febtest:INFO: 0-7 | XA-000-08-002-000-006-086-09 | 37.7 | 1171.5
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_10-10_49_32', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-006-086-09', 'FUSED_ID': 6359364699116561769, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 2, 'N_BROKEN_FAST': '[19, 76]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 2, 'P_BROKEN_FAST': '[19, 76]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.447', '2.0010', '1.846', '2.7710', '7.000', '1.5680', '7.000', '1.5680'], 'VI_aInit': ['2.450', '2.2150', '1.850', '1.4630', '7.000', '1.5420', '7.000', '1.5420'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 125, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
10:51:16:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_5009/TestDate_2023_11_10-10_49_32/