Go Back
FEB_5013 02.08.23 11:19:37
Info
11:19:33:smx_tester:INFO: Setting Elink clock mode to 160 MHz
11:19:33:ST3_emu:ERROR: device described in file: ../ST3_BASE/config/feb8_5_devices.xml not found!!!
11:19:35:smx_tester:INFO: Setting Elink clock mode to 160 MHz
11:19:37:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:19:37:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
11:19:37:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
11:19:37:febtest:INFO: Tsting FEB with SN 5013
11:19:39:smx_tester:INFO: Scanning setup
11:19:39:elinks:INFO: Disabling clock on downlink 0
11:19:39:elinks:INFO: Disabling clock on downlink 1
11:19:39:elinks:INFO: Disabling clock on downlink 2
11:19:39:elinks:INFO: Disabling clock on downlink 3
11:19:39:elinks:INFO: Disabling clock on downlink 4
11:19:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:19:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
11:19:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:19:39:elinks:INFO: Disabling clock on downlink 0
11:19:39:elinks:INFO: Disabling clock on downlink 1
11:19:39:elinks:INFO: Disabling clock on downlink 2
11:19:39:elinks:INFO: Disabling clock on downlink 3
11:19:39:elinks:INFO: Disabling clock on downlink 4
11:19:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:19:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
11:19:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:19:39:elinks:INFO: Disabling clock on downlink 0
11:19:39:elinks:INFO: Disabling clock on downlink 1
11:19:39:elinks:INFO: Disabling clock on downlink 2
11:19:39:elinks:INFO: Disabling clock on downlink 3
11:19:39:elinks:INFO: Disabling clock on downlink 4
11:19:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:19:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 8
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 9
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 10
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 11
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 12
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 13
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
11:19:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
11:19:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:19:39:elinks:INFO: Disabling clock on downlink 0
11:19:39:elinks:INFO: Disabling clock on downlink 1
11:19:39:elinks:INFO: Disabling clock on downlink 2
11:19:39:elinks:INFO: Disabling clock on downlink 3
11:19:39:elinks:INFO: Disabling clock on downlink 4
11:19:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:19:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
11:19:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:19:39:elinks:INFO: Disabling clock on downlink 0
11:19:39:elinks:INFO: Disabling clock on downlink 1
11:19:39:elinks:INFO: Disabling clock on downlink 2
11:19:39:elinks:INFO: Disabling clock on downlink 3
11:19:39:elinks:INFO: Disabling clock on downlink 4
11:19:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
11:19:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
11:19:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
11:19:39:setup_element:INFO: Scanning clock phase
11:19:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:19:40:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:19:40:setup_element:INFO: Clock phase scan results for group 0, downlink 2
11:19:40:setup_element:INFO: Eye window for uplink 8 : ______XXXXXX____________________________________________________________________
Clock Delay: 48
11:19:40:setup_element:INFO: Eye window for uplink 9 : ______XXXXXX____________________________________________________________________
Clock Delay: 48
11:19:40:setup_element:INFO: Eye window for uplink 10: ______XXXXXX____________________________________________________________________
Clock Delay: 48
11:19:40:setup_element:INFO: Eye window for uplink 11: ______XXXXXX____________________________________________________________________
Clock Delay: 48
11:19:40:setup_element:INFO: Eye window for uplink 12: ______XXXXXX____________________________________________________________________
Clock Delay: 48
11:19:40:setup_element:INFO: Eye window for uplink 13: ______XXXXXX____________________________________________________________________
Clock Delay: 48
11:19:40:setup_element:INFO: Eye window for uplink 16: _____XXXXXX_____________________________________________________________________
Clock Delay: 47
11:19:40:setup_element:INFO: Eye window for uplink 17: ______XXXXX_____________________________________________________________________
Clock Delay: 48
11:19:40:setup_element:INFO: Eye window for uplink 18: _____XXXXXX_____________________________________________________________________
Clock Delay: 47
11:19:40:setup_element:INFO: Eye window for uplink 19: ______XXXXX_____________________________________________________________________
Clock Delay: 48
11:19:40:setup_element:INFO: Eye window for uplink 20: ______XXXXXX____________________________________________________________________
Clock Delay: 48
11:19:40:setup_element:INFO: Eye window for uplink 21: ______XXXXXX____________________________________________________________________
Clock Delay: 48
11:19:40:setup_element:INFO: Eye window for uplink 22: ______XXXXXX____________________________________________________________________
Clock Delay: 48
11:19:40:setup_element:INFO: Eye window for uplink 23: ______XXXXXX____________________________________________________________________
Clock Delay: 48
11:19:40:setup_element:INFO: Eye window for uplink 26: _____XXXXXX_____________________________________________________________________
Clock Delay: 47
11:19:40:setup_element:INFO: Eye window for uplink 27: ______XXXXX_____________________________________________________________________
Clock Delay: 48
11:19:40:setup_element:INFO: Eye window for uplink 28: _____XXXXXX_____________________________________________________________________
Clock Delay: 47
11:19:40:setup_element:INFO: Eye window for uplink 29: ______XXXXX_____________________________________________________________________
Clock Delay: 48
11:19:40:setup_element:INFO: Eye window for uplink 30: _____XXXXXX_____________________________________________________________________
Clock Delay: 47
11:19:40:setup_element:INFO: Eye window for uplink 31: ______XXXXX_____________________________________________________________________
Clock Delay: 48
11:19:40:setup_element:INFO: Setting the clock phase to 48 for group 0, downlink 2
11:19:40:setup_element:INFO: Scanning data phases
11:19:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:19:40:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:19:46:setup_element:INFO: Data phase scan results for group 0, downlink 2
11:19:46:setup_element:INFO: Eye window for uplink 8 : _____________XXXXXX_____________________
Data delay found: 35
11:19:46:setup_element:INFO: Eye window for uplink 9 : ________________XXXXXX__________________
Data delay found: 38
11:19:46:setup_element:INFO: Eye window for uplink 10: _____________XXXXX______________________
Data delay found: 35
11:19:46:setup_element:INFO: Eye window for uplink 11: ________________XXXXX___________________
Data delay found: 38
11:19:46:setup_element:INFO: Eye window for uplink 12: _______________XXXX_____________________
Data delay found: 36
11:19:46:setup_element:INFO: Eye window for uplink 13: ________________XXXXX___________________
Data delay found: 38
11:19:46:setup_element:INFO: Eye window for uplink 16: __________________XXXXX_________________
Data delay found: 0
11:19:46:setup_element:INFO: Eye window for uplink 17: ___________________XXXXX________________
Data delay found: 1
11:19:46:setup_element:INFO: Eye window for uplink 18: ___________________XXXX_________________
Data delay found: 0
11:19:46:setup_element:INFO: Eye window for uplink 19: _________________XXXXXX_________________
Data delay found: 39
11:19:46:setup_element:INFO: Eye window for uplink 20: ___________________XXXX_________________
Data delay found: 0
11:19:46:setup_element:INFO: Eye window for uplink 21: ___________________XXXXX________________
Data delay found: 1
11:19:46:setup_element:INFO: Eye window for uplink 22: ____________________XXXXX_______________
Data delay found: 2
11:19:46:setup_element:INFO: Eye window for uplink 23: _________________XXXXXX_________________
Data delay found: 39
11:19:46:setup_element:INFO: Eye window for uplink 26: ________________XXXXX___________________
Data delay found: 38
11:19:46:setup_element:INFO: Eye window for uplink 27: _________________XXXXXXX________________
Data delay found: 0
11:19:46:setup_element:INFO: Eye window for uplink 28: _________________XXXX___________________
Data delay found: 38
11:19:46:setup_element:INFO: Eye window for uplink 29: ___________________XXXXX________________
Data delay found: 1
11:19:46:setup_element:INFO: Eye window for uplink 30: ____________________XXXXX_______________
Data delay found: 2
11:19:46:setup_element:INFO: Eye window for uplink 31: ____________________XXXXX_______________
Data delay found: 2
11:19:46:setup_element:INFO: Setting the data phase to 35 for uplink 8
11:19:46:setup_element:INFO: Setting the data phase to 38 for uplink 9
11:19:46:setup_element:INFO: Setting the data phase to 35 for uplink 10
11:19:46:setup_element:INFO: Setting the data phase to 38 for uplink 11
11:19:46:setup_element:INFO: Setting the data phase to 36 for uplink 12
11:19:46:setup_element:INFO: Setting the data phase to 38 for uplink 13
11:19:46:setup_element:INFO: Setting the data phase to 0 for uplink 16
11:19:46:setup_element:INFO: Setting the data phase to 1 for uplink 17
11:19:46:setup_element:INFO: Setting the data phase to 0 for uplink 18
11:19:46:setup_element:INFO: Setting the data phase to 39 for uplink 19
11:19:46:setup_element:INFO: Setting the data phase to 0 for uplink 20
11:19:46:setup_element:INFO: Setting the data phase to 1 for uplink 21
11:19:46:setup_element:INFO: Setting the data phase to 2 for uplink 22
11:19:46:setup_element:INFO: Setting the data phase to 39 for uplink 23
11:19:46:setup_element:INFO: Setting the data phase to 38 for uplink 26
11:19:46:setup_element:INFO: Setting the data phase to 0 for uplink 27
11:19:46:setup_element:INFO: Setting the data phase to 38 for uplink 28
11:19:46:setup_element:INFO: Setting the data phase to 1 for uplink 29
11:19:46:setup_element:INFO: Setting the data phase to 2 for uplink 30
11:19:46:setup_element:INFO: Setting the data phase to 2 for uplink 31
11:19:46:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [8, 9, 10, 11, 12, 13, 16, 17, 18, 19, 20, 21, 22, 23, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 48
Window Length: 73
Eye Windows:
Uplink 8: ______XXXXXX____________________________________________________________________
Uplink 9: ______XXXXXX____________________________________________________________________
Uplink 10: ______XXXXXX____________________________________________________________________
Uplink 11: ______XXXXXX____________________________________________________________________
Uplink 12: ______XXXXXX____________________________________________________________________
Uplink 13: ______XXXXXX____________________________________________________________________
Uplink 16: _____XXXXXX_____________________________________________________________________
Uplink 17: ______XXXXX_____________________________________________________________________
Uplink 18: _____XXXXXX_____________________________________________________________________
Uplink 19: ______XXXXX_____________________________________________________________________
Uplink 20: ______XXXXXX____________________________________________________________________
Uplink 21: ______XXXXXX____________________________________________________________________
Uplink 22: ______XXXXXX____________________________________________________________________
Uplink 23: ______XXXXXX____________________________________________________________________
Uplink 26: _____XXXXXX_____________________________________________________________________
Uplink 27: ______XXXXX_____________________________________________________________________
Uplink 28: _____XXXXXX_____________________________________________________________________
Uplink 29: ______XXXXX_____________________________________________________________________
Uplink 30: _____XXXXXX_____________________________________________________________________
Uplink 31: ______XXXXX_____________________________________________________________________
Data phase characteristics:
Uplink 8:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 9:
Optimal Phase: 38
Window Length: 34
Eye Window: ________________XXXXXX__________________
Uplink 10:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 11:
Optimal Phase: 38
Window Length: 35
Eye Window: ________________XXXXX___________________
Uplink 12:
Optimal Phase: 36
Window Length: 36
Eye Window: _______________XXXX_____________________
Uplink 13:
Optimal Phase: 38
Window Length: 35
Eye Window: ________________XXXXX___________________
Uplink 16:
Optimal Phase: 0
Window Length: 35
Eye Window: __________________XXXXX_________________
Uplink 17:
Optimal Phase: 1
Window Length: 35
Eye Window: ___________________XXXXX________________
Uplink 18:
Optimal Phase: 0
Window Length: 36
Eye Window: ___________________XXXX_________________
Uplink 19:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
Uplink 20:
Optimal Phase: 0
Window Length: 36
Eye Window: ___________________XXXX_________________
Uplink 21:
Optimal Phase: 1
Window Length: 35
Eye Window: ___________________XXXXX________________
Uplink 22:
Optimal Phase: 2
Window Length: 35
Eye Window: ____________________XXXXX_______________
Uplink 23:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
Uplink 26:
Optimal Phase: 38
Window Length: 35
Eye Window: ________________XXXXX___________________
Uplink 27:
Optimal Phase: 0
Window Length: 33
Eye Window: _________________XXXXXXX________________
Uplink 28:
Optimal Phase: 38
Window Length: 36
Eye Window: _________________XXXX___________________
Uplink 29:
Optimal Phase: 1
Window Length: 35
Eye Window: ___________________XXXXX________________
Uplink 30:
Optimal Phase: 2
Window Length: 35
Eye Window: ____________________XXXXX_______________
Uplink 31:
Optimal Phase: 2
Window Length: 35
Eye Window: ____________________XXXXX_______________
]
11:19:46:setup_element:INFO: Beginning SMX ASICs map scan
11:19:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:19:46:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:19:46:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
11:19:46:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
11:19:46:uplink:INFO: Setting uplinks mask [8, 9, 10, 11, 12, 13, 16, 17, 18, 19, 20, 21, 22, 23, 26, 27, 28, 29, 30, 31]
11:19:46:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 11
11:19:46:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 13
11:19:46:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 2, uplink 21
11:19:46:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 3, uplink 23
11:19:46:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 4, uplink 9
11:19:46:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
11:19:47:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 26
11:19:47:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 2, uplink 18
11:19:47:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 3, uplink 16
11:19:47:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 4, uplink 30
11:19:47:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 10
11:19:47:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 12
11:19:47:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 2, uplink 20
11:19:47:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 3, uplink 22
11:19:47:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 4, uplink 8
11:19:47:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 29
11:19:47:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 27
11:19:47:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 2, uplink 19
11:19:47:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 3, uplink 17
11:19:47:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 4, uplink 31
11:19:49:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [8, 9, 10, 11, 12, 13, 16, 17, 18, 19, 20, 21, 22, 23, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x1: (ASIC uplink, uplink): (0, 11), (1, 13), (2, 21), (3, 23), (4, 9)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 26), (2, 18), (3, 16), (4, 30)
ASIC address 0x5: (ASIC uplink, uplink): (0, 10), (1, 12), (2, 20), (3, 22), (4, 8)
ASIC address 0x7: (ASIC uplink, uplink): (0, 29), (1, 27), (2, 19), (3, 17), (4, 31)
Clock Phase Characteristic:
Optimal Phase: 48
Window Length: 73
Eye Windows:
Uplink 8: ______XXXXXX____________________________________________________________________
Uplink 9: ______XXXXXX____________________________________________________________________
Uplink 10: ______XXXXXX____________________________________________________________________
Uplink 11: ______XXXXXX____________________________________________________________________
Uplink 12: ______XXXXXX____________________________________________________________________
Uplink 13: ______XXXXXX____________________________________________________________________
Uplink 16: _____XXXXXX_____________________________________________________________________
Uplink 17: ______XXXXX_____________________________________________________________________
Uplink 18: _____XXXXXX_____________________________________________________________________
Uplink 19: ______XXXXX_____________________________________________________________________
Uplink 20: ______XXXXXX____________________________________________________________________
Uplink 21: ______XXXXXX____________________________________________________________________
Uplink 22: ______XXXXXX____________________________________________________________________
Uplink 23: ______XXXXXX____________________________________________________________________
Uplink 26: _____XXXXXX_____________________________________________________________________
Uplink 27: ______XXXXX_____________________________________________________________________
Uplink 28: _____XXXXXX_____________________________________________________________________
Uplink 29: ______XXXXX_____________________________________________________________________
Uplink 30: _____XXXXXX_____________________________________________________________________
Uplink 31: ______XXXXX_____________________________________________________________________
Data phase characteristics:
Uplink 8:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 9:
Optimal Phase: 38
Window Length: 34
Eye Window: ________________XXXXXX__________________
Uplink 10:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 11:
Optimal Phase: 38
Window Length: 35
Eye Window: ________________XXXXX___________________
Uplink 12:
Optimal Phase: 36
Window Length: 36
Eye Window: _______________XXXX_____________________
Uplink 13:
Optimal Phase: 38
Window Length: 35
Eye Window: ________________XXXXX___________________
Uplink 16:
Optimal Phase: 0
Window Length: 35
Eye Window: __________________XXXXX_________________
Uplink 17:
Optimal Phase: 1
Window Length: 35
Eye Window: ___________________XXXXX________________
Uplink 18:
Optimal Phase: 0
Window Length: 36
Eye Window: ___________________XXXX_________________
Uplink 19:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
Uplink 20:
Optimal Phase: 0
Window Length: 36
Eye Window: ___________________XXXX_________________
Uplink 21:
Optimal Phase: 1
Window Length: 35
Eye Window: ___________________XXXXX________________
Uplink 22:
Optimal Phase: 2
Window Length: 35
Eye Window: ____________________XXXXX_______________
Uplink 23:
Optimal Phase: 39
Window Length: 34
Eye Window: _________________XXXXXX_________________
Uplink 26:
Optimal Phase: 38
Window Length: 35
Eye Window: ________________XXXXX___________________
Uplink 27:
Optimal Phase: 0
Window Length: 33
Eye Window: _________________XXXXXXX________________
Uplink 28:
Optimal Phase: 38
Window Length: 36
Eye Window: _________________XXXX___________________
Uplink 29:
Optimal Phase: 1
Window Length: 35
Eye Window: ___________________XXXXX________________
Uplink 30:
Optimal Phase: 2
Window Length: 35
Eye Window: ____________________XXXXX_______________
Uplink 31:
Optimal Phase: 2
Window Length: 35
Eye Window: ____________________XXXXX_______________
11:19:49:setup_element:INFO: Performing Elink synchronization
11:19:49:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
11:19:49:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
11:19:49:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
11:19:49:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
11:19:49:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
11:19:49:uplink:INFO: Enabling uplinks [8, 9, 10, 11, 12, 13, 16, 17, 18, 19, 20, 21, 22, 23, 26, 27, 28, 29, 30, 31]
11:19:49:ST3_emu:INFO: Number of chips: 4
11:19:49:ST3_emu:INFO: Chip address: 0x1
11:19:49:ST3_emu:INFO: Chip address: 0x3
11:19:49:ST3_emu:INFO: Chip address: 0x5
11:19:49:ST3_emu:INFO: Chip address: 0x7
11:19:49:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:19:49:febtest:INFO: 0-1 | XA-000-08-002-000-005-177-06 | 28.2 | 1206.9
11:19:50:febtest:INFO: 0-3 | XA-000-08-002-000-006-210-03 | 34.6 | 1189.2
11:19:50:febtest:INFO: 0-5 | XA-000-08-002-000-005-180-06 | 18.7 | 1247.9
11:19:50:febtest:INFO: 0-7 | XA-000-08-002-000-006-214-03 | 12.4 | 1259.6
11:19:50:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:19:54:ST3_smx:INFO: chip: 0-1 25.062742 C 1206.851500 mV
11:19:54:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:19:54:ST3_smx:INFO: Electrons
11:19:54:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:19:56:ST3_smx:INFO: ----> Checking Analog response
11:19:56:ST3_smx:INFO: ----> Checking broken channels
11:19:57:ST3_smx:INFO: Total # broken ch: 4
11:19:57:ST3_smx:INFO: List FAST: [20, 97, 99, 120]
11:19:57:ST3_smx:INFO: List SLOW: []
11:19:57:ST3_smx:INFO: Holes
11:19:57:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:19:59:ST3_smx:INFO: ----> Checking Analog response
11:19:59:ST3_smx:INFO: ----> Checking broken channels
11:19:59:ST3_smx:INFO: Total # broken ch: 4
11:19:59:ST3_smx:INFO: List FAST: [20, 97, 99, 120]
11:19:59:ST3_smx:INFO: List SLOW: []
11:19:59:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:19:59:febtest:INFO: 0-1 | XA-000-08-002-000-005-177-06 | 28.2 | 1201.0
11:20:00:febtest:INFO: 0-3 | XA-000-08-002-000-006-210-03 | 34.6 | 1183.3
11:20:00:febtest:INFO: 0-5 | XA-000-08-002-000-005-180-06 | 18.7 | 1247.9
11:20:00:febtest:INFO: 0-7 | XA-000-08-002-000-006-214-03 | 12.4 | 1259.6
11:20:00:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:20:04:ST3_smx:INFO: chip: 0-3 40.898880 C 1147.806000 mV
11:20:04:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:20:04:ST3_smx:INFO: Electrons
11:20:04:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:20:06:ST3_smx:INFO: ----> Checking Analog response
11:20:06:ST3_smx:INFO: ----> Checking broken channels
11:20:07:ST3_smx:INFO: Total # broken ch: 1
11:20:07:ST3_smx:INFO: List FAST: [76]
11:20:07:ST3_smx:INFO: List SLOW: []
11:20:07:ST3_smx:INFO: Holes
11:20:07:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:20:09:ST3_smx:INFO: ----> Checking Analog response
11:20:09:ST3_smx:INFO: ----> Checking broken channels
11:20:09:ST3_smx:INFO: Total # broken ch: 1
11:20:09:ST3_smx:INFO: List FAST: [76]
11:20:09:ST3_smx:INFO: List SLOW: []
11:20:09:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:20:09:febtest:INFO: 0-1 | XA-000-08-002-000-005-177-06 | 31.4 | 1201.0
11:20:10:febtest:INFO: 0-3 | XA-000-08-002-000-006-210-03 | 44.1 | 1141.9
11:20:10:febtest:INFO: 0-5 | XA-000-08-002-000-005-180-06 | 18.7 | 1247.9
11:20:10:febtest:INFO: 0-7 | XA-000-08-002-000-006-214-03 | 12.4 | 1259.6
11:20:10:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:20:14:ST3_smx:INFO: chip: 0-5 21.902970 C 1230.330540 mV
11:20:14:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:20:14:ST3_smx:INFO: Electrons
11:20:14:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:20:16:ST3_smx:INFO: ----> Checking Analog response
11:20:16:ST3_smx:INFO: ----> Checking broken channels
11:20:16:ST3_smx:INFO: Total # broken ch: 5
11:20:16:ST3_smx:INFO: List FAST: [29, 51, 106, 117, 120]
11:20:16:ST3_smx:INFO: List SLOW: []
11:20:16:ST3_smx:INFO: Holes
11:20:16:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:20:19:ST3_smx:INFO: ----> Checking Analog response
11:20:19:ST3_smx:INFO: ----> Checking broken channels
11:20:19:ST3_smx:INFO: Total # broken ch: 5
11:20:19:ST3_smx:INFO: List FAST: [29, 51, 106, 117, 120]
11:20:19:ST3_smx:INFO: List SLOW: []
11:20:19:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:20:19:febtest:INFO: 0-1 | XA-000-08-002-000-005-177-06 | 31.4 | 1195.1
11:20:19:febtest:INFO: 0-3 | XA-000-08-002-000-006-210-03 | 44.1 | 1141.9
11:20:20:febtest:INFO: 0-5 | XA-000-08-002-000-005-180-06 | 25.1 | 1224.5
11:20:20:febtest:INFO: 0-7 | XA-000-08-002-000-006-214-03 | 12.4 | 1259.6
11:20:20:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
11:20:24:ST3_smx:INFO: chip: 0-7 25.062742 C 1212.728715 mV
11:20:24:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
11:20:24:ST3_smx:INFO: Electrons
11:20:24:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:20:26:ST3_smx:INFO: ----> Checking Analog response
11:20:26:ST3_smx:INFO: ----> Checking broken channels
11:20:27:ST3_smx:INFO: Total # broken ch: 4
11:20:27:ST3_smx:INFO: List FAST: [24, 37, 101, 115]
11:20:27:ST3_smx:INFO: List SLOW: []
11:20:27:ST3_smx:INFO: Holes
11:20:27:ST3_smx:INFO: Injected pulses: 200LSB, amp_cal 11.200000 fC
11:20:29:ST3_smx:INFO: ----> Checking Analog response
11:20:29:ST3_smx:INFO: ----> Checking broken channels
11:20:29:ST3_smx:INFO: Total # broken ch: 4
11:20:29:ST3_smx:INFO: List FAST: [24, 37, 101, 115]
11:20:29:ST3_smx:INFO: List SLOW: []
11:20:29:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
11:20:29:febtest:INFO: 0-1 | XA-000-08-002-000-005-177-06 | 31.4 | 1195.1
11:20:30:febtest:INFO: 0-3 | XA-000-08-002-000-006-210-03 | 44.1 | 1135.9
11:20:30:febtest:INFO: 0-5 | XA-000-08-002-000-005-180-06 | 25.1 | 1224.5
11:20:30:febtest:INFO: 0-7 | XA-000-08-002-000-006-214-03 | 28.2 | 1206.9
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_08_02-11_19_37', 'OPERATOR': 'Oleksandr S.; Robert V.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-006-214-03', 'FUSED_ID': 6359364699116563811, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 4, 'N_BROKEN_FAST': '[24, 37, 101, 115]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 4, 'P_BROKEN_FAST': '[24, 37, 101, 115]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.448', '0.8020', '1.848', '0.9878', '6.999', '1.5280', '6.999', '1.5280'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 200, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 200, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
11:20:33:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir//FEB/FEB_5013/A//TestDate_2023_08_02-11_19_37/
Comment
0421 L28 M03