13:03:39:febtest:INFO:	FEB8.5 selected
13:03:39:smx_tester:INFO:	Setting Elink clock mode to 160 MHz
13:03:47:febtest:INFO:	FEB 8-5 B @ GSI
13:04:52:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:04:52:ST3_Shared:INFO:	--------------------------FEB-ASIC--------------------------
13:04:52:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
13:04:53:febtest:INFO:	Tsting FEB with SN 6019
13:04:54:smx_tester:INFO:	Scanning setup
13:04:54:elinks:INFO:	Disabling clock on downlink 0
13:04:54:elinks:INFO:	Disabling clock on downlink 1
13:04:54:elinks:INFO:	Disabling clock on downlink 2
13:04:54:elinks:INFO:	Disabling clock on downlink 3
13:04:54:elinks:INFO:	Disabling clock on downlink 4
13:04:54:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:04:54:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
13:04:54:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:04:54:elinks:INFO:	Disabling clock on downlink 0
13:04:54:elinks:INFO:	Disabling clock on downlink 1
13:04:54:elinks:INFO:	Disabling clock on downlink 2
13:04:54:elinks:INFO:	Disabling clock on downlink 3
13:04:54:elinks:INFO:	Disabling clock on downlink 4
13:04:54:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:04:54:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
13:04:54:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:04:54:elinks:INFO:	Disabling clock on downlink 0
13:04:54:elinks:INFO:	Disabling clock on downlink 1
13:04:54:elinks:INFO:	Disabling clock on downlink 2
13:04:54:elinks:INFO:	Disabling clock on downlink 3
13:04:54:elinks:INFO:	Disabling clock on downlink 4
13:04:54:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:04:54:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 0
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 1
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 2
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 3
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 4
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 5
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 6
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 7
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 8
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 9
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 10
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 11
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 12
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 13
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 14
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 15
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 16
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 17
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 18
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 19
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 20
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 21
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 22
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 23
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 32
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 33
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 34
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 35
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 36
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 37
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 38
13:04:54:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 39
13:04:54:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:04:54:elinks:INFO:	Disabling clock on downlink 0
13:04:54:elinks:INFO:	Disabling clock on downlink 1
13:04:54:elinks:INFO:	Disabling clock on downlink 2
13:04:54:elinks:INFO:	Disabling clock on downlink 3
13:04:54:elinks:INFO:	Disabling clock on downlink 4
13:04:54:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:04:54:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
13:04:54:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:04:54:elinks:INFO:	Disabling clock on downlink 0
13:04:54:elinks:INFO:	Disabling clock on downlink 1
13:04:54:elinks:INFO:	Disabling clock on downlink 2
13:04:55:elinks:INFO:	Disabling clock on downlink 3
13:04:55:elinks:INFO:	Disabling clock on downlink 4
13:04:55:setup_element:INFO:	Checking SOS, encoding_mode: SOS
13:04:55:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
13:04:55:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
13:04:55:setup_element:INFO:	Scanning clock phase
13:04:55:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:04:55:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:04:55:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
13:04:55:setup_element:INFO:	Eye window for uplink 0 : _____XXXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 1 : _____XXXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 2 : _____XXXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 3 : _____XXXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 4 : _____XXXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 5 : _____XXXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 6 : _____XXXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 7 : _____XXXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 8 : ______XXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 9 : _____XXXXXX_____________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 10: ______XXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 11: _____XXXXXX_____________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 12: ______XXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 13: _____XXXXXX_____________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 14: _____XXXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 15: _____XXXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 16: ______XXXXXX____________________________________________________________________
Clock Delay: 48
13:04:55:setup_element:INFO:	Eye window for uplink 17: ______XXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 18: ______XXXXXX____________________________________________________________________
Clock Delay: 48
13:04:55:setup_element:INFO:	Eye window for uplink 19: ______XXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 20: ______XXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 21: _____XXXXXX_____________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 22: ______XXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 23: _____XXXXXX_____________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 24: _____XXXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 25: ____XXXXXX______________________________________________________________________
Clock Delay: 46
13:04:55:setup_element:INFO:	Eye window for uplink 26: ______XXXXXX____________________________________________________________________
Clock Delay: 48
13:04:55:setup_element:INFO:	Eye window for uplink 27: ______XXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 28: ______XXXXXX____________________________________________________________________
Clock Delay: 48
13:04:55:setup_element:INFO:	Eye window for uplink 29: ______XXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 30: ______XXXXXX____________________________________________________________________
Clock Delay: 48
13:04:55:setup_element:INFO:	Eye window for uplink 31: ______XXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 32: _____XXXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 33: ____XXXXXX______________________________________________________________________
Clock Delay: 46
13:04:55:setup_element:INFO:	Eye window for uplink 34: _____XXXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 35: ____XXXXXX______________________________________________________________________
Clock Delay: 46
13:04:55:setup_element:INFO:	Eye window for uplink 36: _____XXXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 37: ____XXXXXX______________________________________________________________________
Clock Delay: 46
13:04:55:setup_element:INFO:	Eye window for uplink 38: _____XXXXX______________________________________________________________________
Clock Delay: 47
13:04:55:setup_element:INFO:	Eye window for uplink 39: ____XXXXXX______________________________________________________________________
Clock Delay: 46
13:04:55:setup_element:INFO:	Setting the clock phase to 47 for group 0, downlink 2
13:04:55:setup_element:INFO:	Scanning data phases
13:04:55:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:04:55:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:05:02:setup_element:INFO:	Data phase scan results for group 0, downlink 2
13:05:02:setup_element:INFO:	Eye window for uplink 0 : ______________________XXXXXX____________
Data delay found: 4
13:05:02:setup_element:INFO:	Eye window for uplink 1 : ___________________________XXXXX________
Data delay found: 9
13:05:02:setup_element:INFO:	Eye window for uplink 2 : _______________________XXXXXX___________
Data delay found: 5
13:05:02:setup_element:INFO:	Eye window for uplink 3 : ____________________________XXXXX_______
Data delay found: 10
13:05:02:setup_element:INFO:	Eye window for uplink 4 : ________________________XXXXX___________
Data delay found: 6
13:05:02:setup_element:INFO:	Eye window for uplink 5 : _____________________________XXXX_______
Data delay found: 10
13:05:02:setup_element:INFO:	Eye window for uplink 6 : ____________________XXXXX_______________
Data delay found: 2
13:05:02:setup_element:INFO:	Eye window for uplink 7 : __________________________XXXX__________
Data delay found: 7
13:05:02:setup_element:INFO:	Eye window for uplink 8 : ________XXXXXX__________________________
Data delay found: 30
13:05:02:setup_element:INFO:	Eye window for uplink 9 : ____________XXXXX_______________________
Data delay found: 34
13:05:02:setup_element:INFO:	Eye window for uplink 10: __________XXXXXX________________________
Data delay found: 32
13:05:02:setup_element:INFO:	Eye window for uplink 11: ____________XXXXX_______________________
Data delay found: 34
13:05:02:setup_element:INFO:	Eye window for uplink 12: ___________XXXX_________________________
Data delay found: 32
13:05:02:setup_element:INFO:	Eye window for uplink 13: ____________XXXXX_______________________
Data delay found: 34
13:05:02:setup_element:INFO:	Eye window for uplink 14: _____________________XXXXX______________
Data delay found: 3
13:05:02:setup_element:INFO:	Eye window for uplink 15: ___________________________XXXXX________
Data delay found: 9
13:05:02:setup_element:INFO:	Eye window for uplink 16: ________________XXXXXX__________________
Data delay found: 38
13:05:02:setup_element:INFO:	Eye window for uplink 17: _______________XXXX_____________________
Data delay found: 36
13:05:02:setup_element:INFO:	Eye window for uplink 18: ________________XXXXXX__________________
Data delay found: 38
13:05:02:setup_element:INFO:	Eye window for uplink 19: ________________XXXXX___________________
Data delay found: 38
13:05:02:setup_element:INFO:	Eye window for uplink 20: ______________XXXXX_____________________
Data delay found: 36
13:05:02:setup_element:INFO:	Eye window for uplink 21: _______________XXXX_____________________
Data delay found: 36
13:05:02:setup_element:INFO:	Eye window for uplink 22: _______________XXXXXX___________________
Data delay found: 37
13:05:02:setup_element:INFO:	Eye window for uplink 23: _____________XXXX_______________________
Data delay found: 34
13:05:02:setup_element:INFO:	Eye window for uplink 24: __________________________XXXXXX________
Data delay found: 8
13:05:02:setup_element:INFO:	Eye window for uplink 25: ___________________XXXXX________________
Data delay found: 1
13:05:02:setup_element:INFO:	Eye window for uplink 26: _____________XXXXX______________________
Data delay found: 35
13:05:02:setup_element:INFO:	Eye window for uplink 27: _______________XXXXXX___________________
Data delay found: 37
13:05:02:setup_element:INFO:	Eye window for uplink 28: _________________XXXXXX_________________
Data delay found: 39
13:05:02:setup_element:INFO:	Eye window for uplink 29: _________________XXXXX__________________
Data delay found: 39
13:05:02:setup_element:INFO:	Eye window for uplink 30: _________________XXXXX__________________
Data delay found: 39
13:05:02:setup_element:INFO:	Eye window for uplink 31: _______________XXXXXX___________________
Data delay found: 37
13:05:02:setup_element:INFO:	Eye window for uplink 32: ___________________________XXXXX________
Data delay found: 9
13:05:02:setup_element:INFO:	Eye window for uplink 33: ___________________XXXXXX_______________
Data delay found: 1
13:05:02:setup_element:INFO:	Eye window for uplink 34: ___________________________XXXX_________
Data delay found: 8
13:05:02:setup_element:INFO:	Eye window for uplink 35: ____________________XXXXX_______________
Data delay found: 2
13:05:02:setup_element:INFO:	Eye window for uplink 36: _________________________XXXXX__________
Data delay found: 7
13:05:02:setup_element:INFO:	Eye window for uplink 37: ____________________XXXXX_______________
Data delay found: 2
13:05:02:setup_element:INFO:	Eye window for uplink 38: ________________________XXXXX___________
Data delay found: 6
13:05:02:setup_element:INFO:	Eye window for uplink 39: ___________________XXXXX________________
Data delay found: 1
13:05:02:setup_element:INFO:	Setting the data phase to 4 for uplink 0
13:05:02:setup_element:INFO:	Setting the data phase to 9 for uplink 1
13:05:02:setup_element:INFO:	Setting the data phase to 5 for uplink 2
13:05:02:setup_element:INFO:	Setting the data phase to 10 for uplink 3
13:05:02:setup_element:INFO:	Setting the data phase to 6 for uplink 4
13:05:02:setup_element:INFO:	Setting the data phase to 10 for uplink 5
13:05:02:setup_element:INFO:	Setting the data phase to 2 for uplink 6
13:05:02:setup_element:INFO:	Setting the data phase to 7 for uplink 7
13:05:02:setup_element:INFO:	Setting the data phase to 30 for uplink 8
13:05:02:setup_element:INFO:	Setting the data phase to 34 for uplink 9
13:05:02:setup_element:INFO:	Setting the data phase to 32 for uplink 10
13:05:02:setup_element:INFO:	Setting the data phase to 34 for uplink 11
13:05:02:setup_element:INFO:	Setting the data phase to 32 for uplink 12
13:05:02:setup_element:INFO:	Setting the data phase to 34 for uplink 13
13:05:02:setup_element:INFO:	Setting the data phase to 3 for uplink 14
13:05:02:setup_element:INFO:	Setting the data phase to 9 for uplink 15
13:05:02:setup_element:INFO:	Setting the data phase to 38 for uplink 16
13:05:02:setup_element:INFO:	Setting the data phase to 36 for uplink 17
13:05:02:setup_element:INFO:	Setting the data phase to 38 for uplink 18
13:05:02:setup_element:INFO:	Setting the data phase to 38 for uplink 19
13:05:02:setup_element:INFO:	Setting the data phase to 36 for uplink 20
13:05:02:setup_element:INFO:	Setting the data phase to 36 for uplink 21
13:05:02:setup_element:INFO:	Setting the data phase to 37 for uplink 22
13:05:02:setup_element:INFO:	Setting the data phase to 34 for uplink 23
13:05:02:setup_element:INFO:	Setting the data phase to 8 for uplink 24
13:05:02:setup_element:INFO:	Setting the data phase to 1 for uplink 25
13:05:02:setup_element:INFO:	Setting the data phase to 35 for uplink 26
13:05:02:setup_element:INFO:	Setting the data phase to 37 for uplink 27
13:05:02:setup_element:INFO:	Setting the data phase to 39 for uplink 28
13:05:02:setup_element:INFO:	Setting the data phase to 39 for uplink 29
13:05:02:setup_element:INFO:	Setting the data phase to 39 for uplink 30
13:05:02:setup_element:INFO:	Setting the data phase to 37 for uplink 31
13:05:02:setup_element:INFO:	Setting the data phase to 9 for uplink 32
13:05:02:setup_element:INFO:	Setting the data phase to 1 for uplink 33
13:05:02:setup_element:INFO:	Setting the data phase to 8 for uplink 34
13:05:02:setup_element:INFO:	Setting the data phase to 2 for uplink 35
13:05:02:setup_element:INFO:	Setting the data phase to 7 for uplink 36
13:05:02:setup_element:INFO:	Setting the data phase to 2 for uplink 37
13:05:02:setup_element:INFO:	Setting the data phase to 6 for uplink 38
13:05:02:setup_element:INFO:	Setting the data phase to 1 for uplink 39
13:05:02:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 47
    Window Length: 72
    Eye Windows:
      Uplink  0: _____XXXXX______________________________________________________________________
      Uplink  1: _____XXXXX______________________________________________________________________
      Uplink  2: _____XXXXX______________________________________________________________________
      Uplink  3: _____XXXXX______________________________________________________________________
      Uplink  4: _____XXXXX______________________________________________________________________
      Uplink  5: _____XXXXX______________________________________________________________________
      Uplink  6: _____XXXXX______________________________________________________________________
      Uplink  7: _____XXXXX______________________________________________________________________
      Uplink  8: ______XXXX______________________________________________________________________
      Uplink  9: _____XXXXXX_____________________________________________________________________
      Uplink 10: ______XXXX______________________________________________________________________
      Uplink 11: _____XXXXXX_____________________________________________________________________
      Uplink 12: ______XXXX______________________________________________________________________
      Uplink 13: _____XXXXXX_____________________________________________________________________
      Uplink 14: _____XXXXX______________________________________________________________________
      Uplink 15: _____XXXXX______________________________________________________________________
      Uplink 16: ______XXXXXX____________________________________________________________________
      Uplink 17: ______XXXX______________________________________________________________________
      Uplink 18: ______XXXXXX____________________________________________________________________
      Uplink 19: ______XXXX______________________________________________________________________
      Uplink 20: ______XXXX______________________________________________________________________
      Uplink 21: _____XXXXXX_____________________________________________________________________
      Uplink 22: ______XXXX______________________________________________________________________
      Uplink 23: _____XXXXXX_____________________________________________________________________
      Uplink 24: _____XXXXX______________________________________________________________________
      Uplink 25: ____XXXXXX______________________________________________________________________
      Uplink 26: ______XXXXXX____________________________________________________________________
      Uplink 27: ______XXXX______________________________________________________________________
      Uplink 28: ______XXXXXX____________________________________________________________________
      Uplink 29: ______XXXX______________________________________________________________________
      Uplink 30: ______XXXXXX____________________________________________________________________
      Uplink 31: ______XXXX______________________________________________________________________
      Uplink 32: _____XXXXX______________________________________________________________________
      Uplink 33: ____XXXXXX______________________________________________________________________
      Uplink 34: _____XXXXX______________________________________________________________________
      Uplink 35: ____XXXXXX______________________________________________________________________
      Uplink 36: _____XXXXX______________________________________________________________________
      Uplink 37: ____XXXXXX______________________________________________________________________
      Uplink 38: _____XXXXX______________________________________________________________________
      Uplink 39: ____XXXXXX______________________________________________________________________
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 4
      Window Length: 34
      Eye Window: ______________________XXXXXX____________
    Uplink 1:
      Optimal Phase: 9
      Window Length: 35
      Eye Window: ___________________________XXXXX________
    Uplink 2:
      Optimal Phase: 5
      Window Length: 34
      Eye Window: _______________________XXXXXX___________
    Uplink 3:
      Optimal Phase: 10
      Window Length: 35
      Eye Window: ____________________________XXXXX_______
    Uplink 4:
      Optimal Phase: 6
      Window Length: 35
      Eye Window: ________________________XXXXX___________
    Uplink 5:
      Optimal Phase: 10
      Window Length: 36
      Eye Window: _____________________________XXXX_______
    Uplink 6:
      Optimal Phase: 2
      Window Length: 35
      Eye Window: ____________________XXXXX_______________
    Uplink 7:
      Optimal Phase: 7
      Window Length: 36
      Eye Window: __________________________XXXX__________
    Uplink 8:
      Optimal Phase: 30
      Window Length: 34
      Eye Window: ________XXXXXX__________________________
    Uplink 9:
      Optimal Phase: 34
      Window Length: 35
      Eye Window: ____________XXXXX_______________________
    Uplink 10:
      Optimal Phase: 32
      Window Length: 34
      Eye Window: __________XXXXXX________________________
    Uplink 11:
      Optimal Phase: 34
      Window Length: 35
      Eye Window: ____________XXXXX_______________________
    Uplink 12:
      Optimal Phase: 32
      Window Length: 36
      Eye Window: ___________XXXX_________________________
    Uplink 13:
      Optimal Phase: 34
      Window Length: 35
      Eye Window: ____________XXXXX_______________________
    Uplink 14:
      Optimal Phase: 3
      Window Length: 35
      Eye Window: _____________________XXXXX______________
    Uplink 15:
      Optimal Phase: 9
      Window Length: 35
      Eye Window: ___________________________XXXXX________
    Uplink 16:
      Optimal Phase: 38
      Window Length: 34
      Eye Window: ________________XXXXXX__________________
    Uplink 17:
      Optimal Phase: 36
      Window Length: 36
      Eye Window: _______________XXXX_____________________
    Uplink 18:
      Optimal Phase: 38
      Window Length: 34
      Eye Window: ________________XXXXXX__________________
    Uplink 19:
      Optimal Phase: 38
      Window Length: 35
      Eye Window: ________________XXXXX___________________
    Uplink 20:
      Optimal Phase: 36
      Window Length: 35
      Eye Window: ______________XXXXX_____________________
    Uplink 21:
      Optimal Phase: 36
      Window Length: 36
      Eye Window: _______________XXXX_____________________
    Uplink 22:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 23:
      Optimal Phase: 34
      Window Length: 36
      Eye Window: _____________XXXX_______________________
    Uplink 24:
      Optimal Phase: 8
      Window Length: 34
      Eye Window: __________________________XXXXXX________
    Uplink 25:
      Optimal Phase: 1
      Window Length: 35
      Eye Window: ___________________XXXXX________________
    Uplink 26:
      Optimal Phase: 35
      Window Length: 35
      Eye Window: _____________XXXXX______________________
    Uplink 27:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 28:
      Optimal Phase: 39
      Window Length: 34
      Eye Window: _________________XXXXXX_________________
    Uplink 29:
      Optimal Phase: 39
      Window Length: 35
      Eye Window: _________________XXXXX__________________
    Uplink 30:
      Optimal Phase: 39
      Window Length: 35
      Eye Window: _________________XXXXX__________________
    Uplink 31:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 32:
      Optimal Phase: 9
      Window Length: 35
      Eye Window: ___________________________XXXXX________
    Uplink 33:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 34:
      Optimal Phase: 8
      Window Length: 36
      Eye Window: ___________________________XXXX_________
    Uplink 35:
      Optimal Phase: 2
      Window Length: 35
      Eye Window: ____________________XXXXX_______________
    Uplink 36:
      Optimal Phase: 7
      Window Length: 35
      Eye Window: _________________________XXXXX__________
    Uplink 37:
      Optimal Phase: 2
      Window Length: 35
      Eye Window: ____________________XXXXX_______________
    Uplink 38:
      Optimal Phase: 6
      Window Length: 35
      Eye Window: ________________________XXXXX___________
    Uplink 39:
      Optimal Phase: 1
      Window Length: 35
      Eye Window: ___________________XXXXX________________
]
13:05:02:setup_element:INFO:	Beginning SMX ASICs map scan
13:05:02:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:05:02:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:05:02:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
13:05:02:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
13:05:02:uplink:INFO:	Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39]
13:05:02:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 21
13:05:02:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 23
13:05:02:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 2, uplink 9
13:05:02:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 3, uplink 11
13:05:02:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 4, uplink 13
13:05:02:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 15
13:05:02:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 1
13:05:02:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 2, uplink 3
13:05:02:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 3, uplink 5
13:05:02:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 4, uplink 7
13:05:02:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 18
13:05:02:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 16
13:05:02:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 2, uplink 30
13:05:02:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 3, uplink 28
13:05:02:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 4, uplink 26
13:05:02:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 24
13:05:03:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 38
13:05:03:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 2, uplink 36
13:05:03:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 3, uplink 34
13:05:03:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 4, uplink 32
13:05:03:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 20
13:05:03:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 22
13:05:03:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 2, uplink 8
13:05:03:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 3, uplink 10
13:05:03:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 4, uplink 12
13:05:03:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 14
13:05:03:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 0
13:05:03:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 2, uplink 2
13:05:03:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 3, uplink 4
13:05:03:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 4, uplink 6
13:05:03:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 19
13:05:03:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 17
13:05:03:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 2, uplink 31
13:05:03:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 3, uplink 29
13:05:03:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 4, uplink 27
13:05:03:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 25
13:05:03:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 39
13:05:03:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 2, uplink 37
13:05:03:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 3, uplink 35
13:05:04:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 4, uplink 33
13:05:05:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 21), (1, 23), (2, 9), (3, 11), (4, 13)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 15), (1, 1), (2, 3), (3, 5), (4, 7)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 18), (1, 16), (2, 30), (3, 28), (4, 26)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 24), (1, 38), (2, 36), (3, 34), (4, 32)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 20), (1, 22), (2, 8), (3, 10), (4, 12)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 14), (1, 0), (2, 2), (3, 4), (4, 6)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 19), (1, 17), (2, 31), (3, 29), (4, 27)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 25), (1, 39), (2, 37), (3, 35), (4, 33)
  Clock Phase Characteristic:
    Optimal Phase: 47
    Window Length: 72
    Eye Windows:
      Uplink  0: _____XXXXX______________________________________________________________________
      Uplink  1: _____XXXXX______________________________________________________________________
      Uplink  2: _____XXXXX______________________________________________________________________
      Uplink  3: _____XXXXX______________________________________________________________________
      Uplink  4: _____XXXXX______________________________________________________________________
      Uplink  5: _____XXXXX______________________________________________________________________
      Uplink  6: _____XXXXX______________________________________________________________________
      Uplink  7: _____XXXXX______________________________________________________________________
      Uplink  8: ______XXXX______________________________________________________________________
      Uplink  9: _____XXXXXX_____________________________________________________________________
      Uplink 10: ______XXXX______________________________________________________________________
      Uplink 11: _____XXXXXX_____________________________________________________________________
      Uplink 12: ______XXXX______________________________________________________________________
      Uplink 13: _____XXXXXX_____________________________________________________________________
      Uplink 14: _____XXXXX______________________________________________________________________
      Uplink 15: _____XXXXX______________________________________________________________________
      Uplink 16: ______XXXXXX____________________________________________________________________
      Uplink 17: ______XXXX______________________________________________________________________
      Uplink 18: ______XXXXXX____________________________________________________________________
      Uplink 19: ______XXXX______________________________________________________________________
      Uplink 20: ______XXXX______________________________________________________________________
      Uplink 21: _____XXXXXX_____________________________________________________________________
      Uplink 22: ______XXXX______________________________________________________________________
      Uplink 23: _____XXXXXX_____________________________________________________________________
      Uplink 24: _____XXXXX______________________________________________________________________
      Uplink 25: ____XXXXXX______________________________________________________________________
      Uplink 26: ______XXXXXX____________________________________________________________________
      Uplink 27: ______XXXX______________________________________________________________________
      Uplink 28: ______XXXXXX____________________________________________________________________
      Uplink 29: ______XXXX______________________________________________________________________
      Uplink 30: ______XXXXXX____________________________________________________________________
      Uplink 31: ______XXXX______________________________________________________________________
      Uplink 32: _____XXXXX______________________________________________________________________
      Uplink 33: ____XXXXXX______________________________________________________________________
      Uplink 34: _____XXXXX______________________________________________________________________
      Uplink 35: ____XXXXXX______________________________________________________________________
      Uplink 36: _____XXXXX______________________________________________________________________
      Uplink 37: ____XXXXXX______________________________________________________________________
      Uplink 38: _____XXXXX______________________________________________________________________
      Uplink 39: ____XXXXXX______________________________________________________________________
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 4
      Window Length: 34
      Eye Window: ______________________XXXXXX____________
    Uplink 1:
      Optimal Phase: 9
      Window Length: 35
      Eye Window: ___________________________XXXXX________
    Uplink 2:
      Optimal Phase: 5
      Window Length: 34
      Eye Window: _______________________XXXXXX___________
    Uplink 3:
      Optimal Phase: 10
      Window Length: 35
      Eye Window: ____________________________XXXXX_______
    Uplink 4:
      Optimal Phase: 6
      Window Length: 35
      Eye Window: ________________________XXXXX___________
    Uplink 5:
      Optimal Phase: 10
      Window Length: 36
      Eye Window: _____________________________XXXX_______
    Uplink 6:
      Optimal Phase: 2
      Window Length: 35
      Eye Window: ____________________XXXXX_______________
    Uplink 7:
      Optimal Phase: 7
      Window Length: 36
      Eye Window: __________________________XXXX__________
    Uplink 8:
      Optimal Phase: 30
      Window Length: 34
      Eye Window: ________XXXXXX__________________________
    Uplink 9:
      Optimal Phase: 34
      Window Length: 35
      Eye Window: ____________XXXXX_______________________
    Uplink 10:
      Optimal Phase: 32
      Window Length: 34
      Eye Window: __________XXXXXX________________________
    Uplink 11:
      Optimal Phase: 34
      Window Length: 35
      Eye Window: ____________XXXXX_______________________
    Uplink 12:
      Optimal Phase: 32
      Window Length: 36
      Eye Window: ___________XXXX_________________________
    Uplink 13:
      Optimal Phase: 34
      Window Length: 35
      Eye Window: ____________XXXXX_______________________
    Uplink 14:
      Optimal Phase: 3
      Window Length: 35
      Eye Window: _____________________XXXXX______________
    Uplink 15:
      Optimal Phase: 9
      Window Length: 35
      Eye Window: ___________________________XXXXX________
    Uplink 16:
      Optimal Phase: 38
      Window Length: 34
      Eye Window: ________________XXXXXX__________________
    Uplink 17:
      Optimal Phase: 36
      Window Length: 36
      Eye Window: _______________XXXX_____________________
    Uplink 18:
      Optimal Phase: 38
      Window Length: 34
      Eye Window: ________________XXXXXX__________________
    Uplink 19:
      Optimal Phase: 38
      Window Length: 35
      Eye Window: ________________XXXXX___________________
    Uplink 20:
      Optimal Phase: 36
      Window Length: 35
      Eye Window: ______________XXXXX_____________________
    Uplink 21:
      Optimal Phase: 36
      Window Length: 36
      Eye Window: _______________XXXX_____________________
    Uplink 22:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 23:
      Optimal Phase: 34
      Window Length: 36
      Eye Window: _____________XXXX_______________________
    Uplink 24:
      Optimal Phase: 8
      Window Length: 34
      Eye Window: __________________________XXXXXX________
    Uplink 25:
      Optimal Phase: 1
      Window Length: 35
      Eye Window: ___________________XXXXX________________
    Uplink 26:
      Optimal Phase: 35
      Window Length: 35
      Eye Window: _____________XXXXX______________________
    Uplink 27:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 28:
      Optimal Phase: 39
      Window Length: 34
      Eye Window: _________________XXXXXX_________________
    Uplink 29:
      Optimal Phase: 39
      Window Length: 35
      Eye Window: _________________XXXXX__________________
    Uplink 30:
      Optimal Phase: 39
      Window Length: 35
      Eye Window: _________________XXXXX__________________
    Uplink 31:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 32:
      Optimal Phase: 9
      Window Length: 35
      Eye Window: ___________________________XXXXX________
    Uplink 33:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 34:
      Optimal Phase: 8
      Window Length: 36
      Eye Window: ___________________________XXXX_________
    Uplink 35:
      Optimal Phase: 2
      Window Length: 35
      Eye Window: ____________________XXXXX_______________
    Uplink 36:
      Optimal Phase: 7
      Window Length: 35
      Eye Window: _________________________XXXXX__________
    Uplink 37:
      Optimal Phase: 2
      Window Length: 35
      Eye Window: ____________________XXXXX_______________
    Uplink 38:
      Optimal Phase: 6
      Window Length: 35
      Eye Window: ________________________XXXXX___________
    Uplink 39:
      Optimal Phase: 1
      Window Length: 35
      Eye Window: ___________________XXXXX________________

13:05:05:setup_element:INFO:	Performing Elink synchronization
13:05:05:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
13:05:05:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
13:05:05:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
13:05:05:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
13:05:05:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
13:05:05:uplink:INFO:	Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39]
13:05:05:ST3_emu:INFO:	Number of chips: 8
13:05:05:ST3_emu:INFO:	Chip address:  	0x0
13:05:05:ST3_emu:INFO:	Chip address:  	0x1
13:05:05:ST3_emu:INFO:	Chip address:  	0x2
13:05:05:ST3_emu:INFO:	Chip address:  	0x3
13:05:05:ST3_emu:INFO:	Chip address:  	0x4
13:05:05:ST3_emu:INFO:	Chip address:  	0x5
13:05:05:ST3_emu:INFO:	Chip address:  	0x6
13:05:05:ST3_emu:INFO:	Chip address:  	0x7
13:05:06:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:05:06:febtest:INFO:	0-0 | XA-000-08-002-000-007-067-03 |  44.1 | 1165.6
13:05:06:febtest:INFO:	0-1 | XA-000-08-002-000-007-013-06 |  40.9 | 1177.4
13:05:06:febtest:INFO:	0-2 | XA-000-08-002-000-007-044-08 |  25.1 | 1242.0
13:05:07:febtest:INFO:	0-3 | XA-000-08-002-000-007-034-08 |  25.1 | 1236.2
13:05:07:febtest:INFO:	0-4 | XA-000-08-002-000-007-038-08 |  37.7 | 1206.9
13:05:07:febtest:INFO:	0-5 | XA-000-08-002-000-007-043-08 |  31.4 | 1218.6
13:05:07:febtest:INFO:	0-6 | XA-000-08-002-000-007-028-01 |  44.1 | 1171.5
13:05:08:febtest:INFO:	0-7 | XA-000-08-002-000-007-056-15 |  40.9 | 1171.5
13:05:08:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:05:11:ST3_smx:INFO:	chip: 0-0 	 40.898880 C 	 1171.483840 mV
13:05:11:ST3_smx:INFO:	PROCESS 2: Checking channel response with internal pulse
13:05:11:ST3_smx:INFO:		Electrons
13:05:11:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
13:05:13:ST3_smx:INFO:	----> Checking Analog response
13:05:13:ST3_smx:INFO:	----> Checking broken channels
13:05:14:ST3_smx:INFO:	Total # broken ch: 0
13:05:14:ST3_smx:INFO:	List FAST: []
13:05:14:ST3_smx:INFO:	List SLOW: []
13:05:14:ST3_smx:INFO:		Holes
13:05:14:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
13:05:16:ST3_smx:INFO:	----> Checking Analog response
13:05:16:ST3_smx:INFO:	----> Checking broken channels
13:05:16:ST3_smx:INFO:	Total # broken ch: 0
13:05:16:ST3_smx:INFO:	List FAST: []
13:05:16:ST3_smx:INFO:	List SLOW: []
13:05:16:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:05:16:febtest:INFO:	0-0 | XA-000-08-002-000-007-067-03 |  40.9 | 1165.6
13:05:16:febtest:INFO:	0-1 | XA-000-08-002-000-007-013-06 |  40.9 | 1177.4
13:05:16:febtest:INFO:	0-2 | XA-000-08-002-000-007-044-08 |  25.1 | 1236.2
13:05:17:febtest:INFO:	0-3 | XA-000-08-002-000-007-034-08 |  25.1 | 1236.2
13:05:17:febtest:INFO:	0-4 | XA-000-08-002-000-007-038-08 |  37.7 | 1201.0
13:05:17:febtest:INFO:	0-5 | XA-000-08-002-000-007-043-08 |  31.4 | 1212.7
13:05:17:febtest:INFO:	0-6 | XA-000-08-002-000-007-028-01 |  44.1 | 1171.5
13:05:18:febtest:INFO:	0-7 | XA-000-08-002-000-007-056-15 |  40.9 | 1171.5
13:05:18:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:05:21:ST3_smx:INFO:	chip: 0-1 	 50.430383 C 	 1135.937260 mV
13:05:21:ST3_smx:INFO:	PROCESS 2: Checking channel response with internal pulse
13:05:21:ST3_smx:INFO:		Electrons
13:05:21:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
13:05:24:ST3_smx:INFO:	----> Checking Analog response
13:05:24:ST3_smx:INFO:	----> Checking broken channels
13:05:24:ST3_smx:INFO:	Total # broken ch: 0
13:05:24:ST3_smx:INFO:	List FAST: []
13:05:24:ST3_smx:INFO:	List SLOW: []
13:05:24:ST3_smx:INFO:		Holes
13:05:24:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
13:05:26:ST3_smx:INFO:	----> Checking Analog response
13:05:26:ST3_smx:INFO:	----> Checking broken channels
13:05:26:ST3_smx:INFO:	Total # broken ch: 0
13:05:26:ST3_smx:INFO:	List FAST: []
13:05:26:ST3_smx:INFO:	List SLOW: []
13:05:26:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:05:26:febtest:INFO:	0-0 | XA-000-08-002-000-007-067-03 |  40.9 | 1165.6
13:05:26:febtest:INFO:	0-1 | XA-000-08-002-000-007-013-06 |  50.4 | 1135.9
13:05:27:febtest:INFO:	0-2 | XA-000-08-002-000-007-044-08 |  25.1 | 1242.0
13:05:27:febtest:INFO:	0-3 | XA-000-08-002-000-007-034-08 |  28.2 | 1236.2
13:05:27:febtest:INFO:	0-4 | XA-000-08-002-000-007-038-08 |  37.7 | 1201.0
13:05:27:febtest:INFO:	0-5 | XA-000-08-002-000-007-043-08 |  31.4 | 1212.7
13:05:28:febtest:INFO:	0-6 | XA-000-08-002-000-007-028-01 |  44.1 | 1171.5
13:05:28:febtest:INFO:	0-7 | XA-000-08-002-000-007-056-15 |  40.9 | 1171.5
13:05:28:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:05:32:ST3_smx:INFO:	chip: 0-2 	 25.062742 C 	 1230.330540 mV
13:05:32:ST3_smx:INFO:	PROCESS 2: Checking channel response with internal pulse
13:05:32:ST3_smx:INFO:		Electrons
13:05:32:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
13:05:34:ST3_smx:INFO:	----> Checking Analog response
13:05:34:ST3_smx:INFO:	----> Checking broken channels
13:05:34:ST3_smx:INFO:	Total # broken ch: 0
13:05:34:ST3_smx:INFO:	List FAST: []
13:05:34:ST3_smx:INFO:	List SLOW: []
13:05:34:ST3_smx:INFO:		Holes
13:05:34:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
13:05:36:ST3_smx:INFO:	----> Checking Analog response
13:05:36:ST3_smx:INFO:	----> Checking broken channels
13:05:36:ST3_smx:INFO:	Total # broken ch: 0
13:05:36:ST3_smx:INFO:	List FAST: []
13:05:36:ST3_smx:INFO:	List SLOW: []
13:05:36:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:05:36:febtest:INFO:	0-0 | XA-000-08-002-000-007-067-03 |  40.9 | 1165.6
13:05:37:febtest:INFO:	0-1 | XA-000-08-002-000-007-013-06 |  50.4 | 1135.9
13:05:37:febtest:INFO:	0-2 | XA-000-08-002-000-007-044-08 |  25.1 | 1230.3
13:05:37:febtest:INFO:	0-3 | XA-000-08-002-000-007-034-08 |  28.2 | 1236.2
13:05:37:febtest:INFO:	0-4 | XA-000-08-002-000-007-038-08 |  37.7 | 1201.0
13:05:38:febtest:INFO:	0-5 | XA-000-08-002-000-007-043-08 |  31.4 | 1212.7
13:05:38:febtest:INFO:	0-6 | XA-000-08-002-000-007-028-01 |  44.1 | 1165.6
13:05:38:febtest:INFO:	0-7 | XA-000-08-002-000-007-056-15 |  40.9 | 1171.5
13:05:38:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:05:42:ST3_smx:INFO:	chip: 0-3 	 37.726682 C 	 1183.292940 mV
13:05:42:ST3_smx:INFO:	PROCESS 2: Checking channel response with internal pulse
13:05:42:ST3_smx:INFO:		Electrons
13:05:42:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
13:05:44:ST3_smx:INFO:	----> Checking Analog response
13:05:44:ST3_smx:INFO:	----> Checking broken channels
13:05:44:ST3_smx:INFO:	Total # broken ch: 0
13:05:44:ST3_smx:INFO:	List FAST: []
13:05:44:ST3_smx:INFO:	List SLOW: []
13:05:44:ST3_smx:INFO:		Holes
13:05:44:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
13:05:46:ST3_smx:INFO:	----> Checking Analog response
13:05:46:ST3_smx:INFO:	----> Checking broken channels
13:05:46:ST3_smx:INFO:	Total # broken ch: 0
13:05:46:ST3_smx:INFO:	List FAST: []
13:05:46:ST3_smx:INFO:	List SLOW: []
13:05:46:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:05:46:febtest:INFO:	0-0 | XA-000-08-002-000-007-067-03 |  44.1 | 1165.6
13:05:47:febtest:INFO:	0-1 | XA-000-08-002-000-007-013-06 |  50.4 | 1135.9
13:05:47:febtest:INFO:	0-2 | XA-000-08-002-000-007-044-08 |  28.2 | 1230.3
13:05:47:febtest:INFO:	0-3 | XA-000-08-002-000-007-034-08 |  40.9 | 1177.4
13:05:47:febtest:INFO:	0-4 | XA-000-08-002-000-007-038-08 |  37.7 | 1201.0
13:05:48:febtest:INFO:	0-5 | XA-000-08-002-000-007-043-08 |  34.6 | 1212.7
13:05:48:febtest:INFO:	0-6 | XA-000-08-002-000-007-028-01 |  44.1 | 1171.5
13:05:48:febtest:INFO:	0-7 | XA-000-08-002-000-007-056-15 |  40.9 | 1171.5
13:05:48:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:05:52:ST3_smx:INFO:	chip: 0-4 	 34.556970 C 	 1195.082160 mV
13:05:52:ST3_smx:INFO:	PROCESS 2: Checking channel response with internal pulse
13:05:52:ST3_smx:INFO:		Electrons
13:05:52:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
13:05:54:ST3_smx:INFO:	----> Checking Analog response
13:05:54:ST3_smx:INFO:	----> Checking broken channels
13:05:54:ST3_smx:INFO:	Total # broken ch: 0
13:05:54:ST3_smx:INFO:	List FAST: []
13:05:54:ST3_smx:INFO:	List SLOW: []
13:05:54:ST3_smx:INFO:		Holes
13:05:54:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
13:05:56:ST3_smx:INFO:	----> Checking Analog response
13:05:56:ST3_smx:INFO:	----> Checking broken channels
13:05:56:ST3_smx:INFO:	Total # broken ch: 0
13:05:56:ST3_smx:INFO:	List FAST: []
13:05:56:ST3_smx:INFO:	List SLOW: []
13:05:56:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:05:57:febtest:INFO:	0-0 | XA-000-08-002-000-007-067-03 |  44.1 | 1165.6
13:05:57:febtest:INFO:	0-1 | XA-000-08-002-000-007-013-06 |  50.4 | 1130.0
13:05:57:febtest:INFO:	0-2 | XA-000-08-002-000-007-044-08 |  28.2 | 1230.3
13:05:57:febtest:INFO:	0-3 | XA-000-08-002-000-007-034-08 |  40.9 | 1177.4
13:05:58:febtest:INFO:	0-4 | XA-000-08-002-000-007-038-08 |  37.7 | 1195.1
13:05:58:febtest:INFO:	0-5 | XA-000-08-002-000-007-043-08 |  34.6 | 1212.7
13:05:58:febtest:INFO:	0-6 | XA-000-08-002-000-007-028-01 |  44.1 | 1165.6
13:05:58:febtest:INFO:	0-7 | XA-000-08-002-000-007-056-15 |  40.9 | 1171.5
13:05:59:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:06:02:ST3_smx:INFO:	chip: 0-5 	 28.225000 C 	 1218.600960 mV
13:06:02:ST3_smx:INFO:	PROCESS 2: Checking channel response with internal pulse
13:06:02:ST3_smx:INFO:		Electrons
13:06:02:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
13:06:04:ST3_smx:INFO:	----> Checking Analog response
13:06:04:ST3_smx:INFO:	----> Checking broken channels
13:06:04:ST3_smx:INFO:	Total # broken ch: 0
13:06:04:ST3_smx:INFO:	List FAST: []
13:06:04:ST3_smx:INFO:	List SLOW: []
13:06:04:ST3_smx:INFO:		Holes
13:06:04:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
13:06:06:ST3_smx:INFO:	----> Checking Analog response
13:06:06:ST3_smx:INFO:	----> Checking broken channels
13:06:07:ST3_smx:INFO:	Total # broken ch: 0
13:06:07:ST3_smx:INFO:	List FAST: []
13:06:07:ST3_smx:INFO:	List SLOW: []
13:06:07:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:06:07:febtest:INFO:	0-0 | XA-000-08-002-000-007-067-03 |  44.1 | 1165.6
13:06:07:febtest:INFO:	0-1 | XA-000-08-002-000-007-013-06 |  53.6 | 1130.0
13:06:07:febtest:INFO:	0-2 | XA-000-08-002-000-007-044-08 |  28.2 | 1230.3
13:06:08:febtest:INFO:	0-3 | XA-000-08-002-000-007-034-08 |  40.9 | 1177.4
13:06:08:febtest:INFO:	0-4 | XA-000-08-002-000-007-038-08 |  37.7 | 1195.1
13:06:08:febtest:INFO:	0-5 | XA-000-08-002-000-007-043-08 |  31.4 | 1218.6
13:06:08:febtest:INFO:	0-6 | XA-000-08-002-000-007-028-01 |  47.3 | 1171.5
13:06:09:febtest:INFO:	0-7 | XA-000-08-002-000-007-056-15 |  44.1 | 1171.5
13:06:09:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:06:12:ST3_smx:INFO:	chip: 0-6 	 47.250730 C 	 1153.732915 mV
13:06:12:ST3_smx:INFO:	PROCESS 2: Checking channel response with internal pulse
13:06:13:ST3_smx:INFO:		Electrons
13:06:13:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
13:06:14:ST3_smx:INFO:	----> Checking Analog response
13:06:14:ST3_smx:INFO:	----> Checking broken channels
13:06:15:ST3_smx:INFO:	Total # broken ch: 0
13:06:15:ST3_smx:INFO:	List FAST: []
13:06:15:ST3_smx:INFO:	List SLOW: []
13:06:15:ST3_smx:INFO:		Holes
13:06:15:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
13:06:17:ST3_smx:INFO:	----> Checking Analog response
13:06:17:ST3_smx:INFO:	----> Checking broken channels
13:06:17:ST3_smx:INFO:	Total # broken ch: 0
13:06:17:ST3_smx:INFO:	List FAST: []
13:06:17:ST3_smx:INFO:	List SLOW: []
13:06:17:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:06:17:febtest:INFO:	0-0 | XA-000-08-002-000-007-067-03 |  44.1 | 1165.6
13:06:17:febtest:INFO:	0-1 | XA-000-08-002-000-007-013-06 |  53.6 | 1135.9
13:06:18:febtest:INFO:	0-2 | XA-000-08-002-000-007-044-08 |  28.2 | 1224.5
13:06:18:febtest:INFO:	0-3 | XA-000-08-002-000-007-034-08 |  40.9 | 1177.4
13:06:18:febtest:INFO:	0-4 | XA-000-08-002-000-007-038-08 |  37.7 | 1189.2
13:06:18:febtest:INFO:	0-5 | XA-000-08-002-000-007-043-08 |  31.4 | 1218.6
13:06:19:febtest:INFO:	0-6 | XA-000-08-002-000-007-028-01 |  47.3 | 1147.8
13:06:19:febtest:INFO:	0-7 | XA-000-08-002-000-007-056-15 |  44.1 | 1165.6
13:06:19:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
13:06:23:ST3_smx:INFO:	chip: 0-7 	 44.073563 C 	 1147.806000 mV
13:06:23:ST3_smx:INFO:	PROCESS 2: Checking channel response with internal pulse
13:06:23:ST3_smx:INFO:		Electrons
13:06:23:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
13:06:25:ST3_smx:INFO:	----> Checking Analog response
13:06:25:ST3_smx:INFO:	----> Checking broken channels
13:06:25:ST3_smx:INFO:	Total # broken ch: 0
13:06:25:ST3_smx:INFO:	List FAST: []
13:06:25:ST3_smx:INFO:	List SLOW: []
13:06:25:ST3_smx:INFO:		Holes
13:06:25:ST3_smx:INFO:			Injected pulses: 125LSB, amp_cal 7.000000 fC
13:06:27:ST3_smx:INFO:	----> Checking Analog response
13:06:27:ST3_smx:INFO:	----> Checking broken channels
13:06:27:ST3_smx:INFO:	Total # broken ch: 0
13:06:27:ST3_smx:INFO:	List FAST: []
13:06:27:ST3_smx:INFO:	List SLOW: []
13:06:27:febtest:INFO:	 Add. | ASIC-ID                      | T [C] | Vddm [mV]
13:06:27:febtest:INFO:	0-0 | XA-000-08-002-000-007-067-03 |  44.1 | 1165.6
13:06:27:febtest:INFO:	0-1 | XA-000-08-002-000-007-013-06 |  53.6 | 1130.0
13:06:28:febtest:INFO:	0-2 | XA-000-08-002-000-007-044-08 |  28.2 | 1224.5
13:06:28:febtest:INFO:	0-3 | XA-000-08-002-000-007-034-08 |  40.9 | 1171.5
13:06:28:febtest:INFO:	0-4 | XA-000-08-002-000-007-038-08 |  37.7 | 1195.1
13:06:28:febtest:INFO:	0-5 | XA-000-08-002-000-007-043-08 |  31.4 | 1212.7
13:06:29:febtest:INFO:	0-6 | XA-000-08-002-000-007-028-01 |  47.3 | 1147.8
13:06:29:febtest:INFO:	0-7 | XA-000-08-002-000-007-056-15 |  47.3 | 1141.9
############################################################
#                   S U M M A R Y                          #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_01-13_04_52', 'OPERATOR': 'Robert V.; ', 'PROJECT': 'Production', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-007-056-15', 'FUSED_ID': 6359364699116565391, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.448', '1.6520', '1.846', '2.4440', '7.000', '1.5580', '7.000', '1.5580'], 'VI_aInit': ['2.450', '2.0040', '1.850', '1.4670', '7.000', '1.5480', '7.000', '1.5480'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 125, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 125, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

13:06:40:ST3_Shared:INFO:	/home/cbm/public_html/Production_LogDir//FEB/FEB_6019/TestDate_2023_11_01-13_04_52/