XA-000-08-002-000-006-127-07 09.11.23 10:45:25
ADC4
SMX_7
CSA
Calibration
ADC
CSA
Info
10:45:25:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:45:25:ST3_Shared:INFO: -------------------------Microcable-------------------------
10:45:25:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:45:26:smx_tester:INFO: Scanning setup
10:45:26:elinks:INFO: Disabling clock on downlink 0
10:45:26:elinks:INFO: Disabling clock on downlink 1
10:45:26:elinks:INFO: Disabling clock on downlink 2
10:45:26:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:45:26:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:45:27:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 0
10:45:27:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:45:27:elinks:INFO: Disabling clock on downlink 0
10:45:27:elinks:INFO: Disabling clock on downlink 1
10:45:27:elinks:INFO: Disabling clock on downlink 2
10:45:27:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:45:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:45:27:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:45:27:elinks:INFO: Disabling clock on downlink 0
10:45:27:elinks:INFO: Disabling clock on downlink 1
10:45:27:elinks:INFO: Disabling clock on downlink 2
10:45:27:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:45:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:45:27:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:45:27:setup_element:INFO: Scanning clock phase
10:45:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:45:27:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
10:45:27:setup_element:INFO: Clock phase scan results for group 0, downlink 0
10:45:27:setup_element:INFO: Eye window for uplink 0 : _____________________________________________________XXXXXXX____________________
Clock Delay: 16
10:45:27:setup_element:INFO: Setting the clock phase to 16 for group 0, downlink 0
10:45:27:setup_element:INFO: Scanning data phases
10:45:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:45:27:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
10:45:32:setup_element:INFO: Data phase scan results for group 0, downlink 0
10:45:32:setup_element:INFO: Eye window for uplink 0 : ___XXXXX________________________________
Data delay found: 25
10:45:32:setup_element:INFO: Setting the data phase to 25 for uplink 0
10:45:32:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 0
Uplinks: [0]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 16
Window Length: 73
Eye Windows:
Uplink 0: _____________________________________________________XXXXXXX____________________
Data phase characteristics:
Uplink 0:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
]
10:45:32:setup_element:INFO: Beginning SMX ASICs map scan
10:45:32:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:45:32:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
10:45:32:master:INFO: Setting encoding mode EOS for groups [0], downlinks [0]
10:45:32:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [0]
10:45:32:uplink:INFO: Setting uplinks mask [0]
10:45:34:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 0
10:45:35:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 0
Uplinks: [0]
ASICs Map:
ASIC address 0x7: (ASIC uplink, uplink): (0, 0)
Clock Phase Characteristic:
Optimal Phase: 16
Window Length: 73
Eye Windows:
Uplink 0: _____________________________________________________XXXXXXX____________________
Data phase characteristics:
Uplink 0:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
10:45:35:setup_element:INFO: Performing Elink synchronization
10:45:35:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:45:35:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
10:45:35:master:INFO: Setting encoding mode EOS for groups [0], downlinks [0]
10:45:35:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [0]
10:45:35:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 0
10:45:35:uplink:INFO: Enabling uplinks [0]
10:45:35:ST3_emu:INFO: Number of chips: 1
10:45:35:ST3_emu:INFO: Chip address: 0x7
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_7 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_7
10:45:36:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
============== Starting SMX ID burn ==============
10:45:39:asictest:WARNING: Fused ID is not zero 6359364699116562423
10:45:40:asictest:INFO: Starting ADC calibration/scan
10:45:46:asictest:INFO: 0, 51, 0.000000
10:45:51:asictest:INFO: 1, 60, 0.300000
10:45:57:asictest:INFO: 2, 84, 0.600000
10:46:03:asictest:INFO: 3, 130, 0.900000
10:46:09:asictest:INFO: 4, 181, 1.200000
10:46:15:asictest:INFO: 5, 206, 1.300000
10:46:20:asictest:INFO: T [C] Vddm[mV] CSA [mV] AUX [mV]
10:46:21:asictest:INFO: 13.53 1189.80 856.26 352.87
10:46:22:ST3_smx:INFO: chip: 0-7 13.533508 C 1189.797519 mV
10:46:22:ST3_smx:INFO: # loops 0
10:46:24:ST3_smx:INFO: # loops 1
10:46:25:ST3_smx:INFO: # loops 2
10:46:27:ST3_smx:INFO: # loops 3
10:46:28:ST3_smx:INFO: # loops 4
10:46:30:ST3_smx:INFO: Total # of broken channels: 0
10:46:30:ST3_smx:INFO: List of broken channels: []
10:46:30:ST3_smx:INFO: Total # of broken channels: 0
10:46:30:ST3_smx:INFO: List of broken channels: []
10:46:31:asictest:INFO: Starting CSA scan -
10:46:32:asictest:INFO: 0, 0.061600
10:46:32:asictest:INFO: 9, 0.141000
10:46:33:asictest:INFO: 18, 0.212800
10:46:34:asictest:INFO: 27, 0.280300
10:46:35:asictest:INFO: 36, 0.348500
10:46:35:asictest:INFO: 45, 0.412800
10:46:36:asictest:INFO: 54, 0.469000
10:46:37:asictest:INFO: 63, 0.509800
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : Microcable
TEST_DATE : 2023_11_09-10_45_25
OPERATOR : Robert V.;
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID : 0000L000-M000 | index: (1/8)
---------------------------------------
---------------------------------------
ASIC_CONFIG_PARAMETERS
HW_ADDR : 0x7 | VERS_NO : 2.2
ASIC_ID : XA-000-08-002-000-006-127-07 | FUSED_ID : 6359364699116562423
IC_TEMP : 7.08 | VDDM : 1104.29 | AUX_INT : 62.31 | CsaBias : 214.04
CONF_FAIL_REG : 0
CSA_BIAS : 15
THR2_GLB : 30
ADC_VREF_P : 58 | ADC_VREF_N : 30 | ADC_VREF_T : 128 | ADC_VREF_TR : 122
ADC_Chi2/NDF : 4.34275e-04 / 1
ADC_P0 : 0.00000e+00 ± 2.08393e-02
ADC_P1 : 7.84564e-03 ± 3.23294e-04
ADC_P2 : -7.18841e-06 ± 1.79694e-06
CSA_Chi2/NDF : 7.96986e-05 / 1
CSA_P0 : 6.04500e-02 ± 3.36015e-03
CSA_P1 : 9.10595e-03 ± 2.49162e-04
CSA_P2 : -3.02028e-05 ± 3.80277e-06
---------------------------------------
N_BROKEN_DISC : 0 | N_BROKEN_FAST : []
N_BROKEN_CABLE : 0
LIST_OF_BROKEN_CABLES : []
---------------------------------------
VI_before_Init : ['1.199', '0.1378', '1.800', '0.1088', '1.801', '0.1445', '7.000', '0.6893']
VI_after__Init : ['1.200', '0.1386', '1.800', '0.1079', '1.800', '0.1442', '7.000', '0.6902']
VI_at__the_End : ['1.200', '0.5110', '1.800', '0.0730', '1.800', '0.1688', '7.000', '0.6905']
10:47:02:ST3_Shared:INFO: /home/cbm/public_html/Production_LogDir/Microcable/XA-000-08-002-000-006-127-07//TestDate_2023_11_09-10_45_25/
Comment
Irakli Testkabel beide Lagen gebondet