XA-000-08-002-000-006-131-01    09.11.23 10:47:55

ADC4
cADCscan.png
SMX_7
SMX_7.png
CSA
cCSAscan.png
Calibration
ADC
p0.svg
p1.svg
CSA
p0.svg
p2.svg
p1.svg
Report.txt
            10:47:55:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:47:55:ST3_Shared:INFO:	-------------------------Microcable-------------------------
10:47:55:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:47:57:smx_tester:INFO:	Scanning setup
10:47:57:elinks:INFO:	Disabling clock on downlink 0
10:47:57:elinks:INFO:	Disabling clock on downlink 1
10:47:57:elinks:INFO:	Disabling clock on downlink 2
10:47:57:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:47:57:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
10:47:57:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 0
10:47:57:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:47:57:elinks:INFO:	Disabling clock on downlink 0
10:47:57:elinks:INFO:	Disabling clock on downlink 1
10:47:57:elinks:INFO:	Disabling clock on downlink 2
10:47:57:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:47:57:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
10:47:57:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:47:57:elinks:INFO:	Disabling clock on downlink 0
10:47:57:elinks:INFO:	Disabling clock on downlink 1
10:47:57:elinks:INFO:	Disabling clock on downlink 2
10:47:57:setup_element:INFO:	Checking SOS, encoding_mode: SOS
10:47:57:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
10:47:57:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
10:47:57:setup_element:INFO:	Scanning clock phase
10:47:57:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
10:47:57:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [0]
10:47:58:setup_element:INFO:	Clock phase scan results for group 0, downlink 0
10:47:58:setup_element:INFO:	Eye window for uplink 0 : _____________________________________________________XXXXXXX____________________
Clock Delay: 16
10:47:58:setup_element:INFO:	Setting the clock phase to 16 for group 0, downlink 0
10:47:58:setup_element:INFO:	Scanning data phases
10:47:58:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
10:47:58:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [0]
10:48:03:setup_element:INFO:	Data phase scan results for group 0, downlink 0
10:48:03:setup_element:INFO:	Eye window for uplink 0 : ___XXXXX________________________________
Data delay found: 25
10:48:03:setup_element:INFO:	Setting the data phase to 25 for uplink 0
10:48:03:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 0
  Uplinks: [0]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 16
    Window Length: 73
    Eye Windows:
      Uplink  0: _____________________________________________________XXXXXXX____________________
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 25
      Window Length: 35
      Eye Window: ___XXXXX________________________________
]
10:48:03:setup_element:INFO:	Beginning SMX ASICs map scan
10:48:03:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
10:48:03:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [0]
10:48:03:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [0]
10:48:03:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [0]
10:48:03:uplink:INFO:	Setting uplinks mask [0]
10:48:04:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 0
10:48:05:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 0
  Uplinks: [0]
  ASICs Map:
    ASIC address 0x7: (ASIC uplink, uplink): (0, 0)
  Clock Phase Characteristic:
    Optimal Phase: 16
    Window Length: 73
    Eye Windows:
      Uplink  0: _____________________________________________________XXXXXXX____________________
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 25
      Window Length: 35
      Eye Window: ___XXXXX________________________________

10:48:05:setup_element:INFO:	Performing Elink synchronization
10:48:05:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
10:48:05:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [0]
10:48:05:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [0]
10:48:05:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [0]
10:48:05:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 0
10:48:05:uplink:INFO:	Enabling uplinks [0]
10:48:05:ST3_emu:INFO:	Number of chips: 1
10:48:05:ST3_emu:INFO:	Chip address:  	0x7
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_7 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_7
10:48:06:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
 ============== Starting SMX ID burn ==============
10:48:10:asictest:WARNING:	Fused ID is not zero 6359364699116562481
10:48:10:asictest:INFO:	 Starting ADC calibration/scan 
10:48:16:asictest:INFO:	0,	14,	0.000000
10:48:22:asictest:INFO:	1,	49,	0.300000
10:48:28:asictest:INFO:	2,	80,	0.600000
10:48:33:asictest:INFO:	3,	125,	0.900000
10:48:39:asictest:INFO:	4,	171,	1.200000
10:48:45:asictest:INFO:	5,	189,	1.300000
10:48:50:asictest:INFO:	T [C] Vddm[mV] CSA [mV] AUX [mV]
10:48:50:asictest:INFO:	 26.55 1194.99  824.64   78.47
10:48:52:ST3_smx:INFO:	chip: 0-7 	 26.553271 C 	 1194.993684 mV
10:48:52:ST3_smx:INFO:	# loops 0
10:48:53:ST3_smx:INFO:	# loops 1
10:48:55:ST3_smx:INFO:	# loops 2
10:48:57:ST3_smx:INFO:	# loops 3
10:48:58:ST3_smx:INFO:	# loops 4
10:49:00:ST3_smx:INFO:	Total # of broken channels: 0
10:49:00:ST3_smx:INFO:	List of broken channels: []
10:49:00:ST3_smx:INFO:	Total # of broken channels: 0
10:49:00:ST3_smx:INFO:	List of broken channels: []
10:49:01:asictest:INFO:	 Starting CSA scan -
10:49:02:asictest:INFO:	0,	0.063200
10:49:02:asictest:INFO:	9,	0.147300
10:49:03:asictest:INFO:	18,	0.223200
10:49:04:asictest:INFO:	27,	0.295000
10:49:04:asictest:INFO:	36,	0.366700
10:49:05:asictest:INFO:	45,	0.434300
10:49:06:asictest:INFO:	54,	0.493900
10:49:07:asictest:INFO:	63,	0.538300
############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : Microcable
TEST_DATE : 2023_11_09-10_47_55
OPERATOR  : Robert V.; 
SITE      : GSI
SETUP     : GSI_TEST_SETUP_1
Set-ID    : 0000L000-M000 | index: (1/8)
---------------------------------------
---------------------------------------
ASIC_CONFIG_PARAMETERS
  HW_ADDR : 0x7 | VERS_NO : 2.2
  ASIC_ID : XA-000-08-002-000-006-131-01 | FUSED_ID : 6359364699116562481
  IC_TEMP :   19.61 | VDDM : 1127.51 | AUX_INT :    7.90 | CsaBias :  171.23
  CONF_FAIL_REG : 0
  CSA_BIAS : 15
  THR2_GLB : 30
  ADC_VREF_P : 58 | ADC_VREF_N : 30 | ADC_VREF_T : 128 | ADC_VREF_TR : 122
  ADC_Chi2/NDF : 5.41253e-05 / 1
  ADC_P0  : 0.00000e+00 ± 7.35699e-03
  ADC_P1  : 7.90062e-03 ± 1.27379e-04
  ADC_P2  : -5.33539e-06 ± 7.64305e-07
  CSA_Chi2/NDF : 7.12739e-05 / 1
  CSA_P0  : 6.21958e-02 ± 3.17760e-03
  CSA_P1  : 9.61144e-03 ± 2.35625e-04
  CSA_P2  : -3.15476e-05 ± 3.59617e-06
---------------------------------------
N_BROKEN_DISC :  0 | N_BROKEN_FAST :  []
N_BROKEN_CABLE : 0
LIST_OF_BROKEN_CABLES : []
---------------------------------------
VI_before_Init : ['1.199', '0.3049', '1.800', '0.0856', '1.801', '0.1544', '7.001', '0.6898']
VI_after__Init : ['1.200', '0.3047', '1.800', '0.0851', '1.800', '0.1513', '7.000', '0.6905']
VI_at__the_End : ['1.200', '0.5348', '1.800', '0.0727', '1.800', '0.1675', '7.000', '0.6905']
10:49:12:ST3_Shared:INFO:	/home/cbm/public_html/Production_LogDir/Microcable/XA-000-08-002-000-006-131-01//TestDate_2023_11_09-10_47_55/

          
Comment.txt
Irakli Testkabel beide Lagen gebondet