XA-000-08-002-001-008-114-06    01.09.23 09:00:39

ADC4
cADCscan.png
SMX_7
SMX_7.png
CSA
cCSAscan.png
Calibration
ADC
p0.svg
p1.svg
CSA
p0.svg
p2.svg
p1.svg
Report.txt
            09:00:39:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:00:39:ST3_Shared:INFO:	-------------------------Microcable-------------------------
09:00:39:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:00:41:smx_tester:INFO:	Scanning setup
09:00:41:elinks:INFO:	Disabling clock on downlink 0
09:00:41:elinks:INFO:	Disabling clock on downlink 1
09:00:41:elinks:INFO:	Disabling clock on downlink 2
09:00:41:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:00:41:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
09:00:41:setup_element:INFO:	SOS detected for group 0, downlink 0, uplink 0
09:00:41:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:00:41:elinks:INFO:	Disabling clock on downlink 0
09:00:41:elinks:INFO:	Disabling clock on downlink 1
09:00:41:elinks:INFO:	Disabling clock on downlink 2
09:00:41:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:00:41:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
09:00:41:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:00:41:elinks:INFO:	Disabling clock on downlink 0
09:00:41:elinks:INFO:	Disabling clock on downlink 1
09:00:41:elinks:INFO:	Disabling clock on downlink 2
09:00:41:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:00:41:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:00:41:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:00:41:setup_element:INFO:	Scanning clock phase
09:00:41:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
09:00:41:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [0]
09:00:42:setup_element:INFO:	Clock phase scan results for group 0, downlink 0
09:00:42:setup_element:INFO:	Eye window for uplink 0 : _____________________________________________________XXXXXX_____________________
Clock Delay: 15
09:00:42:setup_element:INFO:	Setting the clock phase to 15 for group 0, downlink 0
09:00:42:setup_element:INFO:	Scanning data phases
09:00:42:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
09:00:42:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [0]
09:00:47:setup_element:INFO:	Data phase scan results for group 0, downlink 0
09:00:47:setup_element:INFO:	Eye window for uplink 0 : _____XXX________________________________
Data delay found: 26
09:00:47:setup_element:INFO:	Setting the data phase to 26 for uplink 0
09:00:47:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 0
  Uplinks: [0]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 15
    Window Length: 74
    Eye Windows:
      Uplink  0: _____________________________________________________XXXXXX_____________________
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 26
      Window Length: 37
      Eye Window: _____XXX________________________________
]
09:00:47:setup_element:INFO:	Beginning SMX ASICs map scan
09:00:47:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
09:00:47:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [0]
09:00:47:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [0]
09:00:47:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [0]
09:00:47:uplink:INFO:	Setting uplinks mask [0]
09:00:48:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 0
09:00:49:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 0
  Uplinks: [0]
  ASICs Map:
    ASIC address 0x7: (ASIC uplink, uplink): (0, 0)
  Clock Phase Characteristic:
    Optimal Phase: 15
    Window Length: 74
    Eye Windows:
      Uplink  0: _____________________________________________________XXXXXX_____________________
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 26
      Window Length: 37
      Eye Window: _____XXX________________________________

09:00:49:setup_element:INFO:	Performing Elink synchronization
09:00:49:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
09:00:49:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [0]
09:00:49:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [0]
09:00:49:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [0]
09:00:49:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 0
09:00:49:uplink:INFO:	Enabling uplinks [0]
09:00:49:ST3_emu:INFO:	Number of chips: 1
09:00:49:ST3_emu:INFO:	Chip address:  	0x7
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_7 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_7
09:00:50:ST3_smx:INFO:	PROCESS 1: Configuring AFE with typical values
 ============== Starting SMX ID burn ==============
09:00:54:asictest:WARNING:	Fused ID is not zero 6359364699117618982
09:00:54:asictest:INFO:	 Starting ADC calibration/scan 
09:01:00:asictest:INFO:	0,	51,	0.000000
09:01:06:asictest:INFO:	1,	61,	0.300000
09:01:12:asictest:INFO:	2,	85,	0.600000
09:01:17:asictest:INFO:	3,	132,	0.900000
09:01:23:asictest:INFO:	4,	182,	1.200000
09:01:29:asictest:INFO:	5,	204,	1.300000
09:01:34:asictest:INFO:	T [C] Vddm[mV] CSA [mV] AUX [mV]
09:01:35:asictest:INFO:	 16.15 1195.02  882.70  385.96
09:01:36:ST3_smx:INFO:	chip: 0-7 	 16.153241 C 	 1195.020094 mV
09:01:36:ST3_smx:INFO:	# loops 0
09:01:38:ST3_smx:INFO:	# loops 1
09:01:39:ST3_smx:INFO:	# loops 2
09:01:41:ST3_smx:INFO:	# loops 3
09:01:43:ST3_smx:INFO:	# loops 4
09:01:44:ST3_smx:INFO:	Total # of broken channels: 0
09:01:44:ST3_smx:INFO:	List of broken channels: []
09:01:44:ST3_smx:INFO:	Total # of broken channels: 0
09:01:44:ST3_smx:INFO:	List of broken channels: []
09:01:45:asictest:INFO:	 Starting CSA scan -
09:01:46:asictest:INFO:	0,	0.063400
09:01:47:asictest:INFO:	9,	0.144800
09:01:47:asictest:INFO:	18,	0.219700
09:01:48:asictest:INFO:	27,	0.289600
09:01:49:asictest:INFO:	36,	0.356800
09:01:49:asictest:INFO:	45,	0.425300
09:01:50:asictest:INFO:	54,	0.491300
09:01:51:asictest:INFO:	63,	0.539700
############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : Microcable
TEST_DATE : 2023_09_01-09_00_39
OPERATOR  : Olga B.; 
SITE      : GSI
SETUP     : GSI_TEST_SETUP_1
Set-ID    : 0000L000-M000 | side-N | index: (4/8)
---------------------------------------
---------------------------------------
ASIC_CONFIG_PARAMETERS
  HW_ADDR : 0x7 | VERS_NO : 2.2
  ASIC_ID : XA-000-08-002-001-008-114-06 | FUSED_ID : 6359364699117618982
  IC_TEMP :    9.70 | VDDM : 1122.92 | AUX_INT :  142.10 | CsaBias :  308.53
  CONF_FAIL_REG : 0
  CSA_BIAS : 15
  THR2_GLB : 30
  ADC_VREF_P : 58 | ADC_VREF_N : 30 | ADC_VREF_T : 128 | ADC_VREF_TR : 122
  ADC_Chi2/NDF : 1.75119e-04 / 1
  ADC_P0  : 0.00000e+00 ± 1.32333e-02
  ADC_P1  : 7.58902e-03 ± 2.09919e-04
  ADC_P2  : -5.78609e-06 ± 1.17266e-06
  CSA_Chi2/NDF : 5.81710e-05 / 1
  CSA_P0  : 6.38333e-02 ± 2.87069e-03
  CSA_P1  : 9.03810e-03 ± 2.12867e-04
  CSA_P2  : -2.27219e-05 ± 3.24884e-06
---------------------------------------
N_BROKEN_DISC :  0 | N_BROKEN_FAST :  []
N_BROKEN_CABLE : 0
LIST_OF_BROKEN_CABLES : []
---------------------------------------
VI_before_Init : ['1.199', '0.3546', '1.800', '0.0508', '1.800', '0.1407', '7.000', '0.6870']
VI_after__Init : ['1.199', '0.3544', '1.800', '0.0509', '1.800', '0.1402', '7.000', '0.6878']
VI_at__the_End : ['1.200', '0.5399', '1.800', '0.0715', '1.800', '0.1542', '7.000', '0.6882']
09:01:57:ST3_Shared:INFO:	/home/cbm/public_html/Production_LogDir/Microcable/XA-000-08-002-001-008-114-06//TestDate_2023_09_01-09_00_39/

          
Comment.txt
J076, UK module