XA-000-08-003-000-000-019-03 23.08.23 10:55:12
ADC4
SMX_7
CSA
Calibration
ADC
CSA
Info
10:55:12:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:55:12:ST3_Shared:INFO: -------------------------Microcable-------------------------
10:55:12:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:55:14:smx_tester:INFO: Scanning setup
10:55:14:elinks:INFO: Disabling clock on downlink 0
10:55:14:elinks:INFO: Disabling clock on downlink 1
10:55:14:elinks:INFO: Disabling clock on downlink 2
10:55:14:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:55:14:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:55:14:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 0
10:55:14:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:55:14:elinks:INFO: Disabling clock on downlink 0
10:55:14:elinks:INFO: Disabling clock on downlink 1
10:55:14:elinks:INFO: Disabling clock on downlink 2
10:55:14:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:55:14:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:55:14:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:55:14:elinks:INFO: Disabling clock on downlink 0
10:55:14:elinks:INFO: Disabling clock on downlink 1
10:55:14:elinks:INFO: Disabling clock on downlink 2
10:55:14:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:55:14:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:55:14:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:55:14:setup_element:INFO: Scanning clock phase
10:55:14:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:55:14:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
10:55:14:setup_element:INFO: Clock phase scan results for group 0, downlink 0
10:55:14:setup_element:INFO: Eye window for uplink 0 : ______________________________________________________XXXXXX____________________
Clock Delay: 16
10:55:14:setup_element:INFO: Setting the clock phase to 16 for group 0, downlink 0
10:55:14:setup_element:INFO: Scanning data phases
10:55:14:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:55:14:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
10:55:19:setup_element:INFO: Data phase scan results for group 0, downlink 0
10:55:19:setup_element:INFO: Eye window for uplink 0 : _____XXXXX______________________________
Data delay found: 27
10:55:19:setup_element:INFO: Setting the data phase to 27 for uplink 0
10:55:19:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 0
Uplinks: [0]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 16
Window Length: 74
Eye Windows:
Uplink 0: ______________________________________________________XXXXXX____________________
Data phase characteristics:
Uplink 0:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
]
10:55:19:setup_element:INFO: Beginning SMX ASICs map scan
10:55:19:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:55:19:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
10:55:19:master:INFO: Setting encoding mode EOS for groups [0], downlinks [0]
10:55:19:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [0]
10:55:19:uplink:INFO: Setting uplinks mask [0]
10:55:21:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 0
10:55:22:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 0
Uplinks: [0]
ASICs Map:
ASIC address 0x7: (ASIC uplink, uplink): (0, 0)
Clock Phase Characteristic:
Optimal Phase: 16
Window Length: 74
Eye Windows:
Uplink 0: ______________________________________________________XXXXXX____________________
Data phase characteristics:
Uplink 0:
Optimal Phase: 27
Window Length: 35
Eye Window: _____XXXXX______________________________
10:55:22:setup_element:INFO: Performing Elink synchronization
10:55:22:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:55:22:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
10:55:22:master:INFO: Setting encoding mode EOS for groups [0], downlinks [0]
10:55:22:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [0]
10:55:22:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 0
10:55:22:uplink:INFO: Enabling uplinks [0]
10:55:22:ST3_emu:INFO: Number of chips: 1
10:55:22:ST3_emu:INFO: Chip address: 0x7
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_7 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_7 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_7
10:55:23:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
============== Starting SMX ID burn ==============
10:55:27:asictest:WARNING: Fused ID is not zero 6359364699384971571
10:55:27:asictest:INFO: Starting ADC calibration/scan
10:55:33:asictest:INFO: 0, 0, 0.000000
10:55:39:asictest:INFO: 1, 41, 0.300000
10:55:44:asictest:INFO: 2, 80, 0.600000
10:55:50:asictest:INFO: 3, 124, 0.900000
10:55:56:asictest:INFO: 4, 171, 1.200000
10:56:02:asictest:INFO: 5, 187, 1.300000
10:56:07:asictest:INFO: T [C] Vddm[mV] CSA [mV] AUX [mV]
10:56:08:asictest:INFO: 18.90 1201.43 874.07 0.00
10:56:09:ST3_smx:INFO: chip: 0-7 18.904273 C 1201.425819 mV
10:56:09:ST3_smx:INFO: # loops 0
10:56:11:ST3_smx:INFO: # loops 1
10:56:13:ST3_smx:INFO: # loops 2
10:56:14:ST3_smx:INFO: # loops 3
10:56:16:ST3_smx:INFO: # loops 4
10:56:17:ST3_smx:INFO: Total # of broken channels: 0
10:56:17:ST3_smx:INFO: List of broken channels: []
10:56:17:ST3_smx:INFO: Total # of broken channels: 0
10:56:17:ST3_smx:INFO: List of broken channels: []
10:56:19:asictest:INFO: Starting CSA scan -
10:56:19:asictest:INFO: 0, 0.064400
10:56:20:asictest:INFO: 9, 0.145200
10:56:21:asictest:INFO: 18, 0.219900
10:56:21:asictest:INFO: 27, 0.291000
10:56:22:asictest:INFO: 36, 0.361100
10:56:23:asictest:INFO: 45, 0.434400
10:56:23:asictest:INFO: 54, 0.495900
10:56:24:asictest:INFO: 63, 0.541200
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : Microcable
TEST_DATE : 2023_08_23-10_55_12
OPERATOR : Kerstin S.; Oleksandr S.;
SITE : GSI
SETUP : GSI_TEST_SETUP_1
Set-ID : 0000L000-M000 | side-P | index: (1/8)
---------------------------------------
---------------------------------------
ASIC_CONFIG_PARAMETERS
HW_ADDR : 0x7 | VERS_NO : 2.2
ASIC_ID : XA-000-08-003-000-000-019-03 | FUSED_ID : 6359364699384971571
IC_TEMP : 8.47 | VDDM : 1114.19 | AUX_INT : 0.00 | CsaBias : 132.69
CONF_FAIL_REG : 0
CSA_BIAS : 15
THR2_GLB : 30
ADC_VREF_P : 58 | ADC_VREF_N : 30 | ADC_VREF_T : 128 | ADC_VREF_TR : 122
ADC_Chi2/NDF : 5.40442e-06 / 1
ADC_P0 : 0.00000e+00 ± 2.32474e-03
ADC_P1 : 7.89113e-03 ± 4.06804e-05
ADC_P2 : -5.05992e-06 ± 2.45800e-07
CSA_Chi2/NDF : 1.24828e-04 / 1
CSA_P0 : 6.29792e-02 ± 4.20523e-03
CSA_P1 : 9.26660e-03 ± 3.11826e-04
CSA_P2 : -2.52131e-05 ± 4.75917e-06
---------------------------------------
N_BROKEN_DISC : 0 | N_BROKEN_FAST : []
N_BROKEN_CABLE : 0
LIST_OF_BROKEN_CABLES : []
---------------------------------------
VI_before_Init : ['1.199', '0.3407', '1.800', '0.0747', '1.800', '0.1405', '7.000', '0.6893']
VI_after__Init : ['1.200', '0.3415', '1.800', '0.0742', '1.800', '0.1393', '7.000', '0.6905']
VI_at__the_End : ['1.200', '0.5406', '1.800', '0.0722', '1.800', '0.1636', '7.000', '0.6903']
10:56:50:ST3_Shared:INFO: /home/cbm/public_html/Test_LogDir/Microcable/XA-000-08-003-000-000-019-03//TestDate_2023_08_23-10_55_12/
Comment
J038 for test module, Pside