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FEB_1022 27.10.23 14:14:38
Info
14:13:51:ST3_hmp4040:INFO: ROHDE&SCHWARZ,HMP4040,110099,HW50020003/SW2.71
14:13:52:febtest:INFO: FEB8.2 selected
14:14:20:febtest:INFO: FEB 8-2 B @ GSI
Traceback (most recent call last):
File "./febtest.py", line 441, in NewSN
sn_number = int( self.leFEB_SN.text() )
ValueError: invalid literal for int() with base 10: ''
14:14:28:febtest:INFO: FEB 8-2 A @ GSI
14:14:33:smx_tester:INFO: Setting Elink clock mode to 160 MHz
14:14:38:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:14:38:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
14:14:38:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:14:38:febtest:INFO: Tsting FEB with SN 1022
14:14:40:smx_tester:INFO: Scanning setup
14:14:40:elinks:INFO: Disabling clock on downlink 0
14:14:40:elinks:INFO: Disabling clock on downlink 1
14:14:40:elinks:INFO: Disabling clock on downlink 2
14:14:40:elinks:INFO: Disabling clock on downlink 3
14:14:40:elinks:INFO: Disabling clock on downlink 4
14:14:40:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:14:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:14:40:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:14:40:elinks:INFO: Disabling clock on downlink 0
14:14:40:elinks:INFO: Disabling clock on downlink 1
14:14:40:elinks:INFO: Disabling clock on downlink 2
14:14:40:elinks:INFO: Disabling clock on downlink 3
14:14:40:elinks:INFO: Disabling clock on downlink 4
14:14:40:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:14:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:14:40:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:14:40:elinks:INFO: Disabling clock on downlink 0
14:14:40:elinks:INFO: Disabling clock on downlink 1
14:14:40:elinks:INFO: Disabling clock on downlink 2
14:14:40:elinks:INFO: Disabling clock on downlink 3
14:14:40:elinks:INFO: Disabling clock on downlink 4
14:14:40:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:14:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:14:40:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:14:40:elinks:INFO: Disabling clock on downlink 0
14:14:40:elinks:INFO: Disabling clock on downlink 1
14:14:40:elinks:INFO: Disabling clock on downlink 2
14:14:40:elinks:INFO: Disabling clock on downlink 3
14:14:40:elinks:INFO: Disabling clock on downlink 4
14:14:40:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:14:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:14:41:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 24
14:14:41:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 25
14:14:41:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 26
14:14:41:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 27
14:14:41:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 28
14:14:41:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 29
14:14:41:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 30
14:14:41:setup_element:INFO: SOS detected for group 0, downlink 3, uplink 31
14:14:41:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:14:41:elinks:INFO: Disabling clock on downlink 0
14:14:41:elinks:INFO: Disabling clock on downlink 1
14:14:41:elinks:INFO: Disabling clock on downlink 2
14:14:41:elinks:INFO: Disabling clock on downlink 3
14:14:41:elinks:INFO: Disabling clock on downlink 4
14:14:41:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:14:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:14:41:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:14:41:setup_element:INFO: Scanning clock phase
14:14:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:14:41:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:14:41:setup_element:INFO: Clock phase scan results for group 0, downlink 3
14:14:41:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXXXX___
Clock Delay: 33
14:14:41:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXXXX___
Clock Delay: 33
14:14:41:setup_element:INFO: Eye window for uplink 26: _______________________________________________________________________XXXXX____
Clock Delay: 33
14:14:41:setup_element:INFO: Eye window for uplink 27: _______________________________________________________________________XXXXX____
Clock Delay: 33
14:14:41:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
14:14:41:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
14:14:41:setup_element:INFO: Eye window for uplink 30: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:14:41:setup_element:INFO: Eye window for uplink 31: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:14:41:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 3
14:14:41:setup_element:INFO: Scanning data phases
14:14:41:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:14:41:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:14:46:setup_element:INFO: Data phase scan results for group 0, downlink 3
14:14:46:setup_element:INFO: Eye window for uplink 24: _______________________________XXXXX____
Data delay found: 13
14:14:46:setup_element:INFO: Eye window for uplink 25: ___________________________________XXXXX
Data delay found: 17
14:14:46:setup_element:INFO: Eye window for uplink 26: ____________________________XXXXXX______
Data delay found: 10
14:14:46:setup_element:INFO: Eye window for uplink 27: _________________________________XXXXXXX
Data delay found: 16
14:14:46:setup_element:INFO: Eye window for uplink 28: _________________________________XXXXX__
Data delay found: 15
14:14:46:setup_element:INFO: Eye window for uplink 29: X___________________________________XXXX
Data delay found: 18
14:14:46:setup_element:INFO: Eye window for uplink 30: _________________________________XXXXXX_
Data delay found: 15
14:14:46:setup_element:INFO: Eye window for uplink 31: __________________________________XXXX__
Data delay found: 15
14:14:46:setup_element:INFO: Setting the data phase to 13 for uplink 24
14:14:46:setup_element:INFO: Setting the data phase to 17 for uplink 25
14:14:46:setup_element:INFO: Setting the data phase to 10 for uplink 26
14:14:46:setup_element:INFO: Setting the data phase to 16 for uplink 27
14:14:46:setup_element:INFO: Setting the data phase to 15 for uplink 28
14:14:46:setup_element:INFO: Setting the data phase to 18 for uplink 29
14:14:46:setup_element:INFO: Setting the data phase to 15 for uplink 30
14:14:46:setup_element:INFO: Setting the data phase to 15 for uplink 31
14:14:46:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 3
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 73
Eye Windows:
Uplink 24: _______________________________________________________________________XXXXXX___
Uplink 25: _______________________________________________________________________XXXXXX___
Uplink 26: _______________________________________________________________________XXXXX____
Uplink 27: _______________________________________________________________________XXXXX____
Uplink 28: _______________________________________________________________________XXXXXXX__
Uplink 29: _______________________________________________________________________XXXXXXX__
Uplink 30: _________________________________________________________________________XXXXX__
Uplink 31: _________________________________________________________________________XXXXX__
Data phase characteristics:
Uplink 24:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 25:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 26:
Optimal Phase: 10
Window Length: 34
Eye Window: ____________________________XXXXXX______
Uplink 27:
Optimal Phase: 16
Window Length: 33
Eye Window: _________________________________XXXXXXX
Uplink 28:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 29:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 30:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 31:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
]
14:14:46:setup_element:INFO: Beginning SMX ASICs map scan
14:14:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:14:46:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:14:46:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
14:14:46:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
14:14:46:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
14:14:46:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 24
14:14:46:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 25
14:14:47:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 26
14:14:47:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 27
14:14:47:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 28
14:14:47:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 29
14:14:47:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 30
14:14:48:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 31
14:14:49:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 3
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x1: (ASIC uplink, uplink): (0, 24), (1, 25)
ASIC address 0x3: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x5: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x7: (ASIC uplink, uplink): (0, 30), (1, 31)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 73
Eye Windows:
Uplink 24: _______________________________________________________________________XXXXXX___
Uplink 25: _______________________________________________________________________XXXXXX___
Uplink 26: _______________________________________________________________________XXXXX____
Uplink 27: _______________________________________________________________________XXXXX____
Uplink 28: _______________________________________________________________________XXXXXXX__
Uplink 29: _______________________________________________________________________XXXXXXX__
Uplink 30: _________________________________________________________________________XXXXX__
Uplink 31: _________________________________________________________________________XXXXX__
Data phase characteristics:
Uplink 24:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 25:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 26:
Optimal Phase: 10
Window Length: 34
Eye Window: ____________________________XXXXXX______
Uplink 27:
Optimal Phase: 16
Window Length: 33
Eye Window: _________________________________XXXXXXX
Uplink 28:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 29:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 30:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 31:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
14:14:49:setup_element:INFO: Performing Elink synchronization
14:14:49:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:14:49:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [3]
14:14:49:master:INFO: Setting encoding mode EOS for groups [0], downlinks [3]
14:14:49:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [3]
14:14:49:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 3
14:14:49:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
14:14:49:ST3_emu:INFO: Number of chips: 4
14:14:49:ST3_emu:INFO: Chip address: 0x1
14:14:49:ST3_emu:INFO: Chip address: 0x3
14:14:49:ST3_emu:INFO: Chip address: 0x5
14:14:49:ST3_emu:INFO: Chip address: 0x7
14:14:50:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:14:50:febtest:INFO: 0-1 | XA-000-08-003-000-002-229-06 | 31.4 | 1212.7
14:14:51:febtest:INFO: 0-3 | XA-000-08-003-000-000-140-14 | 60.0 | 1118.1
14:14:51:febtest:INFO: 0-5 | XA-000-08-001-064-042-064-12 | 44.1 | 1183.3
14:14:51:febtest:INFO: 0-7 | XA-000-08-001-064-042-056-00 | 37.7 | 1206.9
14:14:51:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:14:56:ST3_smx:INFO: chip: 0-1 34.556970 C 1189.190035 mV
14:14:56:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
14:14:56:ST3_smx:INFO: Electrons
14:14:56:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:14:59:ST3_smx:INFO: ----> Checking Analog response
14:14:59:ST3_smx:INFO: ----> Checking broken channels
14:14:59:ST3_smx:INFO: Total # broken ch: 5
14:14:59:ST3_smx:INFO: List FAST: [0, 28, 48, 66, 87]
14:14:59:ST3_smx:INFO: List SLOW: []
14:15:00:ST3_smx:INFO: Holes
14:15:00:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:15:02:ST3_smx:INFO: ----> Checking Analog response
14:15:02:ST3_smx:INFO: ----> Checking broken channels
14:15:02:ST3_smx:INFO: Total # broken ch: 5
14:15:02:ST3_smx:INFO: List FAST: [0, 28, 48, 66, 87]
14:15:02:ST3_smx:INFO: List SLOW: []
14:15:02:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:15:03:febtest:INFO: 0-1 | XA-000-08-003-000-002-229-06 | 34.6 | 1183.3
14:15:03:febtest:INFO: 0-3 | XA-000-08-003-000-000-140-14 | 60.0 | 1112.1
14:15:03:febtest:INFO: 0-5 | XA-000-08-001-064-042-064-12 | 40.9 | 1183.3
14:15:03:febtest:INFO: 0-7 | XA-000-08-001-064-042-056-00 | 34.6 | 1206.9
14:15:04:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:15:08:ST3_smx:INFO: chip: 0-3 56.797143 C 1112.140140 mV
14:15:08:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
14:15:08:ST3_smx:INFO: Electrons
14:15:08:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:15:11:ST3_smx:INFO: ----> Checking Analog response
14:15:11:ST3_smx:INFO: ----> Checking broken channels
14:15:11:ST3_smx:INFO: Total # broken ch: 2
14:15:11:ST3_smx:INFO: List FAST: [79, 84]
14:15:11:ST3_smx:INFO: List SLOW: []
14:15:11:ST3_smx:INFO: Holes
14:15:11:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:15:14:ST3_smx:INFO: ----> Checking Analog response
14:15:14:ST3_smx:INFO: ----> Checking broken channels
14:15:14:ST3_smx:INFO: Total # broken ch: 2
14:15:14:ST3_smx:INFO: List FAST: [79, 84]
14:15:14:ST3_smx:INFO: List SLOW: []
14:15:14:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:15:15:febtest:INFO: 0-1 | XA-000-08-003-000-002-229-06 | 34.6 | 1183.3
14:15:15:febtest:INFO: 0-3 | XA-000-08-003-000-000-140-14 | 56.8 | 1112.1
14:15:15:febtest:INFO: 0-5 | XA-000-08-001-064-042-064-12 | 40.9 | 1183.3
14:15:15:febtest:INFO: 0-7 | XA-000-08-001-064-042-056-00 | 34.6 | 1201.0
14:15:16:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:15:21:ST3_smx:INFO: chip: 0-5 40.898880 C 1171.483840 mV
14:15:21:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
14:15:21:ST3_smx:INFO: Electrons
14:15:21:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:15:23:ST3_smx:INFO: ----> Checking Analog response
14:15:23:ST3_smx:INFO: ----> Checking broken channels
14:15:24:ST3_smx:INFO: Total # broken ch: 3
14:15:24:ST3_smx:INFO: List FAST: [22, 96, 104]
14:15:24:ST3_smx:INFO: List SLOW: []
14:15:24:ST3_smx:INFO: Holes
14:15:24:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:15:26:ST3_smx:INFO: ----> Checking Analog response
14:15:26:ST3_smx:INFO: ----> Checking broken channels
14:15:27:ST3_smx:INFO: Total # broken ch: 3
14:15:27:ST3_smx:INFO: List FAST: [22, 96, 104]
14:15:27:ST3_smx:INFO: List SLOW: []
14:15:27:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:15:27:febtest:INFO: 0-1 | XA-000-08-003-000-002-229-06 | 34.6 | 1183.3
14:15:27:febtest:INFO: 0-3 | XA-000-08-003-000-000-140-14 | 56.8 | 1106.2
14:15:27:febtest:INFO: 0-5 | XA-000-08-001-064-042-064-12 | 44.1 | 1165.6
14:15:27:febtest:INFO: 0-7 | XA-000-08-001-064-042-056-00 | 34.6 | 1201.0
14:15:28:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:15:33:ST3_smx:INFO: chip: 0-7 28.225000 C 1218.600960 mV
14:15:33:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
14:15:33:ST3_smx:INFO: Electrons
14:15:33:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:15:35:ST3_smx:INFO: ----> Checking Analog response
14:15:35:ST3_smx:INFO: ----> Checking broken channels
14:15:35:ST3_smx:INFO: Total # broken ch: 5
14:15:35:ST3_smx:INFO: List FAST: [2, 31, 48, 63, 88]
14:15:35:ST3_smx:INFO: List SLOW: []
14:15:35:ST3_smx:INFO: Holes
14:15:35:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:15:38:ST3_smx:INFO: ----> Checking Analog response
14:15:38:ST3_smx:INFO: ----> Checking broken channels
14:15:38:ST3_smx:INFO: Total # broken ch: 5
14:15:38:ST3_smx:INFO: List FAST: [2, 31, 48, 63, 88]
14:15:38:ST3_smx:INFO: List SLOW: []
14:15:38:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:15:39:febtest:INFO: 0-1 | XA-000-08-003-000-002-229-06 | 34.6 | 1177.4
14:15:39:febtest:INFO: 0-3 | XA-000-08-003-000-000-140-14 | 56.8 | 1112.1
14:15:39:febtest:INFO: 0-5 | XA-000-08-001-064-042-064-12 | 44.1 | 1165.6
14:15:39:febtest:INFO: 0-7 | XA-000-08-001-064-042-056-00 | 28.2 | 1212.7
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_10_27-14_14_38', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Test', 'SITE': 'KIT', 'SETUP': 'KIT_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-001-064-042-056-00', 'FUSED_ID': 6359364698915382144, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 5, 'N_BROKEN_FAST': '[2, 31, 48, 63, 88]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 5, 'P_BROKEN_FAST': '[2, 31, 48, 63, 88]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.800', '0.8743', '2.200', '1.5850', '0.000', '0.0000', '7.000', '0.7784'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 110, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
14:15:44:ST3_Shared:INFO: Listo of operators:Henrik;
14:15:45:ST3_Shared:INFO: Listo of operators:Henrik; Benjamin;
14:15:46:ST3_Shared:INFO: Listo of operators:Henrik; Benjamin; Irakli;
14:15:50:ST3_Shared:INFO: /home/cbm/public_html/Test_LogDir//FEB/FEB_1022/TestDate_2023_10_27-14_14_38/