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FEB_2035 23.11.23 10:55:58
TextEdit.txt
10:54:39:ST3_hmp4040:INFO: ROHDE&SCHWARZ,HMP4040,110099,HW50020003/SW2.72
10:54:40:febtest:INFO: FEB8.2 selected
10:55:13:smx_tester:INFO: Setting Elink clock mode to 160 MHz
10:55:31:febtest:INFO: FEB 8-2 B @ GSI
10:55:34:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:55:34:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
10:55:34:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:55:34:febtest:INFO: Tsting FEB with SN 2035
10:55:36:smx_tester:INFO: Scanning setup
10:55:36:elinks:INFO: Disabling clock on downlink 0
10:55:36:elinks:INFO: Disabling clock on downlink 1
10:55:36:elinks:INFO: Disabling clock on downlink 2
10:55:36:elinks:INFO: Disabling clock on downlink 3
10:55:36:elinks:INFO: Disabling clock on downlink 4
10:55:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:55:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:55:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:55:36:elinks:INFO: Disabling clock on downlink 0
10:55:36:elinks:INFO: Disabling clock on downlink 1
10:55:36:elinks:INFO: Disabling clock on downlink 2
10:55:36:elinks:INFO: Disabling clock on downlink 3
10:55:36:elinks:INFO: Disabling clock on downlink 4
10:55:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:55:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:55:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:55:36:elinks:INFO: Disabling clock on downlink 0
10:55:36:elinks:INFO: Disabling clock on downlink 1
10:55:36:elinks:INFO: Disabling clock on downlink 2
10:55:36:elinks:INFO: Disabling clock on downlink 3
10:55:36:elinks:INFO: Disabling clock on downlink 4
10:55:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:55:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:55:36:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:55:36:elinks:INFO: Disabling clock on downlink 0
10:55:36:elinks:INFO: Disabling clock on downlink 1
10:55:36:elinks:INFO: Disabling clock on downlink 2
10:55:36:elinks:INFO: Disabling clock on downlink 3
10:55:36:elinks:INFO: Disabling clock on downlink 4
10:55:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:55:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:55:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:55:37:elinks:INFO: Disabling clock on downlink 0
10:55:37:elinks:INFO: Disabling clock on downlink 1
10:55:37:elinks:INFO: Disabling clock on downlink 2
10:55:37:elinks:INFO: Disabling clock on downlink 3
10:55:37:elinks:INFO: Disabling clock on downlink 4
10:55:37:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:55:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
10:55:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:55:37:ST3_emu:ERROR: # of setup_elements is ZERO!
10:55:58:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:55:58:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
10:55:58:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:55:59:febtest:INFO: Tsting FEB with SN 2035
10:56:00:smx_tester:INFO: Scanning setup
10:56:00:elinks:INFO: Disabling clock on downlink 0
10:56:00:elinks:INFO: Disabling clock on downlink 1
10:56:00:elinks:INFO: Disabling clock on downlink 2
10:56:00:elinks:INFO: Disabling clock on downlink 3
10:56:00:elinks:INFO: Disabling clock on downlink 4
10:56:00:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:56:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:56:01:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:56:01:elinks:INFO: Disabling clock on downlink 0
10:56:01:elinks:INFO: Disabling clock on downlink 1
10:56:01:elinks:INFO: Disabling clock on downlink 2
10:56:01:elinks:INFO: Disabling clock on downlink 3
10:56:01:elinks:INFO: Disabling clock on downlink 4
10:56:01:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:56:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:56:01:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:56:01:elinks:INFO: Disabling clock on downlink 0
10:56:01:elinks:INFO: Disabling clock on downlink 1
10:56:01:elinks:INFO: Disabling clock on downlink 2
10:56:01:elinks:INFO: Disabling clock on downlink 3
10:56:01:elinks:INFO: Disabling clock on downlink 4
10:56:01:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:56:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:56:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
10:56:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
10:56:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
10:56:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
10:56:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
10:56:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
10:56:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
10:56:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
10:56:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
10:56:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
10:56:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
10:56:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
10:56:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
10:56:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
10:56:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
10:56:01:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
10:56:01:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:56:01:elinks:INFO: Disabling clock on downlink 0
10:56:01:elinks:INFO: Disabling clock on downlink 1
10:56:01:elinks:INFO: Disabling clock on downlink 2
10:56:01:elinks:INFO: Disabling clock on downlink 3
10:56:01:elinks:INFO: Disabling clock on downlink 4
10:56:01:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:56:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:56:01:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:56:01:elinks:INFO: Disabling clock on downlink 0
10:56:01:elinks:INFO: Disabling clock on downlink 1
10:56:01:elinks:INFO: Disabling clock on downlink 2
10:56:01:elinks:INFO: Disabling clock on downlink 3
10:56:01:elinks:INFO: Disabling clock on downlink 4
10:56:01:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:56:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
10:56:01:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:56:01:setup_element:INFO: Scanning clock phase
10:56:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:56:01:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:56:01:setup_element:INFO: Clock phase scan results for group 0, downlink 2
10:56:01:setup_element:INFO: Eye window for uplink 16: __________________________________________________________________________XXXXX_
Clock Delay: 36
10:56:01:setup_element:INFO: Eye window for uplink 17: __________________________________________________________________________XXXXX_
Clock Delay: 36
10:56:01:setup_element:INFO: Eye window for uplink 18: __________________________________________________________________________XXXX__
Clock Delay: 35
10:56:01:setup_element:INFO: Eye window for uplink 19: __________________________________________________________________________XXXX__
Clock Delay: 35
10:56:01:setup_element:INFO: Eye window for uplink 20: ________________________________________________________________________XXXXXX__
Clock Delay: 34
10:56:01:setup_element:INFO: Eye window for uplink 21: ________________________________________________________________________XXXXXX__
Clock Delay: 34
10:56:01:setup_element:INFO: Eye window for uplink 22: ________________________________________________________________________XXXXXX__
Clock Delay: 34
10:56:01:setup_element:INFO: Eye window for uplink 23: ________________________________________________________________________XXXXXX__
Clock Delay: 34
10:56:01:setup_element:INFO: Eye window for uplink 24: _________________________________________________________________________XXXXX__
Clock Delay: 35
10:56:01:setup_element:INFO: Eye window for uplink 25: _________________________________________________________________________XXXXX__
Clock Delay: 35
10:56:01:setup_element:INFO: Eye window for uplink 26: _______________________________________________________________________XXXXXX___
Clock Delay: 33
10:56:01:setup_element:INFO: Eye window for uplink 27: _______________________________________________________________________XXXXXX___
Clock Delay: 33
10:56:01:setup_element:INFO: Eye window for uplink 28: _________________________________________________________________________XXXXX__
Clock Delay: 35
10:56:01:setup_element:INFO: Eye window for uplink 29: _________________________________________________________________________XXXXX__
Clock Delay: 35
10:56:01:setup_element:INFO: Eye window for uplink 30: _________________________________________________________________________XXXXXX_
Clock Delay: 35
10:56:01:setup_element:INFO: Eye window for uplink 31: _________________________________________________________________________XXXXXX_
Clock Delay: 35
10:56:01:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 2
10:56:01:setup_element:INFO: Scanning data phases
10:56:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:56:02:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:56:07:setup_element:INFO: Data phase scan results for group 0, downlink 2
10:56:07:setup_element:INFO: Eye window for uplink 16: XXXX_________________________________XXX
Data delay found: 20
10:56:07:setup_element:INFO: Eye window for uplink 17: _________________________________XXXXXX_
Data delay found: 15
10:56:07:setup_element:INFO: Eye window for uplink 18: XX____________________________________XX
Data delay found: 19
10:56:07:setup_element:INFO: Eye window for uplink 19: __________________________________XXXXX_
Data delay found: 16
10:56:07:setup_element:INFO: Eye window for uplink 20: ________________________________XXXXX___
Data delay found: 14
10:56:07:setup_element:INFO: Eye window for uplink 21: _______________________________XXXXX____
Data delay found: 13
10:56:07:setup_element:INFO: Eye window for uplink 22: ___________________________________XXXX_
Data delay found: 16
10:56:07:setup_element:INFO: Eye window for uplink 23: _______________________________XXXX_____
Data delay found: 12
10:56:07:setup_element:INFO: Eye window for uplink 24: ____XXXXXX______________________________
Data delay found: 26
10:56:07:setup_element:INFO: Eye window for uplink 25: ________XXXXX___________________________
Data delay found: 30
10:56:07:setup_element:INFO: Eye window for uplink 26: ____XXXXX_______________________________
Data delay found: 26
10:56:07:setup_element:INFO: Eye window for uplink 27: ________XXXXXX__________________________
Data delay found: 30
10:56:07:setup_element:INFO: Eye window for uplink 28: __________XXXXX_________________________
Data delay found: 32
10:56:07:setup_element:INFO: Eye window for uplink 29: ____________XXXXX_______________________
Data delay found: 34
10:56:07:setup_element:INFO: Eye window for uplink 30: _____________XXXXXX_____________________
Data delay found: 35
10:56:07:setup_element:INFO: Eye window for uplink 31: ______________XXXX______________________
Data delay found: 35
10:56:07:setup_element:INFO: Setting the data phase to 20 for uplink 16
10:56:07:setup_element:INFO: Setting the data phase to 15 for uplink 17
10:56:07:setup_element:INFO: Setting the data phase to 19 for uplink 18
10:56:07:setup_element:INFO: Setting the data phase to 16 for uplink 19
10:56:07:setup_element:INFO: Setting the data phase to 14 for uplink 20
10:56:07:setup_element:INFO: Setting the data phase to 13 for uplink 21
10:56:07:setup_element:INFO: Setting the data phase to 16 for uplink 22
10:56:07:setup_element:INFO: Setting the data phase to 12 for uplink 23
10:56:07:setup_element:INFO: Setting the data phase to 26 for uplink 24
10:56:07:setup_element:INFO: Setting the data phase to 30 for uplink 25
10:56:07:setup_element:INFO: Setting the data phase to 26 for uplink 26
10:56:07:setup_element:INFO: Setting the data phase to 30 for uplink 27
10:56:07:setup_element:INFO: Setting the data phase to 32 for uplink 28
10:56:07:setup_element:INFO: Setting the data phase to 34 for uplink 29
10:56:07:setup_element:INFO: Setting the data phase to 35 for uplink 30
10:56:07:setup_element:INFO: Setting the data phase to 35 for uplink 31
10:56:07:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 72
Eye Windows:
Uplink 16: __________________________________________________________________________XXXXX_
Uplink 17: __________________________________________________________________________XXXXX_
Uplink 18: __________________________________________________________________________XXXX__
Uplink 19: __________________________________________________________________________XXXX__
Uplink 20: ________________________________________________________________________XXXXXX__
Uplink 21: ________________________________________________________________________XXXXXX__
Uplink 22: ________________________________________________________________________XXXXXX__
Uplink 23: ________________________________________________________________________XXXXXX__
Uplink 24: _________________________________________________________________________XXXXX__
Uplink 25: _________________________________________________________________________XXXXX__
Uplink 26: _______________________________________________________________________XXXXXX___
Uplink 27: _______________________________________________________________________XXXXXX___
Uplink 28: _________________________________________________________________________XXXXX__
Uplink 29: _________________________________________________________________________XXXXX__
Uplink 30: _________________________________________________________________________XXXXXX_
Uplink 31: _________________________________________________________________________XXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 20
Window Length: 33
Eye Window: XXXX_________________________________XXX
Uplink 17:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 18:
Optimal Phase: 19
Window Length: 36
Eye Window: XX____________________________________XX
Uplink 19:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 20:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 21:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 22:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 23:
Optimal Phase: 12
Window Length: 36
Eye Window: _______________________________XXXX_____
Uplink 24:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 25:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 26:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 27:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 28:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 29:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 30:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 31:
Optimal Phase: 35
Window Length: 36
Eye Window: ______________XXXX______________________
]
10:56:07:setup_element:INFO: Beginning SMX ASICs map scan
10:56:07:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:56:07:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:56:07:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
10:56:07:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
10:56:07:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
10:56:07:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
10:56:07:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
10:56:07:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
10:56:07:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
10:56:07:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
10:56:07:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
10:56:07:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
10:56:07:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
10:56:08:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
10:56:08:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
10:56:08:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
10:56:08:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
10:56:08:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
10:56:08:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
10:56:08:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
10:56:08:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
10:56:09:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 72
Eye Windows:
Uplink 16: __________________________________________________________________________XXXXX_
Uplink 17: __________________________________________________________________________XXXXX_
Uplink 18: __________________________________________________________________________XXXX__
Uplink 19: __________________________________________________________________________XXXX__
Uplink 20: ________________________________________________________________________XXXXXX__
Uplink 21: ________________________________________________________________________XXXXXX__
Uplink 22: ________________________________________________________________________XXXXXX__
Uplink 23: ________________________________________________________________________XXXXXX__
Uplink 24: _________________________________________________________________________XXXXX__
Uplink 25: _________________________________________________________________________XXXXX__
Uplink 26: _______________________________________________________________________XXXXXX___
Uplink 27: _______________________________________________________________________XXXXXX___
Uplink 28: _________________________________________________________________________XXXXX__
Uplink 29: _________________________________________________________________________XXXXX__
Uplink 30: _________________________________________________________________________XXXXXX_
Uplink 31: _________________________________________________________________________XXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 20
Window Length: 33
Eye Window: XXXX_________________________________XXX
Uplink 17:
Optimal Phase: 15
Window Length: 34
Eye Window: _________________________________XXXXXX_
Uplink 18:
Optimal Phase: 19
Window Length: 36
Eye Window: XX____________________________________XX
Uplink 19:
Optimal Phase: 16
Window Length: 35
Eye Window: __________________________________XXXXX_
Uplink 20:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 21:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 22:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 23:
Optimal Phase: 12
Window Length: 36
Eye Window: _______________________________XXXX_____
Uplink 24:
Optimal Phase: 26
Window Length: 34
Eye Window: ____XXXXXX______________________________
Uplink 25:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 26:
Optimal Phase: 26
Window Length: 35
Eye Window: ____XXXXX_______________________________
Uplink 27:
Optimal Phase: 30
Window Length: 34
Eye Window: ________XXXXXX__________________________
Uplink 28:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 29:
Optimal Phase: 34
Window Length: 35
Eye Window: ____________XXXXX_______________________
Uplink 30:
Optimal Phase: 35
Window Length: 34
Eye Window: _____________XXXXXX_____________________
Uplink 31:
Optimal Phase: 35
Window Length: 36
Eye Window: ______________XXXX______________________
10:56:09:setup_element:INFO: Performing Elink synchronization
10:56:09:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:56:09:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:56:09:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
10:56:09:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
10:56:09:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
10:56:09:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
10:56:10:ST3_emu:INFO: Number of chips: 8
10:56:10:ST3_emu:INFO: Chip address: 0x0
10:56:10:ST3_emu:INFO: Chip address: 0x1
10:56:10:ST3_emu:INFO: Chip address: 0x2
10:56:10:ST3_emu:INFO: Chip address: 0x3
10:56:10:ST3_emu:INFO: Chip address: 0x4
10:56:10:ST3_emu:INFO: Chip address: 0x5
10:56:10:ST3_emu:INFO: Chip address: 0x6
10:56:10:ST3_emu:INFO: Chip address: 0x7
10:56:11:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:56:11:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 40.9 | 1159.7
10:56:11:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 47.3 | 1147.8
10:56:12:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 21.9 | 1236.2
10:56:12:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 37.7 | 1183.3
10:56:12:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 12.4 | 1259.6
10:56:12:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 37.7 | 1183.3
10:56:12:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 12.4 | 1282.9
10:56:13:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 31.4 | 1206.9
10:56:13:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:56:18:ST3_smx:INFO: chip: 0-0 37.726682 C 1165.571835 mV
10:56:18:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:56:18:ST3_smx:INFO: Electrons
10:56:18:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
10:56:20:ST3_smx:INFO: ----> Checking Analog response
10:56:20:ST3_smx:INFO: ----> Checking broken channels
10:56:21:ST3_smx:INFO: Total # broken ch: 0
10:56:21:ST3_smx:INFO: List FAST: []
10:56:21:ST3_smx:INFO: List SLOW: []
10:56:21:ST3_smx:INFO: Holes
10:56:21:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
10:56:23:ST3_smx:INFO: ----> Checking Analog response
10:56:23:ST3_smx:INFO: ----> Checking broken channels
10:56:23:ST3_smx:INFO: Total # broken ch: 0
10:56:23:ST3_smx:INFO: List FAST: []
10:56:23:ST3_smx:INFO: List SLOW: []
10:56:23:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:56:24:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 37.7 | 1159.7
10:56:24:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 47.3 | 1153.7
10:56:24:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 21.9 | 1236.2
10:56:24:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 37.7 | 1183.3
10:56:25:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 12.4 | 1259.6
10:56:25:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 37.7 | 1183.3
10:56:25:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 9.3 | 1277.1
10:56:25:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 28.2 | 1206.9
10:56:26:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:56:31:ST3_smx:INFO: chip: 0-1 40.898880 C 1159.654860 mV
10:56:31:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:56:31:ST3_smx:INFO: Electrons
10:56:31:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
10:56:33:ST3_smx:INFO: ----> Checking Analog response
10:56:33:ST3_smx:INFO: ----> Checking broken channels
10:56:33:ST3_smx:INFO: Total # broken ch: 0
10:56:33:ST3_smx:INFO: List FAST: []
10:56:33:ST3_smx:INFO: List SLOW: []
10:56:33:ST3_smx:INFO: Holes
10:56:33:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
10:56:36:ST3_smx:INFO: ----> Checking Analog response
10:56:36:ST3_smx:INFO: ----> Checking broken channels
10:56:36:ST3_smx:INFO: Total # broken ch: 0
10:56:36:ST3_smx:INFO: List FAST: []
10:56:36:ST3_smx:INFO: List SLOW: []
10:56:36:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:56:36:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 40.9 | 1159.7
10:56:36:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 44.1 | 1159.7
10:56:37:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 21.9 | 1236.2
10:56:37:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 37.7 | 1183.3
10:56:37:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 12.4 | 1259.6
10:56:37:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 37.7 | 1183.3
10:56:37:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 9.3 | 1277.1
10:56:38:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 28.2 | 1206.9
10:56:38:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:56:43:ST3_smx:INFO: chip: 0-2 31.389742 C 1189.190035 mV
10:56:43:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:56:43:ST3_smx:INFO: Electrons
10:56:43:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
10:56:45:ST3_smx:INFO: ----> Checking Analog response
10:56:45:ST3_smx:INFO: ----> Checking broken channels
10:56:45:ST3_smx:INFO: Total # broken ch: 0
10:56:45:ST3_smx:INFO: List FAST: []
10:56:45:ST3_smx:INFO: List SLOW: []
10:56:45:ST3_smx:INFO: Holes
10:56:45:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
10:56:48:ST3_smx:INFO: ----> Checking Analog response
10:56:48:ST3_smx:INFO: ----> Checking broken channels
10:56:48:ST3_smx:INFO: Total # broken ch: 0
10:56:48:ST3_smx:INFO: List FAST: []
10:56:48:ST3_smx:INFO: List SLOW: []
10:56:48:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:56:48:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 40.9 | 1159.7
10:56:49:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 44.1 | 1159.7
10:56:49:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 31.4 | 1189.2
10:56:49:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 37.7 | 1183.3
10:56:49:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 12.4 | 1253.7
10:56:49:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 37.7 | 1183.3
10:56:50:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 9.3 | 1277.1
10:56:50:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 28.2 | 1206.9
10:56:51:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:56:55:ST3_smx:INFO: chip: 0-3 40.898880 C 1159.654860 mV
10:56:55:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:56:55:ST3_smx:INFO: Electrons
10:56:55:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
10:56:57:ST3_smx:INFO: ----> Checking Analog response
10:56:57:ST3_smx:INFO: ----> Checking broken channels
10:56:58:ST3_smx:INFO: Total # broken ch: 0
10:56:58:ST3_smx:INFO: List FAST: []
10:56:58:ST3_smx:INFO: List SLOW: []
10:56:58:ST3_smx:INFO: Holes
10:56:58:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
10:57:00:ST3_smx:INFO: ----> Checking Analog response
10:57:00:ST3_smx:INFO: ----> Checking broken channels
10:57:00:ST3_smx:INFO: Total # broken ch: 0
10:57:00:ST3_smx:INFO: List FAST: []
10:57:00:ST3_smx:INFO: List SLOW: []
10:57:00:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:57:01:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 40.9 | 1153.7
10:57:01:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 40.9 | 1153.7
10:57:01:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 31.4 | 1189.2
10:57:01:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 40.9 | 1153.7
10:57:01:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 15.6 | 1253.7
10:57:02:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 37.7 | 1183.3
10:57:02:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 9.3 | 1277.1
10:57:02:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 28.2 | 1206.9
10:57:03:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:57:07:ST3_smx:INFO: chip: 0-4 12.438562 C 1242.040240 mV
10:57:07:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:57:07:ST3_smx:INFO: Electrons
10:57:07:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
10:57:10:ST3_smx:INFO: ----> Checking Analog response
10:57:10:ST3_smx:INFO: ----> Checking broken channels
10:57:10:ST3_smx:INFO: Total # broken ch: 0
10:57:10:ST3_smx:INFO: List FAST: []
10:57:10:ST3_smx:INFO: List SLOW: []
10:57:10:ST3_smx:INFO: Holes
10:57:10:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
10:57:12:ST3_smx:INFO: ----> Checking Analog response
10:57:12:ST3_smx:INFO: ----> Checking broken channels
10:57:12:ST3_smx:INFO: Total # broken ch: 0
10:57:12:ST3_smx:INFO: List FAST: []
10:57:12:ST3_smx:INFO: List SLOW: []
10:57:12:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:57:13:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 40.9 | 1153.7
10:57:13:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 40.9 | 1153.7
10:57:13:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 34.6 | 1189.2
10:57:13:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 40.9 | 1153.7
10:57:14:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 15.6 | 1242.0
10:57:14:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 37.7 | 1177.4
10:57:14:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 9.3 | 1277.1
10:57:14:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 28.2 | 1206.9
10:57:15:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:57:19:ST3_smx:INFO: chip: 0-5 34.556970 C 1171.483840 mV
10:57:19:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:57:19:ST3_smx:INFO: Electrons
10:57:19:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
10:57:22:ST3_smx:INFO: ----> Checking Analog response
10:57:22:ST3_smx:INFO: ----> Checking broken channels
10:57:22:ST3_smx:INFO: Total # broken ch: 0
10:57:22:ST3_smx:INFO: List FAST: []
10:57:22:ST3_smx:INFO: List SLOW: []
10:57:22:ST3_smx:INFO: Holes
10:57:22:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
10:57:24:ST3_smx:INFO: ----> Checking Analog response
10:57:24:ST3_smx:INFO: ----> Checking broken channels
10:57:24:ST3_smx:INFO: Total # broken ch: 0
10:57:24:ST3_smx:INFO: List FAST: []
10:57:24:ST3_smx:INFO: List SLOW: []
10:57:24:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:57:25:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 40.9 | 1153.7
10:57:25:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 40.9 | 1153.7
10:57:25:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 31.4 | 1183.3
10:57:25:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 40.9 | 1153.7
10:57:25:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 15.6 | 1242.0
10:57:26:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 37.7 | 1171.5
10:57:26:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 12.4 | 1277.1
10:57:26:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 28.2 | 1201.0
10:57:27:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:57:31:ST3_smx:INFO: chip: 0-6 18.745682 C 1230.330540 mV
10:57:31:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:57:31:ST3_smx:INFO: Electrons
10:57:31:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
10:57:34:ST3_smx:INFO: ----> Checking Analog response
10:57:34:ST3_smx:INFO: ----> Checking broken channels
10:57:34:ST3_smx:INFO: Total # broken ch: 0
10:57:34:ST3_smx:INFO: List FAST: []
10:57:34:ST3_smx:INFO: List SLOW: []
10:57:34:ST3_smx:INFO: Holes
10:57:34:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
10:57:37:ST3_smx:INFO: ----> Checking Analog response
10:57:37:ST3_smx:INFO: ----> Checking broken channels
10:57:37:ST3_smx:INFO: Total # broken ch: 0
10:57:37:ST3_smx:INFO: List FAST: []
10:57:37:ST3_smx:INFO: List SLOW: []
10:57:37:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:57:37:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 40.9 | 1153.7
10:57:37:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 44.1 | 1153.7
10:57:37:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 31.4 | 1183.3
10:57:38:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 40.9 | 1147.8
10:57:38:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 15.6 | 1242.0
10:57:38:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 37.7 | 1171.5
10:57:38:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 21.9 | 1224.5
10:57:39:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 28.2 | 1201.0
10:57:39:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
10:57:43:ST3_smx:INFO: chip: 0-7 34.556970 C 1165.571835 mV
10:57:43:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
10:57:43:ST3_smx:INFO: Electrons
10:57:43:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
10:57:46:ST3_smx:INFO: ----> Checking Analog response
10:57:46:ST3_smx:INFO: ----> Checking broken channels
10:57:46:ST3_smx:INFO: Total # broken ch: 0
10:57:46:ST3_smx:INFO: List FAST: []
10:57:46:ST3_smx:INFO: List SLOW: []
10:57:46:ST3_smx:INFO: Holes
10:57:46:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
10:57:48:ST3_smx:INFO: ----> Checking Analog response
10:57:48:ST3_smx:INFO: ----> Checking broken channels
10:57:49:ST3_smx:INFO: Total # broken ch: 0
10:57:49:ST3_smx:INFO: List FAST: []
10:57:49:ST3_smx:INFO: List SLOW: []
10:57:49:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
10:57:49:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 40.9 | 1153.7
10:57:49:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 40.9 | 1147.8
10:57:49:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 31.4 | 1183.3
10:57:49:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 40.9 | 1147.8
10:57:50:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 15.6 | 1242.0
10:57:50:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 34.6 | 1165.6
10:57:50:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 21.9 | 1224.5
10:57:50:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 37.7 | 1165.6
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_23-10_55_58', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Test', 'SITE': 'KIT', 'SETUP': 'KIT_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-007-083-04', 'FUSED_ID': 6359364699116565812, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.800', '1.4980', '2.203', '2.5430', '0.000', '0.0000', '7.000', '0.7593'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 110, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
10:58:07:ST3_Shared:INFO: Listo of operators:Benjamin;
10:58:08:ST3_Shared:INFO: Listo of operators:Benjamin; Irakli;
10:58:12:ST3_Shared:INFO: /home/cbm/public_html/Test_LogDir//FEB/FEB_2035/TestDate_2023_11_23-10_55_58/