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FEB_2035 23.11.23 14:57:37
Info
14:57:20:febtest:INFO: FEB8.2 selected
14:57:20:smx_tester:INFO: Setting Elink clock mode to 160 MHz
14:57:33:febtest:INFO: FEB 8-2 B @ GSI
14:57:37:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:57:37:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
14:57:37:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:57:37:febtest:INFO: Tsting FEB with SN 2035
14:57:39:smx_tester:INFO: Scanning setup
14:57:39:elinks:INFO: Disabling clock on downlink 0
14:57:39:elinks:INFO: Disabling clock on downlink 1
14:57:39:elinks:INFO: Disabling clock on downlink 2
14:57:39:elinks:INFO: Disabling clock on downlink 3
14:57:39:elinks:INFO: Disabling clock on downlink 4
14:57:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:57:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:57:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:57:39:elinks:INFO: Disabling clock on downlink 0
14:57:39:elinks:INFO: Disabling clock on downlink 1
14:57:39:elinks:INFO: Disabling clock on downlink 2
14:57:39:elinks:INFO: Disabling clock on downlink 3
14:57:39:elinks:INFO: Disabling clock on downlink 4
14:57:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:57:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:57:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:57:39:elinks:INFO: Disabling clock on downlink 0
14:57:39:elinks:INFO: Disabling clock on downlink 1
14:57:39:elinks:INFO: Disabling clock on downlink 2
14:57:39:elinks:INFO: Disabling clock on downlink 3
14:57:39:elinks:INFO: Disabling clock on downlink 4
14:57:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:57:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:57:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
14:57:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
14:57:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
14:57:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
14:57:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
14:57:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
14:57:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
14:57:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
14:57:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
14:57:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
14:57:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
14:57:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
14:57:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
14:57:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
14:57:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
14:57:39:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
14:57:39:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:57:39:elinks:INFO: Disabling clock on downlink 0
14:57:39:elinks:INFO: Disabling clock on downlink 1
14:57:39:elinks:INFO: Disabling clock on downlink 2
14:57:39:elinks:INFO: Disabling clock on downlink 3
14:57:39:elinks:INFO: Disabling clock on downlink 4
14:57:39:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:57:39:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:57:40:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:57:40:elinks:INFO: Disabling clock on downlink 0
14:57:40:elinks:INFO: Disabling clock on downlink 1
14:57:40:elinks:INFO: Disabling clock on downlink 2
14:57:40:elinks:INFO: Disabling clock on downlink 3
14:57:40:elinks:INFO: Disabling clock on downlink 4
14:57:40:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:57:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:57:40:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:57:40:setup_element:INFO: Scanning clock phase
14:57:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:57:40:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:57:40:setup_element:INFO: Clock phase scan results for group 0, downlink 2
14:57:40:setup_element:INFO: Eye window for uplink 16: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:57:40:setup_element:INFO: Eye window for uplink 17: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:57:40:setup_element:INFO: Eye window for uplink 18: __________________________________________________________________________XXXX__
Clock Delay: 35
14:57:40:setup_element:INFO: Eye window for uplink 19: __________________________________________________________________________XXXX__
Clock Delay: 35
14:57:40:setup_element:INFO: Eye window for uplink 20: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:57:40:setup_element:INFO: Eye window for uplink 21: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:57:40:setup_element:INFO: Eye window for uplink 22: ________________________________________________________________________________
Clock Delay: 40
14:57:40:setup_element:INFO: Eye window for uplink 23: ________________________________________________________________________________
Clock Delay: 40
14:57:40:setup_element:INFO: Eye window for uplink 24: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:57:40:setup_element:INFO: Eye window for uplink 25: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:57:40:setup_element:INFO: Eye window for uplink 26: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
14:57:40:setup_element:INFO: Eye window for uplink 27: _______________________________________________________________________XXXXXXX__
Clock Delay: 34
14:57:40:setup_element:INFO: Eye window for uplink 28: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:57:40:setup_element:INFO: Eye window for uplink 29: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:57:40:setup_element:INFO: Eye window for uplink 30: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:57:40:setup_element:INFO: Eye window for uplink 31: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:57:40:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 2
14:57:40:setup_element:INFO: Scanning data phases
14:57:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:57:40:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:57:45:setup_element:INFO: Data phase scan results for group 0, downlink 2
14:57:45:setup_element:INFO: Eye window for uplink 16: XXX__________________________________XXX
Data delay found: 19
14:57:45:setup_element:INFO: Eye window for uplink 17: __________________________________XXXX__
Data delay found: 15
14:57:45:setup_element:INFO: Eye window for uplink 18: X___________________________________XXXX
Data delay found: 18
14:57:45:setup_element:INFO: Eye window for uplink 19: _________________________________XXXXX__
Data delay found: 15
14:57:45:setup_element:INFO: Eye window for uplink 20: ________________________________XXXXX___
Data delay found: 14
14:57:45:setup_element:INFO: Eye window for uplink 21: _______________________________XXXXX____
Data delay found: 13
14:57:45:setup_element:INFO: Eye window for uplink 22: __________________________________XXXX__
Data delay found: 15
14:57:45:setup_element:INFO: Eye window for uplink 23: ______________________________XXXX______
Data delay found: 11
14:57:45:setup_element:INFO: Eye window for uplink 24: ___XXXXXX_______________________________
Data delay found: 25
14:57:45:setup_element:INFO: Eye window for uplink 25: _______XXXXX____________________________
Data delay found: 29
14:57:45:setup_element:INFO: Eye window for uplink 26: ___XXXXX________________________________
Data delay found: 25
14:57:45:setup_element:INFO: Eye window for uplink 27: _______XXXXXX___________________________
Data delay found: 29
14:57:45:setup_element:INFO: Eye window for uplink 28: _________XXXXXX_________________________
Data delay found: 31
14:57:45:setup_element:INFO: Eye window for uplink 29: ____________XXXXXX______________________
Data delay found: 34
14:57:45:setup_element:INFO: Eye window for uplink 30: _____________XXXXX______________________
Data delay found: 35
14:57:45:setup_element:INFO: Eye window for uplink 31: _____________XXXX_______________________
Data delay found: 34
14:57:45:setup_element:INFO: Setting the data phase to 19 for uplink 16
14:57:45:setup_element:INFO: Setting the data phase to 15 for uplink 17
14:57:45:setup_element:INFO: Setting the data phase to 18 for uplink 18
14:57:45:setup_element:INFO: Setting the data phase to 15 for uplink 19
14:57:45:setup_element:INFO: Setting the data phase to 14 for uplink 20
14:57:45:setup_element:INFO: Setting the data phase to 13 for uplink 21
14:57:45:setup_element:INFO: Setting the data phase to 15 for uplink 22
14:57:45:setup_element:INFO: Setting the data phase to 11 for uplink 23
14:57:45:setup_element:INFO: Setting the data phase to 25 for uplink 24
14:57:45:setup_element:INFO: Setting the data phase to 29 for uplink 25
14:57:45:setup_element:INFO: Setting the data phase to 25 for uplink 26
14:57:45:setup_element:INFO: Setting the data phase to 29 for uplink 27
14:57:45:setup_element:INFO: Setting the data phase to 31 for uplink 28
14:57:45:setup_element:INFO: Setting the data phase to 34 for uplink 29
14:57:45:setup_element:INFO: Setting the data phase to 35 for uplink 30
14:57:45:setup_element:INFO: Setting the data phase to 34 for uplink 31
14:57:45:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 72
Eye Windows:
Uplink 16: __________________________________________________________________________XXXXX_
Uplink 17: __________________________________________________________________________XXXXX_
Uplink 18: __________________________________________________________________________XXXX__
Uplink 19: __________________________________________________________________________XXXX__
Uplink 20: ________________________________________________________________________XXXXXX__
Uplink 21: ________________________________________________________________________XXXXXX__
Uplink 22: ________________________________________________________________________________
Uplink 23: ________________________________________________________________________________
Uplink 24: _________________________________________________________________________XXXXX__
Uplink 25: _________________________________________________________________________XXXXX__
Uplink 26: _______________________________________________________________________XXXXXXX__
Uplink 27: _______________________________________________________________________XXXXXXX__
Uplink 28: _________________________________________________________________________XXXXX__
Uplink 29: _________________________________________________________________________XXXXX__
Uplink 30: __________________________________________________________________________XXXXX_
Uplink 31: __________________________________________________________________________XXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 17:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 18:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 19:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 20:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 21:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 11
Window Length: 36
Eye Window: ______________________________XXXX______
Uplink 24:
Optimal Phase: 25
Window Length: 34
Eye Window: ___XXXXXX_______________________________
Uplink 25:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 26:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 27:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 28:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 29:
Optimal Phase: 34
Window Length: 34
Eye Window: ____________XXXXXX______________________
Uplink 30:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 31:
Optimal Phase: 34
Window Length: 36
Eye Window: _____________XXXX_______________________
]
14:57:45:setup_element:INFO: Beginning SMX ASICs map scan
14:57:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:57:45:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:57:45:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
14:57:45:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
14:57:45:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
14:57:45:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
14:57:45:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
14:57:45:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
14:57:45:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
14:57:46:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
14:57:46:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
14:57:46:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
14:57:46:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
14:57:46:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
14:57:46:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
14:57:46:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
14:57:46:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
14:57:46:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
14:57:46:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
14:57:47:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
14:57:47:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
14:57:48:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 72
Eye Windows:
Uplink 16: __________________________________________________________________________XXXXX_
Uplink 17: __________________________________________________________________________XXXXX_
Uplink 18: __________________________________________________________________________XXXX__
Uplink 19: __________________________________________________________________________XXXX__
Uplink 20: ________________________________________________________________________XXXXXX__
Uplink 21: ________________________________________________________________________XXXXXX__
Uplink 22: ________________________________________________________________________________
Uplink 23: ________________________________________________________________________________
Uplink 24: _________________________________________________________________________XXXXX__
Uplink 25: _________________________________________________________________________XXXXX__
Uplink 26: _______________________________________________________________________XXXXXXX__
Uplink 27: _______________________________________________________________________XXXXXXX__
Uplink 28: _________________________________________________________________________XXXXX__
Uplink 29: _________________________________________________________________________XXXXX__
Uplink 30: __________________________________________________________________________XXXXX_
Uplink 31: __________________________________________________________________________XXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 19
Window Length: 34
Eye Window: XXX__________________________________XXX
Uplink 17:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 18:
Optimal Phase: 18
Window Length: 35
Eye Window: X___________________________________XXXX
Uplink 19:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 20:
Optimal Phase: 14
Window Length: 35
Eye Window: ________________________________XXXXX___
Uplink 21:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 11
Window Length: 36
Eye Window: ______________________________XXXX______
Uplink 24:
Optimal Phase: 25
Window Length: 34
Eye Window: ___XXXXXX_______________________________
Uplink 25:
Optimal Phase: 29
Window Length: 35
Eye Window: _______XXXXX____________________________
Uplink 26:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 27:
Optimal Phase: 29
Window Length: 34
Eye Window: _______XXXXXX___________________________
Uplink 28:
Optimal Phase: 31
Window Length: 34
Eye Window: _________XXXXXX_________________________
Uplink 29:
Optimal Phase: 34
Window Length: 34
Eye Window: ____________XXXXXX______________________
Uplink 30:
Optimal Phase: 35
Window Length: 35
Eye Window: _____________XXXXX______________________
Uplink 31:
Optimal Phase: 34
Window Length: 36
Eye Window: _____________XXXX_______________________
14:57:48:setup_element:INFO: Performing Elink synchronization
14:57:48:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:57:48:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:57:48:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
14:57:48:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
14:57:48:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
14:57:48:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
14:57:48:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
14:57:49:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:57:49:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 44.1 | 1159.7
14:57:49:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 47.3 | 1159.7
14:57:50:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 21.9 | 1236.2
14:57:50:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 37.7 | 1189.2
14:57:50:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 15.6 | 1259.6
14:57:50:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 37.7 | 1189.2
14:57:51:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 12.4 | 1282.9
14:57:51:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 31.4 | 1206.9
14:57:51:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:57:54:ST3_smx:INFO: chip: 0-0 40.898880 C 1177.390875 mV
14:57:54:ST3_smx:INFO: Electrons
14:57:54:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:57:56:ST3_smx:INFO: ----> Checking Analog response
14:57:56:ST3_smx:INFO: ----> Checking broken channels
14:57:56:ST3_smx:INFO: Total # broken ch: 0
14:57:56:ST3_smx:INFO: List FAST: []
14:57:56:ST3_smx:INFO: List SLOW: []
14:57:56:ST3_smx:INFO: Holes
14:57:56:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:57:58:ST3_smx:INFO: ----> Checking Analog response
14:57:58:ST3_smx:INFO: ----> Checking broken channels
14:57:58:ST3_smx:INFO: Total # broken ch: 0
14:57:58:ST3_smx:INFO: List FAST: []
14:57:58:ST3_smx:INFO: List SLOW: []
14:57:58:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:57:59:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 44.1 | 1171.5
14:57:59:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 47.3 | 1153.7
14:57:59:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 21.9 | 1242.0
14:57:59:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 37.7 | 1189.2
14:57:59:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 15.6 | 1259.6
14:58:00:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 37.7 | 1189.2
14:58:00:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 12.4 | 1282.9
14:58:00:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 31.4 | 1212.7
14:58:01:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:58:04:ST3_smx:INFO: chip: 0-1 44.073563 C 1177.390875 mV
14:58:04:ST3_smx:INFO: Electrons
14:58:04:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:58:06:ST3_smx:INFO: ----> Checking Analog response
14:58:06:ST3_smx:INFO: ----> Checking broken channels
14:58:07:ST3_smx:INFO: Total # broken ch: 0
14:58:07:ST3_smx:INFO: List FAST: []
14:58:07:ST3_smx:INFO: List SLOW: []
14:58:07:ST3_smx:INFO: Holes
14:58:07:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:58:09:ST3_smx:INFO: ----> Checking Analog response
14:58:09:ST3_smx:INFO: ----> Checking broken channels
14:58:09:ST3_smx:INFO: Total # broken ch: 0
14:58:09:ST3_smx:INFO: List FAST: []
14:58:09:ST3_smx:INFO: List SLOW: []
14:58:09:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:58:09:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 40.9 | 1171.5
14:58:09:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 47.3 | 1171.5
14:58:09:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 21.9 | 1242.0
14:58:10:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 37.7 | 1189.2
14:58:10:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 15.6 | 1253.7
14:58:10:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 37.7 | 1195.1
14:58:10:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 12.4 | 1282.9
14:58:10:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 31.4 | 1212.7
14:58:11:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:58:15:ST3_smx:INFO: chip: 0-2 34.556970 C 1206.851500 mV
14:58:15:ST3_smx:INFO: Electrons
14:58:15:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:58:17:ST3_smx:INFO: ----> Checking Analog response
14:58:17:ST3_smx:INFO: ----> Checking broken channels
14:58:17:ST3_smx:INFO: Total # broken ch: 0
14:58:17:ST3_smx:INFO: List FAST: []
14:58:17:ST3_smx:INFO: List SLOW: []
14:58:17:ST3_smx:INFO: Holes
14:58:17:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:58:19:ST3_smx:INFO: ----> Checking Analog response
14:58:19:ST3_smx:INFO: ----> Checking broken channels
14:58:19:ST3_smx:INFO: Total # broken ch: 0
14:58:19:ST3_smx:INFO: List FAST: []
14:58:19:ST3_smx:INFO: List SLOW: []
14:58:19:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:58:20:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 40.9 | 1171.5
14:58:20:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 44.1 | 1171.5
14:58:20:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 34.6 | 1206.9
14:58:20:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 37.7 | 1189.2
14:58:20:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 15.6 | 1259.6
14:58:21:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 37.7 | 1195.1
14:58:21:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 12.4 | 1282.9
14:58:21:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 31.4 | 1212.7
14:58:22:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:58:25:ST3_smx:INFO: chip: 0-3 40.898880 C 1177.390875 mV
14:58:25:ST3_smx:INFO: Electrons
14:58:25:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:58:27:ST3_smx:INFO: ----> Checking Analog response
14:58:27:ST3_smx:INFO: ----> Checking broken channels
14:58:27:ST3_smx:INFO: Total # broken ch: 0
14:58:27:ST3_smx:INFO: List FAST: []
14:58:27:ST3_smx:INFO: List SLOW: []
14:58:27:ST3_smx:INFO: Holes
14:58:27:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:58:29:ST3_smx:INFO: ----> Checking Analog response
14:58:29:ST3_smx:INFO: ----> Checking broken channels
14:58:29:ST3_smx:INFO: Total # broken ch: 0
14:58:29:ST3_smx:INFO: List FAST: []
14:58:30:ST3_smx:INFO: List SLOW: []
14:58:30:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:58:30:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 40.9 | 1171.5
14:58:30:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 44.1 | 1171.5
14:58:30:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 34.6 | 1206.9
14:58:30:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 44.1 | 1171.5
14:58:31:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 15.6 | 1259.6
14:58:31:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 37.7 | 1195.1
14:58:31:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 12.4 | 1282.9
14:58:31:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 31.4 | 1212.7
14:58:32:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:58:35:ST3_smx:INFO: chip: 0-4 15.590880 C 1259.567515 mV
14:58:35:ST3_smx:INFO: Electrons
14:58:35:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:58:37:ST3_smx:INFO: ----> Checking Analog response
14:58:37:ST3_smx:INFO: ----> Checking broken channels
14:58:37:ST3_smx:INFO: Total # broken ch: 0
14:58:37:ST3_smx:INFO: List FAST: []
14:58:37:ST3_smx:INFO: List SLOW: []
14:58:37:ST3_smx:INFO: Holes
14:58:37:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:58:39:ST3_smx:INFO: ----> Checking Analog response
14:58:39:ST3_smx:INFO: ----> Checking broken channels
14:58:39:ST3_smx:INFO: Total # broken ch: 0
14:58:39:ST3_smx:INFO: List FAST: []
14:58:39:ST3_smx:INFO: List SLOW: []
14:58:39:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:58:40:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 40.9 | 1171.5
14:58:40:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 44.1 | 1171.5
14:58:40:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 34.6 | 1206.9
14:58:40:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 44.1 | 1171.5
14:58:40:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 18.7 | 1259.6
14:58:41:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 37.7 | 1195.1
14:58:41:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 12.4 | 1282.9
14:58:41:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 31.4 | 1212.7
14:58:42:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:58:45:ST3_smx:INFO: chip: 0-5 37.726682 C 1200.969315 mV
14:58:45:ST3_smx:INFO: Electrons
14:58:45:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:58:48:ST3_smx:INFO: ----> Checking Analog response
14:58:48:ST3_smx:INFO: ----> Checking broken channels
14:58:48:ST3_smx:INFO: Total # broken ch: 0
14:58:48:ST3_smx:INFO: List FAST: []
14:58:48:ST3_smx:INFO: List SLOW: []
14:58:48:ST3_smx:INFO: Holes
14:58:48:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:58:50:ST3_smx:INFO: ----> Checking Analog response
14:58:50:ST3_smx:INFO: ----> Checking broken channels
14:58:50:ST3_smx:INFO: Total # broken ch: 0
14:58:50:ST3_smx:INFO: List FAST: []
14:58:50:ST3_smx:INFO: List SLOW: []
14:58:50:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:58:50:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 40.9 | 1171.5
14:58:51:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 44.1 | 1171.5
14:58:51:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 34.6 | 1206.9
14:58:51:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 40.9 | 1171.5
14:58:51:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 18.7 | 1259.6
14:58:51:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 40.9 | 1195.1
14:58:52:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 12.4 | 1282.9
14:58:52:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 31.4 | 1212.7
14:58:52:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:58:56:ST3_smx:INFO: chip: 0-6 21.902970 C 1247.887635 mV
14:58:56:ST3_smx:INFO: Electrons
14:58:56:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:58:58:ST3_smx:INFO: ----> Checking Analog response
14:58:58:ST3_smx:INFO: ----> Checking broken channels
14:58:59:ST3_smx:INFO: Total # broken ch: 0
14:58:59:ST3_smx:INFO: List FAST: []
14:58:59:ST3_smx:INFO: List SLOW: []
14:58:59:ST3_smx:INFO: Holes
14:58:59:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:59:01:ST3_smx:INFO: ----> Checking Analog response
14:59:01:ST3_smx:INFO: ----> Checking broken channels
14:59:01:ST3_smx:INFO: Total # broken ch: 0
14:59:01:ST3_smx:INFO: List FAST: []
14:59:01:ST3_smx:INFO: List SLOW: []
14:59:01:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:59:01:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 40.9 | 1177.4
14:59:01:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 44.1 | 1171.5
14:59:02:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 34.6 | 1206.9
14:59:02:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 40.9 | 1177.4
14:59:02:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 18.7 | 1259.6
14:59:02:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 37.7 | 1195.1
14:59:02:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 25.1 | 1242.0
14:59:03:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 31.4 | 1206.9
14:59:03:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:59:07:ST3_smx:INFO: chip: 0-7 40.898880 C 1189.190035 mV
14:59:07:ST3_smx:INFO: Electrons
14:59:07:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:59:09:ST3_smx:INFO: ----> Checking Analog response
14:59:09:ST3_smx:INFO: ----> Checking broken channels
14:59:09:ST3_smx:INFO: Total # broken ch: 0
14:59:09:ST3_smx:INFO: List FAST: []
14:59:09:ST3_smx:INFO: List SLOW: []
14:59:09:ST3_smx:INFO: Holes
14:59:09:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
14:59:11:ST3_smx:INFO: ----> Checking Analog response
14:59:11:ST3_smx:INFO: ----> Checking broken channels
14:59:11:ST3_smx:INFO: Total # broken ch: 0
14:59:11:ST3_smx:INFO: List FAST: []
14:59:11:ST3_smx:INFO: List SLOW: []
14:59:11:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:59:11:febtest:INFO: 0-0 | XA-000-08-002-000-007-008-06 | 40.9 | 1177.4
14:59:11:febtest:INFO: 0-1 | XA-000-08-002-000-007-199-09 | 44.1 | 1171.5
14:59:12:febtest:INFO: 0-2 | XA-000-08-002-000-007-031-01 | 34.6 | 1206.9
14:59:12:febtest:INFO: 0-3 | XA-000-08-002-000-007-198-09 | 40.9 | 1177.4
14:59:12:febtest:INFO: 0-4 | XA-000-08-002-000-007-041-08 | 18.7 | 1259.6
14:59:12:febtest:INFO: 0-5 | XA-000-08-002-000-007-127-10 | 37.7 | 1201.0
14:59:12:febtest:INFO: 0-6 | XA-000-08-002-000-007-047-08 | 25.1 | 1242.0
14:59:13:febtest:INFO: 0-7 | XA-000-08-002-000-007-083-04 | 40.9 | 1183.3
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_11_23-14_57_37', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'KIT', 'SITE': 'KIT', 'SETUP': 'KIT_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-007-083-04', 'FUSED_ID': 6359364699116565812, 'HW_ADDR': 7, 'UPLINK': 24, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'FEB_SN': '6012', 'FEB_TYPE': 8.2, 'FEB_UPLINKS': 2, 'FEB_A': 0, 'FEB_B': 1, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.800', '1.4950', '2.200', '2.6800', '0.000', '0.0000', '7.001', '1.6300'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 110, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 2023_11_23-14_57_37
OPERATOR : Alois Alzheimer
SITE : KIT
SETUP : KIT_TEST_SETUP_1
Set-ID :
---------------------------------------14:59:21:ST3_Shared:INFO: /home/cbm/public_html/KIT_LogDir//FEB/FEB_2035/TestDate_2023_11_23-14_57_37/
MODULE_NAME :
FEB_SN : 6012
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 0
FEB_B : 1
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.800', '1.4950', '2.200', '2.6800', '0.000', '0.0000', '7.001', '1.6300']
VI_after__Init : ['2.800', '1.9870', '2.200', '0.3178', '0.000', '0.0000', '7.000', '1.6370']
VI_at__the_End : ['2.800', '1.9870', '2.200', '0.3179', '0.000', '0.0000', '7.000', '1.6380']