14:52:28:ST3_hmp4040:INFO:	ROHDE&SCHWARZ,HMP4040,110099,HW50020003/SW2.72
14:52:28:febtest:INFO:	FEB 8-2 selected
14:52:28:smx_tester:INFO:	Setting Elink clock mode to 160 MHz
14:52:28:febtest:INFO:	FEB type: 8.2
14:52:28:febtest:INFO:	FEB SN: 2035
14:52:28:febtest:INFO:	FEB A: 0
14:52:28:febtest:INFO:	FEB B: 1
14:52:29:febtest:INFO:	FEB 8-2 selected
14:52:29:smx_tester:INFO:	Setting Elink clock mode to 160 MHz
14:52:33:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:52:33:ST3_Shared:INFO:	--------------------------FEB-ASIC--------------------------
14:52:33:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:52:34:febtest:INFO:	Testing FEB with SN 2035
14:52:36:smx_tester:INFO:	Scanning setup
14:52:36:elinks:INFO:	Disabling clock on downlink 0
14:52:36:elinks:INFO:	Disabling clock on downlink 1
14:52:36:elinks:INFO:	Disabling clock on downlink 2
14:52:36:elinks:INFO:	Disabling clock on downlink 3
14:52:36:elinks:INFO:	Disabling clock on downlink 4
14:52:36:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:52:36:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
14:52:37:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:52:37:elinks:INFO:	Disabling clock on downlink 0
14:52:37:elinks:INFO:	Disabling clock on downlink 1
14:52:37:elinks:INFO:	Disabling clock on downlink 2
14:52:37:elinks:INFO:	Disabling clock on downlink 3
14:52:37:elinks:INFO:	Disabling clock on downlink 4
14:52:37:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:52:37:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:52:37:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:52:37:elinks:INFO:	Disabling clock on downlink 0
14:52:37:elinks:INFO:	Disabling clock on downlink 1
14:52:37:elinks:INFO:	Disabling clock on downlink 2
14:52:37:elinks:INFO:	Disabling clock on downlink 3
14:52:37:elinks:INFO:	Disabling clock on downlink 4
14:52:37:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:52:37:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:52:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 16
14:52:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 17
14:52:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 18
14:52:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 19
14:52:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 20
14:52:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 21
14:52:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 22
14:52:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 23
14:52:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
14:52:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
14:52:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
14:52:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
14:52:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
14:52:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
14:52:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
14:52:37:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
14:52:37:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:52:37:elinks:INFO:	Disabling clock on downlink 0
14:52:37:elinks:INFO:	Disabling clock on downlink 1
14:52:37:elinks:INFO:	Disabling clock on downlink 2
14:52:37:elinks:INFO:	Disabling clock on downlink 3
14:52:37:elinks:INFO:	Disabling clock on downlink 4
14:52:37:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:52:37:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
14:52:37:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:52:37:elinks:INFO:	Disabling clock on downlink 0
14:52:37:elinks:INFO:	Disabling clock on downlink 1
14:52:37:elinks:INFO:	Disabling clock on downlink 2
14:52:37:elinks:INFO:	Disabling clock on downlink 3
14:52:37:elinks:INFO:	Disabling clock on downlink 4
14:52:37:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:52:37:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
14:52:37:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:52:37:setup_element:INFO:	Scanning clock phase
14:52:37:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:52:37:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:52:37:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
14:52:37:setup_element:INFO:	Eye window for uplink 16: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:52:37:setup_element:INFO:	Eye window for uplink 17: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:52:37:setup_element:INFO:	Eye window for uplink 18: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:52:37:setup_element:INFO:	Eye window for uplink 19: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:52:37:setup_element:INFO:	Eye window for uplink 20: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:52:37:setup_element:INFO:	Eye window for uplink 21: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:52:37:setup_element:INFO:	Eye window for uplink 22: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:52:37:setup_element:INFO:	Eye window for uplink 23: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:52:37:setup_element:INFO:	Eye window for uplink 24: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:52:37:setup_element:INFO:	Eye window for uplink 25: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:52:37:setup_element:INFO:	Eye window for uplink 26: _______________________________________________________________________XXXXXX___
Clock Delay: 33
14:52:37:setup_element:INFO:	Eye window for uplink 27: _______________________________________________________________________XXXXXX___
Clock Delay: 33
14:52:37:setup_element:INFO:	Eye window for uplink 28: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:52:37:setup_element:INFO:	Eye window for uplink 29: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:52:37:setup_element:INFO:	Eye window for uplink 30: _________________________________________________________________________XXXXXX_
Clock Delay: 35
14:52:37:setup_element:INFO:	Eye window for uplink 31: _________________________________________________________________________XXXXXX_
Clock Delay: 35
14:52:37:setup_element:INFO:	Setting the clock phase to 34 for group 0, downlink 2
14:52:37:setup_element:INFO:	Scanning data phases
14:52:37:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:52:38:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:52:43:setup_element:INFO:	Data phase scan results for group 0, downlink 2
14:52:43:setup_element:INFO:	Eye window for uplink 16: X_________________________________XXXXXX
Data delay found: 17
14:52:43:setup_element:INFO:	Eye window for uplink 17: ________________________________XXXX____
Data delay found: 13
14:52:43:setup_element:INFO:	Eye window for uplink 18: ___________________________________XXXXX
Data delay found: 17
14:52:43:setup_element:INFO:	Eye window for uplink 19: _______________________________XXXXX____
Data delay found: 13
14:52:43:setup_element:INFO:	Eye window for uplink 20: _______________________________XXXX_____
Data delay found: 12
14:52:43:setup_element:INFO:	Eye window for uplink 21: _____________________________XXXXX______
Data delay found: 11
14:52:43:setup_element:INFO:	Eye window for uplink 22: _________________________________XXXX___
Data delay found: 14
14:52:43:setup_element:INFO:	Eye window for uplink 23: _____________________________XXXX_______
Data delay found: 10
14:52:43:setup_element:INFO:	Eye window for uplink 24: __XXXXXX________________________________
Data delay found: 24
14:52:43:setup_element:INFO:	Eye window for uplink 25: ______XXXXX_____________________________
Data delay found: 28
14:52:43:setup_element:INFO:	Eye window for uplink 26: __XXXXX_________________________________
Data delay found: 24
14:52:43:setup_element:INFO:	Eye window for uplink 27: ______XXXXXX____________________________
Data delay found: 28
14:52:43:setup_element:INFO:	Eye window for uplink 28: ________XXXXX___________________________
Data delay found: 30
14:52:43:setup_element:INFO:	Eye window for uplink 29: __________XXXXX_________________________
Data delay found: 32
14:52:43:setup_element:INFO:	Eye window for uplink 30: ___________XXXXXX_______________________
Data delay found: 33
14:52:43:setup_element:INFO:	Eye window for uplink 31: ____________XXXX________________________
Data delay found: 33
14:52:43:setup_element:INFO:	Setting the data phase to 17 for uplink 16
14:52:43:setup_element:INFO:	Setting the data phase to 13 for uplink 17
14:52:43:setup_element:INFO:	Setting the data phase to 17 for uplink 18
14:52:43:setup_element:INFO:	Setting the data phase to 13 for uplink 19
14:52:43:setup_element:INFO:	Setting the data phase to 12 for uplink 20
14:52:43:setup_element:INFO:	Setting the data phase to 11 for uplink 21
14:52:43:setup_element:INFO:	Setting the data phase to 14 for uplink 22
14:52:43:setup_element:INFO:	Setting the data phase to 10 for uplink 23
14:52:43:setup_element:INFO:	Setting the data phase to 24 for uplink 24
14:52:43:setup_element:INFO:	Setting the data phase to 28 for uplink 25
14:52:43:setup_element:INFO:	Setting the data phase to 24 for uplink 26
14:52:43:setup_element:INFO:	Setting the data phase to 28 for uplink 27
14:52:43:setup_element:INFO:	Setting the data phase to 30 for uplink 28
14:52:43:setup_element:INFO:	Setting the data phase to 32 for uplink 29
14:52:43:setup_element:INFO:	Setting the data phase to 33 for uplink 30
14:52:43:setup_element:INFO:	Setting the data phase to 33 for uplink 31
14:52:43:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 34
    Window Length: 72
    Eye Windows:
      Uplink 16: __________________________________________________________________________XXXXX_
      Uplink 17: __________________________________________________________________________XXXXX_
      Uplink 18: __________________________________________________________________________XXXXX_
      Uplink 19: __________________________________________________________________________XXXXX_
      Uplink 20: ________________________________________________________________________XXXXXX__
      Uplink 21: ________________________________________________________________________XXXXXX__
      Uplink 22: ________________________________________________________________________XXXXXX__
      Uplink 23: ________________________________________________________________________XXXXXX__
      Uplink 24: _________________________________________________________________________XXXXX__
      Uplink 25: _________________________________________________________________________XXXXX__
      Uplink 26: _______________________________________________________________________XXXXXX___
      Uplink 27: _______________________________________________________________________XXXXXX___
      Uplink 28: _________________________________________________________________________XXXXX__
      Uplink 29: _________________________________________________________________________XXXXX__
      Uplink 30: _________________________________________________________________________XXXXXX_
      Uplink 31: _________________________________________________________________________XXXXXX_
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 17
      Window Length: 33
      Eye Window: X_________________________________XXXXXX
    Uplink 17:
      Optimal Phase: 13
      Window Length: 36
      Eye Window: ________________________________XXXX____
    Uplink 18:
      Optimal Phase: 17
      Window Length: 35
      Eye Window: ___________________________________XXXXX
    Uplink 19:
      Optimal Phase: 13
      Window Length: 35
      Eye Window: _______________________________XXXXX____
    Uplink 20:
      Optimal Phase: 12
      Window Length: 36
      Eye Window: _______________________________XXXX_____
    Uplink 21:
      Optimal Phase: 11
      Window Length: 35
      Eye Window: _____________________________XXXXX______
    Uplink 22:
      Optimal Phase: 14
      Window Length: 36
      Eye Window: _________________________________XXXX___
    Uplink 23:
      Optimal Phase: 10
      Window Length: 36
      Eye Window: _____________________________XXXX_______
    Uplink 24:
      Optimal Phase: 24
      Window Length: 34
      Eye Window: __XXXXXX________________________________
    Uplink 25:
      Optimal Phase: 28
      Window Length: 35
      Eye Window: ______XXXXX_____________________________
    Uplink 26:
      Optimal Phase: 24
      Window Length: 35
      Eye Window: __XXXXX_________________________________
    Uplink 27:
      Optimal Phase: 28
      Window Length: 34
      Eye Window: ______XXXXXX____________________________
    Uplink 28:
      Optimal Phase: 30
      Window Length: 35
      Eye Window: ________XXXXX___________________________
    Uplink 29:
      Optimal Phase: 32
      Window Length: 35
      Eye Window: __________XXXXX_________________________
    Uplink 30:
      Optimal Phase: 33
      Window Length: 34
      Eye Window: ___________XXXXXX_______________________
    Uplink 31:
      Optimal Phase: 33
      Window Length: 36
      Eye Window: ____________XXXX________________________
]
14:52:43:setup_element:INFO:	Beginning SMX ASICs map scan
14:52:43:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:52:43:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:52:43:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
14:52:43:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
14:52:43:uplink:INFO:	Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
14:52:43:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 23
14:52:43:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 22
14:52:43:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
14:52:43:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
14:52:43:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 21
14:52:43:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 20
14:52:43:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
14:52:43:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
14:52:43:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 19
14:52:44:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 18
14:52:44:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
14:52:44:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
14:52:44:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 17
14:52:44:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 16
14:52:44:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
14:52:44:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
14:52:45:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 34
    Window Length: 72
    Eye Windows:
      Uplink 16: __________________________________________________________________________XXXXX_
      Uplink 17: __________________________________________________________________________XXXXX_
      Uplink 18: __________________________________________________________________________XXXXX_
      Uplink 19: __________________________________________________________________________XXXXX_
      Uplink 20: ________________________________________________________________________XXXXXX__
      Uplink 21: ________________________________________________________________________XXXXXX__
      Uplink 22: ________________________________________________________________________XXXXXX__
      Uplink 23: ________________________________________________________________________XXXXXX__
      Uplink 24: _________________________________________________________________________XXXXX__
      Uplink 25: _________________________________________________________________________XXXXX__
      Uplink 26: _______________________________________________________________________XXXXXX___
      Uplink 27: _______________________________________________________________________XXXXXX___
      Uplink 28: _________________________________________________________________________XXXXX__
      Uplink 29: _________________________________________________________________________XXXXX__
      Uplink 30: _________________________________________________________________________XXXXXX_
      Uplink 31: _________________________________________________________________________XXXXXX_
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 17
      Window Length: 33
      Eye Window: X_________________________________XXXXXX
    Uplink 17:
      Optimal Phase: 13
      Window Length: 36
      Eye Window: ________________________________XXXX____
    Uplink 18:
      Optimal Phase: 17
      Window Length: 35
      Eye Window: ___________________________________XXXXX
    Uplink 19:
      Optimal Phase: 13
      Window Length: 35
      Eye Window: _______________________________XXXXX____
    Uplink 20:
      Optimal Phase: 12
      Window Length: 36
      Eye Window: _______________________________XXXX_____
    Uplink 21:
      Optimal Phase: 11
      Window Length: 35
      Eye Window: _____________________________XXXXX______
    Uplink 22:
      Optimal Phase: 14
      Window Length: 36
      Eye Window: _________________________________XXXX___
    Uplink 23:
      Optimal Phase: 10
      Window Length: 36
      Eye Window: _____________________________XXXX_______
    Uplink 24:
      Optimal Phase: 24
      Window Length: 34
      Eye Window: __XXXXXX________________________________
    Uplink 25:
      Optimal Phase: 28
      Window Length: 35
      Eye Window: ______XXXXX_____________________________
    Uplink 26:
      Optimal Phase: 24
      Window Length: 35
      Eye Window: __XXXXX_________________________________
    Uplink 27:
      Optimal Phase: 28
      Window Length: 34
      Eye Window: ______XXXXXX____________________________
    Uplink 28:
      Optimal Phase: 30
      Window Length: 35
      Eye Window: ________XXXXX___________________________
    Uplink 29:
      Optimal Phase: 32
      Window Length: 35
      Eye Window: __________XXXXX_________________________
    Uplink 30:
      Optimal Phase: 33
      Window Length: 34
      Eye Window: ___________XXXXXX_______________________
    Uplink 31:
      Optimal Phase: 33
      Window Length: 36
      Eye Window: ____________XXXX________________________

14:52:45:setup_element:INFO:	Performing Elink synchronization
14:52:45:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:52:45:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:52:45:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
14:52:45:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
14:52:45:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
14:52:45:uplink:INFO:	Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
14:52:46:ST3_emu:INFO:	Number of chips: 8
addr  |  upli  |  dwnli  |  grp |  uplinks | uplinks_map
   0  |   [0]   |  2  |  0  |     [23]     |  [(0, 23), (1, 22)]
   1  |   [0]   |  2  |  0  |     [30]     |  [(0, 30), (1, 31)]
   2  |   [0]   |  2  |  0  |     [21]     |  [(0, 21), (1, 20)]
   3  |   [0]   |  2  |  0  |     [28]     |  [(0, 28), (1, 29)]
   4  |   [0]   |  2  |  0  |     [19]     |  [(0, 19), (1, 18)]
   5  |   [0]   |  2  |  0  |     [26]     |  [(0, 26), (1, 27)]
   6  |   [0]   |  2  |  0  |     [17]     |  [(0, 17), (1, 16)]
   7  |   [0]   |  2  |  0  |     [24]     |  [(0, 24), (1, 25)]
FEB type: B FEB_A: 0 FEB_B: 1
14:52:47:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:52:47:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  50.4 | 1165.6
14:52:47:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  47.3 | 1183.3
14:52:48:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  31.4 | 1236.2
14:52:48:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  47.3 | 1183.3
14:52:48:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  21.9 | 1253.7
14:52:48:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  44.1 | 1189.2
14:52:49:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  15.6 | 1282.9
14:52:49:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  37.7 | 1206.9
14:52:49:ST3_smx:INFO:	Configuring SMX FAST
14:52:51:ST3_smx:INFO:	chip: 23-0 	 47.250730 C 	 1177.390875 mV
14:52:51:ST3_smx:INFO:		Electrons
14:52:51:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:52:53:ST3_smx:INFO:	----> Checking Analog response
14:52:53:ST3_smx:INFO:	----> Checking broken channels
14:52:54:ST3_smx:INFO:	Total # broken ch: 0
14:52:54:ST3_smx:INFO:	List FAST: []
14:52:54:ST3_smx:INFO:	List SLOW: []
14:52:54:ST3_smx:INFO:		Holes
14:52:54:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:52:56:ST3_smx:INFO:	----> Checking Analog response
14:52:56:ST3_smx:INFO:	----> Checking broken channels
14:52:56:ST3_smx:INFO:	Total # broken ch: 0
14:52:56:ST3_smx:INFO:	List FAST: []
14:52:56:ST3_smx:INFO:	List SLOW: []
14:52:56:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:52:56:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  50.4 | 1171.5
14:52:56:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  47.3 | 1183.3
14:52:57:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  31.4 | 1236.2
14:52:57:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  47.3 | 1183.3
14:52:57:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  21.9 | 1259.6
14:52:57:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  47.3 | 1189.2
14:52:57:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  18.7 | 1282.9
14:52:58:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  37.7 | 1206.9
14:52:58:ST3_smx:INFO:	Configuring SMX FAST
14:53:00:ST3_smx:INFO:	chip: 30-1 	 50.430383 C 	 1177.390875 mV
14:53:00:ST3_smx:INFO:		Electrons
14:53:00:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:02:ST3_smx:INFO:	----> Checking Analog response
14:53:02:ST3_smx:INFO:	----> Checking broken channels
14:53:02:ST3_smx:INFO:	Total # broken ch: 0
14:53:02:ST3_smx:INFO:	List FAST: []
14:53:02:ST3_smx:INFO:	List SLOW: []
14:53:02:ST3_smx:INFO:		Holes
14:53:02:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:04:ST3_smx:INFO:	----> Checking Analog response
14:53:04:ST3_smx:INFO:	----> Checking broken channels
14:53:05:ST3_smx:INFO:	Total # broken ch: 0
14:53:05:ST3_smx:INFO:	List FAST: []
14:53:05:ST3_smx:INFO:	List SLOW: []
14:53:05:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:53:05:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  47.3 | 1171.5
14:53:05:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  53.6 | 1171.5
14:53:05:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  31.4 | 1236.2
14:53:05:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  47.3 | 1183.3
14:53:06:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  25.1 | 1253.7
14:53:06:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  44.1 | 1189.2
14:53:06:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  18.7 | 1282.9
14:53:06:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  37.7 | 1212.7
14:53:07:ST3_smx:INFO:	Configuring SMX FAST
14:53:09:ST3_smx:INFO:	chip: 21-2 	 44.073563 C 	 1206.851500 mV
14:53:09:ST3_smx:INFO:		Electrons
14:53:09:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:11:ST3_smx:INFO:	----> Checking Analog response
14:53:11:ST3_smx:INFO:	----> Checking broken channels
14:53:11:ST3_smx:INFO:	Total # broken ch: 0
14:53:11:ST3_smx:INFO:	List FAST: []
14:53:11:ST3_smx:INFO:	List SLOW: []
14:53:11:ST3_smx:INFO:		Holes
14:53:11:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:13:ST3_smx:INFO:	----> Checking Analog response
14:53:13:ST3_smx:INFO:	----> Checking broken channels
14:53:14:ST3_smx:INFO:	Total # broken ch: 0
14:53:14:ST3_smx:INFO:	List FAST: []
14:53:14:ST3_smx:INFO:	List SLOW: []
14:53:14:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:53:14:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  47.3 | 1177.4
14:53:14:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  53.6 | 1171.5
14:53:14:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  44.1 | 1201.0
14:53:14:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  47.3 | 1183.3
14:53:15:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  25.1 | 1253.7
14:53:15:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  47.3 | 1189.2
14:53:15:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  18.7 | 1288.7
14:53:15:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  37.7 | 1206.9
14:53:16:ST3_smx:INFO:	Configuring SMX FAST
14:53:18:ST3_smx:INFO:	chip: 28-3 	 50.430383 C 	 1171.483840 mV
14:53:18:ST3_smx:INFO:		Electrons
14:53:18:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:20:ST3_smx:INFO:	----> Checking Analog response
14:53:20:ST3_smx:INFO:	----> Checking broken channels
14:53:20:ST3_smx:INFO:	Total # broken ch: 0
14:53:20:ST3_smx:INFO:	List FAST: []
14:53:20:ST3_smx:INFO:	List SLOW: []
14:53:20:ST3_smx:INFO:		Holes
14:53:20:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:22:ST3_smx:INFO:	----> Checking Analog response
14:53:22:ST3_smx:INFO:	----> Checking broken channels
14:53:22:ST3_smx:INFO:	Total # broken ch: 0
14:53:22:ST3_smx:INFO:	List FAST: []
14:53:22:ST3_smx:INFO:	List SLOW: []
14:53:22:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:53:23:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  50.4 | 1177.4
14:53:23:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  53.6 | 1171.5
14:53:23:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  44.1 | 1201.0
14:53:23:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  53.6 | 1171.5
14:53:23:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  25.1 | 1259.6
14:53:24:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  47.3 | 1189.2
14:53:24:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  18.7 | 1288.7
14:53:24:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  37.7 | 1212.7
14:53:25:ST3_smx:INFO:	Configuring SMX FAST
14:53:27:ST3_smx:INFO:	chip: 19-4 	 25.062742 C 	 1259.567515 mV
14:53:27:ST3_smx:INFO:		Electrons
14:53:27:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:29:ST3_smx:INFO:	----> Checking Analog response
14:53:29:ST3_smx:INFO:	----> Checking broken channels
14:53:29:ST3_smx:INFO:	Total # broken ch: 0
14:53:29:ST3_smx:INFO:	List FAST: []
14:53:29:ST3_smx:INFO:	List SLOW: []
14:53:29:ST3_smx:INFO:		Holes
14:53:29:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:31:ST3_smx:INFO:	----> Checking Analog response
14:53:31:ST3_smx:INFO:	----> Checking broken channels
14:53:31:ST3_smx:INFO:	Total # broken ch: 0
14:53:31:ST3_smx:INFO:	List FAST: []
14:53:31:ST3_smx:INFO:	List SLOW: []
14:53:31:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:53:31:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  50.4 | 1177.4
14:53:31:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  53.6 | 1171.5
14:53:32:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  44.1 | 1206.9
14:53:32:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  53.6 | 1171.5
14:53:32:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  28.2 | 1253.7
14:53:32:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  47.3 | 1189.2
14:53:32:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  18.7 | 1288.7
14:53:33:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  37.7 | 1212.7
14:53:33:ST3_smx:INFO:	Configuring SMX FAST
14:53:35:ST3_smx:INFO:	chip: 26-5 	 47.250730 C 	 1195.082160 mV
14:53:35:ST3_smx:INFO:		Electrons
14:53:35:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:37:ST3_smx:INFO:	----> Checking Analog response
14:53:37:ST3_smx:INFO:	----> Checking broken channels
14:53:37:ST3_smx:INFO:	Total # broken ch: 0
14:53:37:ST3_smx:INFO:	List FAST: []
14:53:37:ST3_smx:INFO:	List SLOW: []
14:53:37:ST3_smx:INFO:		Holes
14:53:37:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:39:ST3_smx:INFO:	----> Checking Analog response
14:53:39:ST3_smx:INFO:	----> Checking broken channels
14:53:39:ST3_smx:INFO:	Total # broken ch: 0
14:53:39:ST3_smx:INFO:	List FAST: []
14:53:39:ST3_smx:INFO:	List SLOW: []
14:53:39:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:53:39:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  50.4 | 1177.4
14:53:40:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  53.6 | 1171.5
14:53:40:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  44.1 | 1206.9
14:53:40:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  53.6 | 1171.5
14:53:40:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  28.2 | 1259.6
14:53:41:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  47.3 | 1195.1
14:53:41:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  21.9 | 1288.7
14:53:41:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  37.7 | 1212.7
14:53:42:ST3_smx:INFO:	Configuring SMX FAST
14:53:44:ST3_smx:INFO:	chip: 17-6 	 28.225000 C 	 1253.730060 mV
14:53:44:ST3_smx:INFO:		Electrons
14:53:44:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:46:ST3_smx:INFO:	----> Checking Analog response
14:53:46:ST3_smx:INFO:	----> Checking broken channels
14:53:46:ST3_smx:INFO:	Total # broken ch: 0
14:53:46:ST3_smx:INFO:	List FAST: []
14:53:46:ST3_smx:INFO:	List SLOW: []
14:53:46:ST3_smx:INFO:		Holes
14:53:46:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:48:ST3_smx:INFO:	----> Checking Analog response
14:53:48:ST3_smx:INFO:	----> Checking broken channels
14:53:48:ST3_smx:INFO:	Total # broken ch: 0
14:53:48:ST3_smx:INFO:	List FAST: []
14:53:48:ST3_smx:INFO:	List SLOW: []
14:53:48:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:53:48:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  50.4 | 1177.4
14:53:48:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  53.6 | 1177.4
14:53:48:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  44.1 | 1206.9
14:53:49:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  53.6 | 1171.5
14:53:49:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  28.2 | 1259.6
14:53:49:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  47.3 | 1195.1
14:53:49:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  31.4 | 1253.7
14:53:50:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  37.7 | 1212.7
14:53:50:ST3_smx:INFO:	Configuring SMX FAST
14:53:52:ST3_smx:INFO:	chip: 24-7 	 47.250730 C 	 1189.190035 mV
14:53:52:ST3_smx:INFO:		Electrons
14:53:52:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:54:ST3_smx:INFO:	----> Checking Analog response
14:53:54:ST3_smx:INFO:	----> Checking broken channels
14:53:54:ST3_smx:INFO:	Total # broken ch: 0
14:53:54:ST3_smx:INFO:	List FAST: []
14:53:54:ST3_smx:INFO:	List SLOW: []
14:53:54:ST3_smx:INFO:		Holes
14:53:54:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:56:ST3_smx:INFO:	----> Checking Analog response
14:53:56:ST3_smx:INFO:	----> Checking broken channels
14:53:56:ST3_smx:INFO:	Total # broken ch: 0
14:53:56:ST3_smx:INFO:	List FAST: []
14:53:56:ST3_smx:INFO:	List SLOW: []
14:53:56:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:53:56:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  50.4 | 1177.4
14:53:57:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  53.6 | 1177.4
14:53:57:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  44.1 | 1206.9
14:53:57:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  53.6 | 1171.5
14:53:57:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  28.2 | 1259.6
14:53:57:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  47.3 | 1195.1
14:53:58:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  31.4 | 1253.7
14:53:58:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  47.3 | 1183.3
############################################################
#                   S U M M A R Y                          #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '24_02_22-14_52_33', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'KIT', 'SITE': 'KIT', 'SETUP': 'KIT_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-007-083-04', 'FUSED_ID': 6359364699116565812, 'HW_ADDR': 7, 'UPLINK': 24, 'VERS_NO': '', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'FEB_SN': '2035', 'FEB_TYPE': 8.2, 'FEB_UPLINKS': 2, 'FEB_A': 0, 'FEB_B': 1, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.800', '1.8920', '2.200', '2.5240', '0.000', '0.0000', '7.001', '1.6690'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 150, 'PlsLoop': 500, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 24_02_22-14_52_33
OPERATOR  : Alois Alzheimer
SITE      : KIT
SETUP     : KIT_TEST_SETUP_1
Set-ID    : 
---------------------------------------
MODULE_NAME : 
FEB_SN : 2035
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 0
FEB_B : 1
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.800', '1.8920', '2.200', '2.5240', '0.000', '0.0000', '7.001', '1.6690']
VI_after__Init : ['2.800', '1.9910', '2.200', '0.3194', '0.000', '0.0000', '7.000', '1.6630']
VI_at__the_End : ['2.800', '1.9910', '2.200', '0.3194', '0.000', '0.0000', '7.000', '1.6630']