DTL-STS tests database

FEB_2035 22.02.24 15:10:10

link:
...SMX_0.root
link: XA-000-08-002-000-007-031-01
...SMX_2.root
link: XA-000-08-002-000-007-041-08
...SMX_4.root
link: XA-000-08-002-000-007-047-08
...SMX_6.root
link: XA-000-08-002-000-007-199-09
...SMX_1.root
link: XA-000-08-002-000-007-198-09
...SMX_3.root
link: XA-000-08-002-000-007-127-10
...SMX_5.root
link: XA-000-08-002-000-007-083-04
...SMX_7.root
Info
            15:09:56:ST3_hmp4040:INFO:	ROHDE&SCHWARZ,HMP4040,110099,HW50020003/SW2.72
15:09:57:febtest:INFO:	FEB 8-2 selected
15:09:57:smx_tester:INFO:	Setting Elink clock mode to 160 MHz
15:09:57:febtest:INFO:	FEB type: 8.2
15:09:57:febtest:INFO:	FEB SN: 3000
15:09:57:febtest:INFO:	FEB 8-2 selected
15:09:57:smx_tester:INFO:	Setting Elink clock mode to 160 MHz
15:10:08:febtest:INFO:	FEB 8-2 selected
15:10:08:smx_tester:INFO:	Setting Elink clock mode to 160 MHz
15:10:08:febtest:INFO:	FEB type: 8.2
15:10:08:febtest:INFO:	FEB SN: 2035
15:10:10:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:10:10:ST3_Shared:INFO:	--------------------------FEB-ASIC--------------------------
15:10:10:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
15:10:10:febtest:INFO:	Testing FEB with SN 2035
15:10:13:smx_tester:INFO:	Scanning setup
15:10:13:elinks:INFO:	Disabling clock on downlink 0
15:10:13:elinks:INFO:	Disabling clock on downlink 1
15:10:13:elinks:INFO:	Disabling clock on downlink 2
15:10:13:elinks:INFO:	Disabling clock on downlink 3
15:10:13:elinks:INFO:	Disabling clock on downlink 4
15:10:13:setup_element:INFO:	Checking SOS, encoding_mode: SOS
15:10:13:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
15:10:13:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
15:10:13:elinks:INFO:	Disabling clock on downlink 0
15:10:13:elinks:INFO:	Disabling clock on downlink 1
15:10:13:elinks:INFO:	Disabling clock on downlink 2
15:10:13:elinks:INFO:	Disabling clock on downlink 3
15:10:13:elinks:INFO:	Disabling clock on downlink 4
15:10:13:setup_element:INFO:	Checking SOS, encoding_mode: SOS
15:10:13:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
15:10:13:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
15:10:13:elinks:INFO:	Disabling clock on downlink 0
15:10:13:elinks:INFO:	Disabling clock on downlink 1
15:10:13:elinks:INFO:	Disabling clock on downlink 2
15:10:13:elinks:INFO:	Disabling clock on downlink 3
15:10:13:elinks:INFO:	Disabling clock on downlink 4
15:10:13:setup_element:INFO:	Checking SOS, encoding_mode: SOS
15:10:13:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
15:10:13:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 16
15:10:13:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 17
15:10:14:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 18
15:10:14:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 19
15:10:14:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 20
15:10:14:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 21
15:10:14:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 22
15:10:14:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 23
15:10:14:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 24
15:10:14:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 25
15:10:14:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 26
15:10:14:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 27
15:10:14:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 28
15:10:14:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 29
15:10:14:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 30
15:10:14:setup_element:INFO:	SOS detected for group 0, downlink 2, uplink 31
15:10:14:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
15:10:14:elinks:INFO:	Disabling clock on downlink 0
15:10:14:elinks:INFO:	Disabling clock on downlink 1
15:10:14:elinks:INFO:	Disabling clock on downlink 2
15:10:14:elinks:INFO:	Disabling clock on downlink 3
15:10:14:elinks:INFO:	Disabling clock on downlink 4
15:10:14:setup_element:INFO:	Checking SOS, encoding_mode: SOS
15:10:14:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
15:10:14:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
15:10:14:elinks:INFO:	Disabling clock on downlink 0
15:10:14:elinks:INFO:	Disabling clock on downlink 1
15:10:14:elinks:INFO:	Disabling clock on downlink 2
15:10:14:elinks:INFO:	Disabling clock on downlink 3
15:10:14:elinks:INFO:	Disabling clock on downlink 4
15:10:14:setup_element:INFO:	Checking SOS, encoding_mode: SOS
15:10:14:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
15:10:14:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
15:10:14:setup_element:INFO:	Scanning clock phase
15:10:14:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
15:10:14:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:10:14:setup_element:INFO:	Clock phase scan results for group 0, downlink 2
15:10:14:setup_element:INFO:	Eye window for uplink 16: __________________________________________________________________________XXXXX_
Clock Delay: 36
15:10:14:setup_element:INFO:	Eye window for uplink 17: __________________________________________________________________________XXXXX_
Clock Delay: 36
15:10:14:setup_element:INFO:	Eye window for uplink 18: __________________________________________________________________________XXXXX_
Clock Delay: 36
15:10:14:setup_element:INFO:	Eye window for uplink 19: __________________________________________________________________________XXXXX_
Clock Delay: 36
15:10:14:setup_element:INFO:	Eye window for uplink 20: ________________________________________________________________________________
Clock Delay: 40
15:10:14:setup_element:INFO:	Eye window for uplink 21: ________________________________________________________________________________
Clock Delay: 40
15:10:14:setup_element:INFO:	Eye window for uplink 22: ________________________________________________________________________XXXXXX__
Clock Delay: 34
15:10:14:setup_element:INFO:	Eye window for uplink 23: ________________________________________________________________________XXXXXX__
Clock Delay: 34
15:10:14:setup_element:INFO:	Eye window for uplink 24: _________________________________________________________________________XXXXX__
Clock Delay: 35
15:10:14:setup_element:INFO:	Eye window for uplink 25: _________________________________________________________________________XXXXX__
Clock Delay: 35
15:10:14:setup_element:INFO:	Eye window for uplink 26: ________________________________________________________________________XXXXXX__
Clock Delay: 34
15:10:14:setup_element:INFO:	Eye window for uplink 27: ________________________________________________________________________XXXXXX__
Clock Delay: 34
15:10:14:setup_element:INFO:	Eye window for uplink 28: _________________________________________________________________________XXXXX__
Clock Delay: 35
15:10:14:setup_element:INFO:	Eye window for uplink 29: _________________________________________________________________________XXXXX__
Clock Delay: 35
15:10:14:setup_element:INFO:	Eye window for uplink 30: __________________________________________________________________________XXXXX_
Clock Delay: 36
15:10:14:setup_element:INFO:	Eye window for uplink 31: __________________________________________________________________________XXXXX_
Clock Delay: 36
15:10:14:setup_element:INFO:	Setting the clock phase to 35 for group 0, downlink 2
15:10:14:setup_element:INFO:	Scanning data phases
15:10:14:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
15:10:14:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:10:19:setup_element:INFO:	Data phase scan results for group 0, downlink 2
15:10:19:setup_element:INFO:	Eye window for uplink 16: X_________________________________XXXXXX
Data delay found: 17
15:10:19:setup_element:INFO:	Eye window for uplink 17: _______________________________XXXXX____
Data delay found: 13
15:10:19:setup_element:INFO:	Eye window for uplink 18: __________________________________XXXXX_
Data delay found: 16
15:10:19:setup_element:INFO:	Eye window for uplink 19: _______________________________XXXXX____
Data delay found: 13
15:10:19:setup_element:INFO:	Eye window for uplink 20: _____________________________XXXXX______
Data delay found: 11
15:10:19:setup_element:INFO:	Eye window for uplink 21: _____________________________XXXX_______
Data delay found: 10
15:10:19:setup_element:INFO:	Eye window for uplink 22: ________________________________XXXXX___
Data delay found: 14
15:10:19:setup_element:INFO:	Eye window for uplink 23: ____________________________XXXXX_______
Data delay found: 10
15:10:19:setup_element:INFO:	Eye window for uplink 24: __XXXXX_________________________________
Data delay found: 24
15:10:19:setup_element:INFO:	Eye window for uplink 25: _____XXXXX______________________________
Data delay found: 27
15:10:19:setup_element:INFO:	Eye window for uplink 26: _XXXXXX_________________________________
Data delay found: 23
15:10:19:setup_element:INFO:	Eye window for uplink 27: _____XXXXXXX____________________________
Data delay found: 28
15:10:19:setup_element:INFO:	Eye window for uplink 28: _______XXXXX____________________________
Data delay found: 29
15:10:19:setup_element:INFO:	Eye window for uplink 29: _________XXXXX__________________________
Data delay found: 31
15:10:19:setup_element:INFO:	Eye window for uplink 30: __________XXXXXX________________________
Data delay found: 32
15:10:19:setup_element:INFO:	Eye window for uplink 31: ___________XXXX_________________________
Data delay found: 32
15:10:19:setup_element:INFO:	Setting the data phase to 17 for uplink 16
15:10:19:setup_element:INFO:	Setting the data phase to 13 for uplink 17
15:10:19:setup_element:INFO:	Setting the data phase to 16 for uplink 18
15:10:19:setup_element:INFO:	Setting the data phase to 13 for uplink 19
15:10:19:setup_element:INFO:	Setting the data phase to 11 for uplink 20
15:10:19:setup_element:INFO:	Setting the data phase to 10 for uplink 21
15:10:19:setup_element:INFO:	Setting the data phase to 14 for uplink 22
15:10:19:setup_element:INFO:	Setting the data phase to 10 for uplink 23
15:10:19:setup_element:INFO:	Setting the data phase to 24 for uplink 24
15:10:19:setup_element:INFO:	Setting the data phase to 27 for uplink 25
15:10:19:setup_element:INFO:	Setting the data phase to 23 for uplink 26
15:10:19:setup_element:INFO:	Setting the data phase to 28 for uplink 27
15:10:19:setup_element:INFO:	Setting the data phase to 29 for uplink 28
15:10:19:setup_element:INFO:	Setting the data phase to 31 for uplink 29
15:10:19:setup_element:INFO:	Setting the data phase to 32 for uplink 30
15:10:19:setup_element:INFO:	Setting the data phase to 32 for uplink 31
15:10:19:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 35
    Window Length: 73
    Eye Windows:
      Uplink 16: __________________________________________________________________________XXXXX_
      Uplink 17: __________________________________________________________________________XXXXX_
      Uplink 18: __________________________________________________________________________XXXXX_
      Uplink 19: __________________________________________________________________________XXXXX_
      Uplink 20: ________________________________________________________________________________
      Uplink 21: ________________________________________________________________________________
      Uplink 22: ________________________________________________________________________XXXXXX__
      Uplink 23: ________________________________________________________________________XXXXXX__
      Uplink 24: _________________________________________________________________________XXXXX__
      Uplink 25: _________________________________________________________________________XXXXX__
      Uplink 26: ________________________________________________________________________XXXXXX__
      Uplink 27: ________________________________________________________________________XXXXXX__
      Uplink 28: _________________________________________________________________________XXXXX__
      Uplink 29: _________________________________________________________________________XXXXX__
      Uplink 30: __________________________________________________________________________XXXXX_
      Uplink 31: __________________________________________________________________________XXXXX_
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 17
      Window Length: 33
      Eye Window: X_________________________________XXXXXX
    Uplink 17:
      Optimal Phase: 13
      Window Length: 35
      Eye Window: _______________________________XXXXX____
    Uplink 18:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 19:
      Optimal Phase: 13
      Window Length: 35
      Eye Window: _______________________________XXXXX____
    Uplink 20:
      Optimal Phase: 11
      Window Length: 35
      Eye Window: _____________________________XXXXX______
    Uplink 21:
      Optimal Phase: 10
      Window Length: 36
      Eye Window: _____________________________XXXX_______
    Uplink 22:
      Optimal Phase: 14
      Window Length: 35
      Eye Window: ________________________________XXXXX___
    Uplink 23:
      Optimal Phase: 10
      Window Length: 35
      Eye Window: ____________________________XXXXX_______
    Uplink 24:
      Optimal Phase: 24
      Window Length: 35
      Eye Window: __XXXXX_________________________________
    Uplink 25:
      Optimal Phase: 27
      Window Length: 35
      Eye Window: _____XXXXX______________________________
    Uplink 26:
      Optimal Phase: 23
      Window Length: 34
      Eye Window: _XXXXXX_________________________________
    Uplink 27:
      Optimal Phase: 28
      Window Length: 33
      Eye Window: _____XXXXXXX____________________________
    Uplink 28:
      Optimal Phase: 29
      Window Length: 35
      Eye Window: _______XXXXX____________________________
    Uplink 29:
      Optimal Phase: 31
      Window Length: 35
      Eye Window: _________XXXXX__________________________
    Uplink 30:
      Optimal Phase: 32
      Window Length: 34
      Eye Window: __________XXXXXX________________________
    Uplink 31:
      Optimal Phase: 32
      Window Length: 36
      Eye Window: ___________XXXX_________________________
]
15:10:19:setup_element:INFO:	Beginning SMX ASICs map scan
15:10:19:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
15:10:19:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:10:19:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
15:10:19:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
15:10:19:uplink:INFO:	Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:10:19:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 23
15:10:19:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 22
15:10:20:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 30
15:10:20:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 31
15:10:20:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 21
15:10:20:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 20
15:10:20:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 28
15:10:20:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 29
15:10:20:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 19
15:10:20:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 18
15:10:20:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 26
15:10:20:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 27
15:10:21:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 17
15:10:21:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 16
15:10:21:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 24
15:10:21:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 25
15:10:22:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 2
  Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
  Clock Phase Characteristic:
    Optimal Phase: 35
    Window Length: 73
    Eye Windows:
      Uplink 16: __________________________________________________________________________XXXXX_
      Uplink 17: __________________________________________________________________________XXXXX_
      Uplink 18: __________________________________________________________________________XXXXX_
      Uplink 19: __________________________________________________________________________XXXXX_
      Uplink 20: ________________________________________________________________________________
      Uplink 21: ________________________________________________________________________________
      Uplink 22: ________________________________________________________________________XXXXXX__
      Uplink 23: ________________________________________________________________________XXXXXX__
      Uplink 24: _________________________________________________________________________XXXXX__
      Uplink 25: _________________________________________________________________________XXXXX__
      Uplink 26: ________________________________________________________________________XXXXXX__
      Uplink 27: ________________________________________________________________________XXXXXX__
      Uplink 28: _________________________________________________________________________XXXXX__
      Uplink 29: _________________________________________________________________________XXXXX__
      Uplink 30: __________________________________________________________________________XXXXX_
      Uplink 31: __________________________________________________________________________XXXXX_
  Data phase characteristics:
    Uplink 16:
      Optimal Phase: 17
      Window Length: 33
      Eye Window: X_________________________________XXXXXX
    Uplink 17:
      Optimal Phase: 13
      Window Length: 35
      Eye Window: _______________________________XXXXX____
    Uplink 18:
      Optimal Phase: 16
      Window Length: 35
      Eye Window: __________________________________XXXXX_
    Uplink 19:
      Optimal Phase: 13
      Window Length: 35
      Eye Window: _______________________________XXXXX____
    Uplink 20:
      Optimal Phase: 11
      Window Length: 35
      Eye Window: _____________________________XXXXX______
    Uplink 21:
      Optimal Phase: 10
      Window Length: 36
      Eye Window: _____________________________XXXX_______
    Uplink 22:
      Optimal Phase: 14
      Window Length: 35
      Eye Window: ________________________________XXXXX___
    Uplink 23:
      Optimal Phase: 10
      Window Length: 35
      Eye Window: ____________________________XXXXX_______
    Uplink 24:
      Optimal Phase: 24
      Window Length: 35
      Eye Window: __XXXXX_________________________________
    Uplink 25:
      Optimal Phase: 27
      Window Length: 35
      Eye Window: _____XXXXX______________________________
    Uplink 26:
      Optimal Phase: 23
      Window Length: 34
      Eye Window: _XXXXXX_________________________________
    Uplink 27:
      Optimal Phase: 28
      Window Length: 33
      Eye Window: _____XXXXXXX____________________________
    Uplink 28:
      Optimal Phase: 29
      Window Length: 35
      Eye Window: _______XXXXX____________________________
    Uplink 29:
      Optimal Phase: 31
      Window Length: 35
      Eye Window: _________XXXXX__________________________
    Uplink 30:
      Optimal Phase: 32
      Window Length: 34
      Eye Window: __________XXXXXX________________________
    Uplink 31:
      Optimal Phase: 32
      Window Length: 36
      Eye Window: ___________XXXX_________________________

15:10:22:setup_element:INFO:	Performing Elink synchronization
15:10:22:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
15:10:22:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [2]
15:10:22:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [2]
15:10:22:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [2]
15:10:22:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 2
15:10:22:uplink:INFO:	Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
15:10:22:ST3_emu:INFO:	Number of chips: 8
addr  |  upli  |  dwnli  |  grp |  uplinks | uplinks_map
   0  |   [0]   |  2  |  0  |     [23]     |  [(0, 23), (1, 22)]
   1  |   [0]   |  2  |  0  |     [30]     |  [(0, 30), (1, 31)]
   2  |   [0]   |  2  |  0  |     [21]     |  [(0, 21), (1, 20)]
   3  |   [0]   |  2  |  0  |     [28]     |  [(0, 28), (1, 29)]
   4  |   [0]   |  2  |  0  |     [19]     |  [(0, 19), (1, 18)]
   5  |   [0]   |  2  |  0  |     [26]     |  [(0, 26), (1, 27)]
   6  |   [0]   |  2  |  0  |     [17]     |  [(0, 17), (1, 16)]
   7  |   [0]   |  2  |  0  |     [24]     |  [(0, 24), (1, 25)]
FEB type: B FEB_A: 0 FEB_B: 1
15:10:24:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
15:10:24:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  50.4 | 1159.7
15:10:24:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  44.1 | 1183.3
15:10:24:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  28.2 | 1236.2
15:10:25:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  44.1 | 1183.3
15:10:25:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  21.9 | 1259.6
15:10:25:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  44.1 | 1183.3
15:10:25:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  15.6 | 1282.9
15:10:26:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  34.6 | 1212.7
15:10:26:ST3_smx:INFO:	Configuring SMX FAST
15:10:27:ST3_smx:INFO:	chip: 23-0 	 47.250730 C 	 1177.390875 mV
15:10:27:ST3_smx:INFO:		Electrons
15:10:27:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:10:30:ST3_smx:INFO:	----> Checking Analog response
15:10:30:ST3_smx:INFO:	----> Checking broken channels
15:10:31:ST3_smx:INFO:	Total # broken ch: 0
15:10:31:ST3_smx:INFO:	List FAST: []
15:10:31:ST3_smx:INFO:	List SLOW: []
15:10:31:ST3_smx:INFO:		Holes
15:10:31:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:10:33:ST3_smx:INFO:	----> Checking Analog response
15:10:33:ST3_smx:INFO:	----> Checking broken channels
15:10:33:ST3_smx:INFO:	Total # broken ch: 0
15:10:33:ST3_smx:INFO:	List FAST: []
15:10:33:ST3_smx:INFO:	List SLOW: []
15:10:33:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
15:10:33:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  47.3 | 1171.5
15:10:33:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  44.1 | 1189.2
15:10:34:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  31.4 | 1236.2
15:10:34:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  44.1 | 1183.3
15:10:34:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  21.9 | 1253.7
15:10:34:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  44.1 | 1189.2
15:10:34:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  18.7 | 1282.9
15:10:35:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  34.6 | 1206.9
15:10:35:ST3_smx:INFO:	Configuring SMX FAST
15:10:37:ST3_smx:INFO:	chip: 30-1 	 50.430383 C 	 1177.390875 mV
15:10:37:ST3_smx:INFO:		Electrons
15:10:37:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:10:39:ST3_smx:INFO:	----> Checking Analog response
15:10:39:ST3_smx:INFO:	----> Checking broken channels
15:10:39:ST3_smx:INFO:	Total # broken ch: 0
15:10:39:ST3_smx:INFO:	List FAST: []
15:10:39:ST3_smx:INFO:	List SLOW: []
15:10:40:ST3_smx:INFO:		Holes
15:10:40:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:10:42:ST3_smx:INFO:	----> Checking Analog response
15:10:42:ST3_smx:INFO:	----> Checking broken channels
15:10:42:ST3_smx:INFO:	Total # broken ch: 0
15:10:42:ST3_smx:INFO:	List FAST: []
15:10:42:ST3_smx:INFO:	List SLOW: []
15:10:42:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
15:10:42:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  47.3 | 1171.5
15:10:42:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  50.4 | 1171.5
15:10:43:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  31.4 | 1236.2
15:10:43:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  47.3 | 1189.2
15:10:43:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  21.9 | 1253.7
15:10:43:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  44.1 | 1189.2
15:10:43:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  18.7 | 1282.9
15:10:44:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  37.7 | 1212.7
15:10:44:ST3_smx:INFO:	Configuring SMX FAST
15:10:46:ST3_smx:INFO:	chip: 21-2 	 40.898880 C 	 1206.851500 mV
15:10:46:ST3_smx:INFO:		Electrons
15:10:46:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:10:48:ST3_smx:INFO:	----> Checking Analog response
15:10:48:ST3_smx:INFO:	----> Checking broken channels
15:10:48:ST3_smx:INFO:	Total # broken ch: 0
15:10:48:ST3_smx:INFO:	List FAST: []
15:10:48:ST3_smx:INFO:	List SLOW: []
15:10:48:ST3_smx:INFO:		Holes
15:10:48:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:10:51:ST3_smx:INFO:	----> Checking Analog response
15:10:51:ST3_smx:INFO:	----> Checking broken channels
15:10:51:ST3_smx:INFO:	Total # broken ch: 0
15:10:51:ST3_smx:INFO:	List FAST: []
15:10:51:ST3_smx:INFO:	List SLOW: []
15:10:51:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
15:10:51:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  47.3 | 1177.4
15:10:51:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  50.4 | 1171.5
15:10:51:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  44.1 | 1201.0
15:10:52:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  47.3 | 1183.3
15:10:52:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  21.9 | 1259.6
15:10:52:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  47.3 | 1189.2
15:10:52:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  18.7 | 1288.7
15:10:52:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  37.7 | 1212.7
15:10:53:ST3_smx:INFO:	Configuring SMX FAST
15:10:55:ST3_smx:INFO:	chip: 28-3 	 50.430383 C 	 1171.483840 mV
15:10:55:ST3_smx:INFO:		Electrons
15:10:55:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:10:57:ST3_smx:INFO:	----> Checking Analog response
15:10:57:ST3_smx:INFO:	----> Checking broken channels
15:10:57:ST3_smx:INFO:	Total # broken ch: 0
15:10:57:ST3_smx:INFO:	List FAST: []
15:10:57:ST3_smx:INFO:	List SLOW: []
15:10:57:ST3_smx:INFO:		Holes
15:10:57:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:11:00:ST3_smx:INFO:	----> Checking Analog response
15:11:00:ST3_smx:INFO:	----> Checking broken channels
15:11:00:ST3_smx:INFO:	Total # broken ch: 0
15:11:00:ST3_smx:INFO:	List FAST: []
15:11:00:ST3_smx:INFO:	List SLOW: []
15:11:00:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
15:11:00:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  47.3 | 1171.5
15:11:00:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  50.4 | 1171.5
15:11:00:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  44.1 | 1201.0
15:11:01:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  53.6 | 1171.5
15:11:01:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  25.1 | 1259.6
15:11:01:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  47.3 | 1189.2
15:11:01:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  18.7 | 1288.7
15:11:02:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  37.7 | 1212.7
15:11:02:ST3_smx:INFO:	Configuring SMX FAST
15:11:04:ST3_smx:INFO:	chip: 19-4 	 25.062742 C 	 1259.567515 mV
15:11:04:ST3_smx:INFO:		Electrons
15:11:04:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:11:06:ST3_smx:INFO:	----> Checking Analog response
15:11:06:ST3_smx:INFO:	----> Checking broken channels
15:11:07:ST3_smx:INFO:	Total # broken ch: 0
15:11:07:ST3_smx:INFO:	List FAST: []
15:11:07:ST3_smx:INFO:	List SLOW: []
15:11:07:ST3_smx:INFO:		Holes
15:11:07:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:11:09:ST3_smx:INFO:	----> Checking Analog response
15:11:09:ST3_smx:INFO:	----> Checking broken channels
15:11:09:ST3_smx:INFO:	Total # broken ch: 0
15:11:09:ST3_smx:INFO:	List FAST: []
15:11:09:ST3_smx:INFO:	List SLOW: []
15:11:09:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
15:11:09:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  50.4 | 1177.4
15:11:09:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  50.4 | 1171.5
15:11:10:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  44.1 | 1206.9
15:11:10:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  50.4 | 1171.5
15:11:10:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  25.1 | 1253.7
15:11:10:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  47.3 | 1189.2
15:11:10:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  18.7 | 1288.7
15:11:11:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  37.7 | 1212.7
15:11:11:ST3_smx:INFO:	Configuring SMX FAST
15:11:13:ST3_smx:INFO:	chip: 26-5 	 44.073563 C 	 1195.082160 mV
15:11:13:ST3_smx:INFO:		Electrons
15:11:13:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:11:16:ST3_smx:INFO:	----> Checking Analog response
15:11:16:ST3_smx:INFO:	----> Checking broken channels
15:11:16:ST3_smx:INFO:	Total # broken ch: 0
15:11:16:ST3_smx:INFO:	List FAST: []
15:11:16:ST3_smx:INFO:	List SLOW: []
15:11:16:ST3_smx:INFO:		Holes
15:11:16:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:11:18:ST3_smx:INFO:	----> Checking Analog response
15:11:18:ST3_smx:INFO:	----> Checking broken channels
15:11:18:ST3_smx:INFO:	Total # broken ch: 0
15:11:18:ST3_smx:INFO:	List FAST: []
15:11:18:ST3_smx:INFO:	List SLOW: []
15:11:18:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
15:11:18:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  50.4 | 1177.4
15:11:19:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  50.4 | 1177.4
15:11:19:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  44.1 | 1206.9
15:11:19:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  50.4 | 1171.5
15:11:19:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  28.2 | 1253.7
15:11:19:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  47.3 | 1195.1
15:11:20:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  18.7 | 1288.7
15:11:20:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  37.7 | 1212.7
15:11:20:ST3_smx:INFO:	Configuring SMX FAST
15:11:23:ST3_smx:INFO:	chip: 17-6 	 31.389742 C 	 1253.730060 mV
15:11:23:ST3_smx:INFO:		Electrons
15:11:23:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:11:25:ST3_smx:INFO:	----> Checking Analog response
15:11:25:ST3_smx:INFO:	----> Checking broken channels
15:11:25:ST3_smx:INFO:	Total # broken ch: 0
15:11:25:ST3_smx:INFO:	List FAST: []
15:11:25:ST3_smx:INFO:	List SLOW: []
15:11:25:ST3_smx:INFO:		Holes
15:11:25:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:11:27:ST3_smx:INFO:	----> Checking Analog response
15:11:27:ST3_smx:INFO:	----> Checking broken channels
15:11:28:ST3_smx:INFO:	Total # broken ch: 0
15:11:28:ST3_smx:INFO:	List FAST: []
15:11:28:ST3_smx:INFO:	List SLOW: []
15:11:28:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
15:11:28:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  50.4 | 1177.4
15:11:28:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  53.6 | 1177.4
15:11:28:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  44.1 | 1206.9
15:11:28:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  53.6 | 1171.5
15:11:29:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  28.2 | 1253.7
15:11:29:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  47.3 | 1195.1
15:11:29:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  31.4 | 1253.7
15:11:29:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  37.7 | 1212.7
15:11:30:ST3_smx:INFO:	Configuring SMX FAST
15:11:32:ST3_smx:INFO:	chip: 24-7 	 47.250730 C 	 1189.190035 mV
15:11:32:ST3_smx:INFO:		Electrons
15:11:32:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:11:34:ST3_smx:INFO:	----> Checking Analog response
15:11:34:ST3_smx:INFO:	----> Checking broken channels
15:11:34:ST3_smx:INFO:	Total # broken ch: 0
15:11:34:ST3_smx:INFO:	List FAST: []
15:11:34:ST3_smx:INFO:	List SLOW: []
15:11:34:ST3_smx:INFO:		Holes
15:11:34:ST3_smx:INFO:			Injected pulses: 150LSB, amp_cal 8.400000 fC
15:11:36:ST3_smx:INFO:	----> Checking Analog response
15:11:36:ST3_smx:INFO:	----> Checking broken channels
15:11:37:ST3_smx:INFO:	Total # broken ch: 0
15:11:37:ST3_smx:INFO:	List FAST: []
15:11:37:ST3_smx:INFO:	List SLOW: []
15:11:37:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
15:11:37:febtest:INFO:	23-00 | XA-000-08-002-000-007-008-06 |  50.4 | 1177.4
15:11:37:febtest:INFO:	30-01 | XA-000-08-002-000-007-199-09 |  53.6 | 1177.4
15:11:37:febtest:INFO:	21-02 | XA-000-08-002-000-007-031-01 |  44.1 | 1206.9
15:11:38:febtest:INFO:	28-03 | XA-000-08-002-000-007-198-09 |  53.6 | 1171.5
15:11:38:febtest:INFO:	19-04 | XA-000-08-002-000-007-041-08 |  28.2 | 1259.6
15:11:38:febtest:INFO:	26-05 | XA-000-08-002-000-007-127-10 |  47.3 | 1195.1
15:11:38:febtest:INFO:	17-06 | XA-000-08-002-000-007-047-08 |  31.4 | 1253.7
15:11:38:febtest:INFO:	24-07 | XA-000-08-002-000-007-083-04 |  47.3 | 1183.3
############################################################
#                   S U M M A R Y                          #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '24_02_22-15_10_10', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'KIT', 'SITE': 'KIT', 'SETUP': 'KIT_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-007-083-04', 'FUSED_ID': 6359364699116565812, 'HW_ADDR': 7, 'UPLINK': 24, 'VERS_NO': '', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'FEB_SN': '2035', 'FEB_TYPE': 8.2, 'FEB_UPLINKS': 2, 'FEB_A': 0, 'FEB_B': 1, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.800', '1.4750', '2.200', '2.5560', '0.000', '0.0000', '7.000', '1.6580'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 150, 'PlsLoop': 500, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 24_02_22-15_10_10
OPERATOR  : Alois Alzheimer
SITE      : KIT
SETUP     : KIT_TEST_SETUP_1
Set-ID    : 
---------------------------------------
MODULE_NAME : 
FEB_SN : 2035
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 0
FEB_B : 1
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MODULE_NAME
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VI_before_Init : ['2.800', '1.4750', '2.200', '2.5560', '0.000', '0.0000', '7.000', '1.6580']
VI_after__Init : ['2.800', '1.9910', '2.200', '0.3193', '0.000', '0.0000', '7.000', '1.6640']
VI_at__the_End : ['2.800', '1.9920', '2.200', '0.3193', '0.000', '0.0000', '7.000', '1.6640']
Comment