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FEB_3000 10.10.23 14:23:55
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14:23:49:ST3_hmp4040:INFO: ROHDE&SCHWARZ,HMP4040,110099,HW50020003/SW2.71
14:23:49:febtest:INFO: FEB8.2 selected
14:23:50:smx_tester:INFO: Setting Elink clock mode to 160 MHz
14:23:55:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:23:55:ST3_Shared:INFO: -----------------------FEB-Microcable-----------------------
14:23:55:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:23:55:febtest:INFO: Tsting FEB with SN 6000
14:23:57:smx_tester:INFO: Scanning setup
14:23:57:elinks:INFO: Disabling clock on downlink 0
14:23:57:elinks:INFO: Disabling clock on downlink 1
14:23:57:elinks:INFO: Disabling clock on downlink 2
14:23:57:elinks:INFO: Disabling clock on downlink 3
14:23:57:elinks:INFO: Disabling clock on downlink 4
14:23:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:23:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:23:57:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 0
14:23:57:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 1
14:23:57:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 2
14:23:57:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 3
14:23:57:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 5
14:23:57:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 6
14:23:57:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 7
14:23:57:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:23:57:elinks:INFO: Disabling clock on downlink 0
14:23:57:elinks:INFO: Disabling clock on downlink 1
14:23:57:elinks:INFO: Disabling clock on downlink 2
14:23:57:elinks:INFO: Disabling clock on downlink 3
14:23:57:elinks:INFO: Disabling clock on downlink 4
14:23:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:23:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:23:57:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:23:57:elinks:INFO: Disabling clock on downlink 0
14:23:57:elinks:INFO: Disabling clock on downlink 1
14:23:57:elinks:INFO: Disabling clock on downlink 2
14:23:57:elinks:INFO: Disabling clock on downlink 3
14:23:57:elinks:INFO: Disabling clock on downlink 4
14:23:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:23:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:23:57:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:23:57:elinks:INFO: Disabling clock on downlink 0
14:23:57:elinks:INFO: Disabling clock on downlink 1
14:23:57:elinks:INFO: Disabling clock on downlink 2
14:23:57:elinks:INFO: Disabling clock on downlink 3
14:23:57:elinks:INFO: Disabling clock on downlink 4
14:23:57:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:23:57:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:23:58:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:23:58:elinks:INFO: Disabling clock on downlink 0
14:23:58:elinks:INFO: Disabling clock on downlink 1
14:23:58:elinks:INFO: Disabling clock on downlink 2
14:23:58:elinks:INFO: Disabling clock on downlink 3
14:23:58:elinks:INFO: Disabling clock on downlink 4
14:23:58:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:23:58:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:23:58:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:23:58:setup_element:INFO: Scanning clock phase
14:23:58:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:23:58:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
14:23:58:setup_element:INFO: Clock phase scan results for group 0, downlink 0
14:23:58:setup_element:INFO: Eye window for uplink 0 : ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
14:23:58:setup_element:INFO: Eye window for uplink 1 : ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
14:23:58:setup_element:INFO: Eye window for uplink 2 : ____________________________________________________________________XXXXXX______
Clock Delay: 30
14:23:58:setup_element:INFO: Eye window for uplink 3 : ___________________________________________________________________XXXXXX_______
Clock Delay: 29
14:23:58:setup_element:INFO: Eye window for uplink 5 : _____________________________________________________________________XXXXXX_____
Clock Delay: 31
14:23:58:setup_element:INFO: Eye window for uplink 6 : ___________________________________________________________________XXXXXX_______
Clock Delay: 29
14:23:58:setup_element:INFO: Eye window for uplink 7 : ____________________________________________________________________XXXXXX______
Clock Delay: 30
14:23:58:setup_element:INFO: Setting the clock phase to 30 for group 0, downlink 0
14:23:58:setup_element:INFO: Scanning data phases
14:23:58:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:23:58:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
14:24:03:setup_element:INFO: Data phase scan results for group 0, downlink 0
14:24:03:setup_element:INFO: Eye window for uplink 0 : __________________________XXXXXX________
Data delay found: 8
14:24:03:setup_element:INFO: Eye window for uplink 1 : _________________________XXXXX__________
Data delay found: 7
14:24:03:setup_element:INFO: Eye window for uplink 2 : ____________________________XXXXXX______
Data delay found: 10
14:24:03:setup_element:INFO: Eye window for uplink 3 : ___________________________XXXXX________
Data delay found: 9
14:24:03:setup_element:INFO: Eye window for uplink 5 : ___________________________________XXXX_
Data delay found: 16
14:24:03:setup_element:INFO: Eye window for uplink 6 : __________________________XXX___________
Data delay found: 7
14:24:03:setup_element:INFO: Eye window for uplink 7 : ________________________XXXXX___________
Data delay found: 6
14:24:03:setup_element:INFO: Setting the data phase to 8 for uplink 0
14:24:03:setup_element:INFO: Setting the data phase to 7 for uplink 1
14:24:03:setup_element:INFO: Setting the data phase to 10 for uplink 2
14:24:03:setup_element:INFO: Setting the data phase to 9 for uplink 3
14:24:03:setup_element:INFO: Setting the data phase to 16 for uplink 5
14:24:03:setup_element:INFO: Setting the data phase to 7 for uplink 6
14:24:03:setup_element:INFO: Setting the data phase to 6 for uplink 7
14:24:03:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 0
Uplinks: [0, 1, 2, 3, 5, 6, 7]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 30
Window Length: 72
Eye Windows:
Uplink 0: ____________________________________________________________________XXXXXXX_____
Uplink 1: ____________________________________________________________________XXXXXXX_____
Uplink 2: ____________________________________________________________________XXXXXX______
Uplink 3: ___________________________________________________________________XXXXXX_______
Uplink 5: _____________________________________________________________________XXXXXX_____
Uplink 6: ___________________________________________________________________XXXXXX_______
Uplink 7: ____________________________________________________________________XXXXXX______
Data phase characteristics:
Uplink 0:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 1:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 2:
Optimal Phase: 10
Window Length: 34
Eye Window: ____________________________XXXXXX______
Uplink 3:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 5:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 6:
Optimal Phase: 7
Window Length: 37
Eye Window: __________________________XXX___________
Uplink 7:
Optimal Phase: 6
Window Length: 35
Eye Window: ________________________XXXXX___________
]
14:24:03:setup_element:INFO: Beginning SMX ASICs map scan
14:24:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:24:03:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
14:24:03:master:INFO: Setting encoding mode EOS for groups [0], downlinks [0]
14:24:03:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [0]
14:24:03:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 5, 6, 7]
14:24:04:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 0
14:24:04:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 5
14:24:04:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 1
14:24:04:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 6
14:24:04:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 2
14:24:04:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
14:24:05:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 3
14:24:06:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 0
Uplinks: [0, 1, 2, 3, 5, 6, 7]
ASICs Map:
ASIC address 0x1: (ASIC uplink, uplink): (0, 0)
ASIC address 0x2: (ASIC uplink, uplink): (0, 5)
ASIC address 0x3: (ASIC uplink, uplink): (0, 1)
ASIC address 0x4: (ASIC uplink, uplink): (0, 6)
ASIC address 0x5: (ASIC uplink, uplink): (0, 2)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7)
ASIC address 0x7: (ASIC uplink, uplink): (0, 3)
Clock Phase Characteristic:
Optimal Phase: 30
Window Length: 72
Eye Windows:
Uplink 0: ____________________________________________________________________XXXXXXX_____
Uplink 1: ____________________________________________________________________XXXXXXX_____
Uplink 2: ____________________________________________________________________XXXXXX______
Uplink 3: ___________________________________________________________________XXXXXX_______
Uplink 5: _____________________________________________________________________XXXXXX_____
Uplink 6: ___________________________________________________________________XXXXXX_______
Uplink 7: ____________________________________________________________________XXXXXX______
Data phase characteristics:
Uplink 0:
Optimal Phase: 8
Window Length: 34
Eye Window: __________________________XXXXXX________
Uplink 1:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 2:
Optimal Phase: 10
Window Length: 34
Eye Window: ____________________________XXXXXX______
Uplink 3:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 5:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 6:
Optimal Phase: 7
Window Length: 37
Eye Window: __________________________XXX___________
Uplink 7:
Optimal Phase: 6
Window Length: 35
Eye Window: ________________________XXXXX___________
14:24:06:setup_element:INFO: Performing Elink synchronization
14:24:06:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:24:06:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
14:24:06:master:INFO: Setting encoding mode EOS for groups [0], downlinks [0]
14:24:06:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [0]
14:24:06:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 0
14:24:06:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 5, 6, 7]
14:24:06:ST3_emu:INFO: Number of chips: 7
14:24:06:ST3_emu:INFO: Chip address: 0x1
14:24:06:ST3_emu:INFO: Chip address: 0x2
14:24:06:ST3_emu:INFO: Chip address: 0x3
14:24:06:ST3_emu:INFO: Chip address: 0x4
14:24:06:ST3_emu:INFO: Chip address: 0x5
14:24:06:ST3_emu:INFO: Chip address: 0x6
14:24:06:ST3_emu:INFO: Chip address: 0x7
14:24:07:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:24:07:febtest:INFO: 0-1 | XA-000-08-003-000-001-163-13 | 56.8 | 1171.5
14:24:08:febtest:INFO: 0-2 | XA-000-08-003-000-001-134-03 | 60.0 | 1165.6
14:24:08:febtest:INFO: 0-3 | XA-000-08-003-000-001-167-13 | 72.8 | 1118.1
14:24:08:febtest:INFO: 0-4 | XA-000-08-003-000-001-142-03 | 63.2 | 1153.7
14:24:08:febtest:INFO: 0-5 | XA-000-08-003-000-001-157-04 | 79.2 | 1100.2
14:24:09:febtest:INFO: 0-6 | XA-000-08-003-000-001-131-03 | 72.8 | 1124.0
14:24:09:febtest:INFO: 0-7 | XA-000-08-003-000-001-128-03 | 50.4 | 1212.7
14:24:09:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:24:12:ST3_smx:INFO: chip: 0-1 66.365920 C 1124.048640 mV
14:24:12:ST3_smx:INFO: # loops 0
14:24:14:ST3_smx:INFO: # loops 1
14:24:15:ST3_smx:INFO: # loops 2
14:24:17:ST3_smx:INFO: # loops 3
14:24:18:ST3_smx:INFO: # loops 4
14:24:20:ST3_smx:INFO: Total # of broken channels: 0
14:24:20:ST3_smx:INFO: List of broken channels: []
14:24:20:ST3_smx:INFO: Total # of broken channels: 0
14:24:20:ST3_smx:INFO: List of broken channels: []
14:24:21:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:24:25:ST3_smx:INFO: chip: 0-2 69.560482 C 1124.048640 mV
14:24:25:ST3_smx:INFO: # loops 0
14:24:26:ST3_smx:INFO: # loops 1
14:24:28:ST3_smx:INFO: # loops 2
14:24:30:ST3_smx:INFO: # loops 3
14:24:31:ST3_smx:INFO: # loops 4
14:24:33:ST3_smx:INFO: Total # of broken channels: 0
14:24:33:ST3_smx:INFO: List of broken channels: []
14:24:33:ST3_smx:INFO: Total # of broken channels: 0
14:24:33:ST3_smx:INFO: List of broken channels: []
14:24:34:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:24:37:ST3_smx:INFO: chip: 0-3 79.159080 C 1106.178435 mV
14:24:37:ST3_smx:INFO: # loops 0
14:24:39:ST3_smx:INFO: # loops 1
14:24:41:ST3_smx:INFO: # loops 2
14:24:42:ST3_smx:INFO: # loops 3
14:24:44:ST3_smx:INFO: # loops 4
14:24:45:ST3_smx:INFO: Total # of broken channels: 0
14:24:45:ST3_smx:INFO: List of broken channels: []
14:24:45:ST3_smx:INFO: Total # of broken channels: 0
14:24:45:ST3_smx:INFO: List of broken channels: []
14:24:46:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:24:50:ST3_smx:INFO: chip: 0-4 69.560482 C 1153.732915 mV
14:24:50:ST3_smx:INFO: # loops 0
14:24:51:ST3_smx:INFO: # loops 1
14:24:53:ST3_smx:INFO: # loops 2
14:24:55:ST3_smx:INFO: # loops 3
14:24:56:ST3_smx:INFO: # loops 4
14:24:58:ST3_smx:INFO: Total # of broken channels: 0
14:24:58:ST3_smx:INFO: List of broken channels: []
14:24:58:ST3_smx:INFO: Total # of broken channels: 0
14:24:58:ST3_smx:INFO: List of broken channels: []
14:24:59:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:25:02:ST3_smx:INFO: chip: 0-5 82.363583 C 1100.211760 mV
14:25:02:ST3_smx:INFO: # loops 0
14:25:04:ST3_smx:INFO: # loops 1
14:25:06:ST3_smx:INFO: # loops 2
14:25:07:ST3_smx:INFO: # loops 3
14:25:09:ST3_smx:INFO: # loops 4
14:25:11:ST3_smx:INFO: Total # of broken channels: 1
14:25:11:ST3_smx:INFO: List of broken channels: [1]
14:25:11:ST3_smx:INFO: Total # of broken channels: 1
14:25:11:ST3_smx:INFO: List of broken channels: [1]
14:25:12:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:25:15:ST3_smx:INFO: chip: 0-6 85.570570 C 1100.211760 mV
14:25:15:ST3_smx:INFO: # loops 0
14:25:17:ST3_smx:INFO: # loops 1
14:25:18:ST3_smx:INFO: # loops 2
14:25:20:ST3_smx:INFO: # loops 3
14:25:21:ST3_smx:INFO: # loops 4
14:25:23:ST3_smx:INFO: Total # of broken channels: 0
14:25:23:ST3_smx:INFO: List of broken channels: []
14:25:23:ST3_smx:INFO: Total # of broken channels: 0
14:25:23:ST3_smx:INFO: List of broken channels: []
14:25:24:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
14:25:28:ST3_smx:INFO: chip: 0-7 72.757530 C 1159.654860 mV
14:25:28:ST3_smx:INFO: # loops 0
14:25:29:ST3_smx:INFO: # loops 1
14:25:31:ST3_smx:INFO: # loops 2
14:25:32:ST3_smx:INFO: # loops 3
14:25:34:ST3_smx:INFO: # loops 4
14:25:36:ST3_smx:INFO: Total # of broken channels: 16
14:25:36:ST3_smx:INFO: List of broken channels: [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 54]
14:25:36:ST3_smx:INFO: Total # of broken channels: 30
14:25:36:ST3_smx:INFO: List of broken channels: [0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30, 32, 34, 36, 38, 40, 42, 44, 46, 48, 50, 54, 58, 60, 70]
14:25:36:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
14:25:37:febtest:INFO: 0-1 | XA-000-08-003-000-001-163-13 | 82.4 | 1106.2
14:25:37:febtest:INFO: 0-2 | XA-000-08-003-000-001-134-03 | 82.4 | 1112.1
14:25:37:febtest:INFO: 0-3 | XA-000-08-003-000-001-167-13 | 88.8 | 1094.2
14:25:37:febtest:INFO: 0-4 | XA-000-08-003-000-001-142-03 | 79.2 | 1147.8
14:25:37:febtest:INFO: 0-5 | XA-000-08-003-000-001-157-04 | 88.8 | 1100.2
14:25:38:febtest:INFO: 0-6 | XA-000-08-003-000-001-131-03 | 92.0 | 1100.2
14:25:38:febtest:INFO: 0-7 | XA-000-08-003-000-001-128-03 | 76.0 | 1153.7
14:26:45:febtest:INFO: FEB 8-2 A @ KIT
14:27:00:ST3_Shared:INFO: /home/cbm/public_html/Test_LogDir//FEB/FEB_3000/TestDate_2023_10_10-14_23_55/