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FEB_3000 10.10.23 17:35:16
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17:34:45:ST3_hmp4040:INFO: ROHDE&SCHWARZ,HMP4040,110099,HW50020003/SW2.71
17:34:46:febtest:INFO: FEB8.2 selected
17:34:46:smx_tester:INFO: Setting Elink clock mode to 160 MHz
17:35:02:smx_tester:INFO: Setting Elink clock mode to 160 MHz
17:35:02:ST3_emu:ERROR: device described in file: ../ST3_BASE/config/feb8_2_devices.xml not found!!!
17:35:05:smx_tester:INFO: Setting Elink clock mode to 160 MHz
17:35:16:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
17:35:16:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
17:35:16:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
17:35:17:febtest:INFO: Tsting FEB with SN 3000
17:35:18:smx_tester:INFO: Scanning setup
17:35:18:elinks:INFO: Disabling clock on downlink 0
17:35:18:elinks:INFO: Disabling clock on downlink 1
17:35:18:elinks:INFO: Disabling clock on downlink 2
17:35:18:elinks:INFO: Disabling clock on downlink 3
17:35:18:elinks:INFO: Disabling clock on downlink 4
17:35:18:setup_element:INFO: Checking SOS, encoding_mode: SOS
17:35:18:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
17:35:19:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 0
17:35:19:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 1
17:35:19:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 2
17:35:19:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 3
17:35:19:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 5
17:35:19:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 6
17:35:19:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 7
17:35:19:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
17:35:19:elinks:INFO: Disabling clock on downlink 0
17:35:19:elinks:INFO: Disabling clock on downlink 1
17:35:19:elinks:INFO: Disabling clock on downlink 2
17:35:19:elinks:INFO: Disabling clock on downlink 3
17:35:19:elinks:INFO: Disabling clock on downlink 4
17:35:19:setup_element:INFO: Checking SOS, encoding_mode: SOS
17:35:19:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
17:35:19:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
17:35:19:elinks:INFO: Disabling clock on downlink 0
17:35:19:elinks:INFO: Disabling clock on downlink 1
17:35:19:elinks:INFO: Disabling clock on downlink 2
17:35:19:elinks:INFO: Disabling clock on downlink 3
17:35:19:elinks:INFO: Disabling clock on downlink 4
17:35:19:setup_element:INFO: Checking SOS, encoding_mode: SOS
17:35:19:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
17:35:19:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
17:35:19:elinks:INFO: Disabling clock on downlink 0
17:35:19:elinks:INFO: Disabling clock on downlink 1
17:35:19:elinks:INFO: Disabling clock on downlink 2
17:35:19:elinks:INFO: Disabling clock on downlink 3
17:35:19:elinks:INFO: Disabling clock on downlink 4
17:35:19:setup_element:INFO: Checking SOS, encoding_mode: SOS
17:35:19:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
17:35:19:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
17:35:19:elinks:INFO: Disabling clock on downlink 0
17:35:19:elinks:INFO: Disabling clock on downlink 1
17:35:19:elinks:INFO: Disabling clock on downlink 2
17:35:19:elinks:INFO: Disabling clock on downlink 3
17:35:19:elinks:INFO: Disabling clock on downlink 4
17:35:19:setup_element:INFO: Checking SOS, encoding_mode: SOS
17:35:19:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
17:35:19:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
17:35:19:setup_element:INFO: Scanning clock phase
17:35:19:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
17:35:19:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
17:35:19:setup_element:INFO: Clock phase scan results for group 0, downlink 0
17:35:19:setup_element:INFO: Eye window for uplink 0 : ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
17:35:19:setup_element:INFO: Eye window for uplink 1 : ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
17:35:19:setup_element:INFO: Eye window for uplink 2 : ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
17:35:19:setup_element:INFO: Eye window for uplink 3 : ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
17:35:19:setup_element:INFO: Eye window for uplink 5 : _____________________________________________________________________XXXXXX_____
Clock Delay: 31
17:35:19:setup_element:INFO: Eye window for uplink 6 : ____________________________________________________________________XXXXXX______
Clock Delay: 30
17:35:19:setup_element:INFO: Eye window for uplink 7 : ____________________________________________________________________XXXXXXX_____
Clock Delay: 31
17:35:19:setup_element:INFO: Setting the clock phase to 31 for group 0, downlink 0
17:35:19:setup_element:INFO: Scanning data phases
17:35:19:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
17:35:20:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
17:35:25:setup_element:INFO: Data phase scan results for group 0, downlink 0
17:35:25:setup_element:INFO: Eye window for uplink 0 : ____________________________XXXX________
Data delay found: 9
17:35:25:setup_element:INFO: Eye window for uplink 1 : _________________________XXXXX__________
Data delay found: 7
17:35:25:setup_element:INFO: Eye window for uplink 2 : ____________________________XXXXXX______
Data delay found: 10
17:35:25:setup_element:INFO: Eye window for uplink 3 : ___________________________XXXXX________
Data delay found: 9
17:35:25:setup_element:INFO: Eye window for uplink 5 : ___________________________________XXXX_
Data delay found: 16
17:35:25:setup_element:INFO: Eye window for uplink 6 : ___________XXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 5
17:35:25:setup_element:INFO: Eye window for uplink 7 : ________________________XXXXX___________
Data delay found: 6
17:35:25:setup_element:INFO: Setting the data phase to 9 for uplink 0
17:35:25:setup_element:INFO: Setting the data phase to 7 for uplink 1
17:35:25:setup_element:INFO: Setting the data phase to 10 for uplink 2
17:35:25:setup_element:INFO: Setting the data phase to 9 for uplink 3
17:35:25:setup_element:INFO: Setting the data phase to 16 for uplink 5
17:35:25:setup_element:INFO: Setting the data phase to 5 for uplink 6
17:35:25:setup_element:INFO: Setting the data phase to 6 for uplink 7
17:35:25:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 0
Uplinks: [0, 1, 2, 3, 5, 6, 7]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 31
Window Length: 73
Eye Windows:
Uplink 0: ____________________________________________________________________XXXXXXX_____
Uplink 1: ____________________________________________________________________XXXXXXX_____
Uplink 2: ____________________________________________________________________XXXXXXX_____
Uplink 3: ____________________________________________________________________XXXXXXX_____
Uplink 5: _____________________________________________________________________XXXXXX_____
Uplink 6: ____________________________________________________________________XXXXXX______
Uplink 7: ____________________________________________________________________XXXXXXX_____
Data phase characteristics:
Uplink 0:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
Uplink 1:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 2:
Optimal Phase: 10
Window Length: 34
Eye Window: ____________________________XXXXXX______
Uplink 3:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 5:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 6:
Optimal Phase: 5
Window Length: 11
Eye Window: ___________XXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 7:
Optimal Phase: 6
Window Length: 35
Eye Window: ________________________XXXXX___________
]
17:35:25:setup_element:INFO: Beginning SMX ASICs map scan
17:35:25:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
17:35:25:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
17:35:25:master:INFO: Setting encoding mode EOS for groups [0], downlinks [0]
17:35:25:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [0]
17:35:25:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 5, 6, 7]
17:35:25:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 0
17:35:25:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 5
17:35:25:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 1
17:35:25:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 6
17:35:26:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 2
17:35:26:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
17:35:26:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 3
17:35:27:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 0
Uplinks: [0, 1, 2, 3, 5, 6, 7]
ASICs Map:
ASIC address 0x1: (ASIC uplink, uplink): (0, 0)
ASIC address 0x2: (ASIC uplink, uplink): (0, 5)
ASIC address 0x3: (ASIC uplink, uplink): (0, 1)
ASIC address 0x4: (ASIC uplink, uplink): (0, 6)
ASIC address 0x5: (ASIC uplink, uplink): (0, 2)
ASIC address 0x6: (ASIC uplink, uplink): (0, 7)
ASIC address 0x7: (ASIC uplink, uplink): (0, 3)
Clock Phase Characteristic:
Optimal Phase: 31
Window Length: 73
Eye Windows:
Uplink 0: ____________________________________________________________________XXXXXXX_____
Uplink 1: ____________________________________________________________________XXXXXXX_____
Uplink 2: ____________________________________________________________________XXXXXXX_____
Uplink 3: ____________________________________________________________________XXXXXXX_____
Uplink 5: _____________________________________________________________________XXXXXX_____
Uplink 6: ____________________________________________________________________XXXXXX______
Uplink 7: ____________________________________________________________________XXXXXXX_____
Data phase characteristics:
Uplink 0:
Optimal Phase: 9
Window Length: 36
Eye Window: ____________________________XXXX________
Uplink 1:
Optimal Phase: 7
Window Length: 35
Eye Window: _________________________XXXXX__________
Uplink 2:
Optimal Phase: 10
Window Length: 34
Eye Window: ____________________________XXXXXX______
Uplink 3:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 5:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 6:
Optimal Phase: 5
Window Length: 11
Eye Window: ___________XXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 7:
Optimal Phase: 6
Window Length: 35
Eye Window: ________________________XXXXX___________
17:35:27:setup_element:INFO: Performing Elink synchronization
17:35:27:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
17:35:27:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
17:35:27:master:INFO: Setting encoding mode EOS for groups [0], downlinks [0]
17:35:27:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [0]
17:35:27:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 0
17:35:27:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 5, 6, 7]
17:35:27:ST3_emu:INFO: Number of chips: 7
17:35:27:ST3_emu:INFO: Chip address: 0x1
17:35:27:ST3_emu:INFO: Chip address: 0x2
17:35:27:ST3_emu:INFO: Chip address: 0x3
17:35:28:ST3_emu:INFO: Chip address: 0x4
17:35:28:ST3_emu:INFO: Chip address: 0x5
17:35:28:ST3_emu:INFO: Chip address: 0x6
17:35:28:ST3_emu:INFO: Chip address: 0x7
17:35:29:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
17:35:29:febtest:INFO: 0-1 | XA-000-08-003-000-001-163-13 | 47.3 | 1159.7
17:35:29:febtest:INFO: 0-2 | XA-000-08-003-000-001-134-03 | 50.4 | 1153.7
17:35:29:febtest:INFO: 0-3 | XA-000-08-003-000-001-167-13 | 63.2 | 1118.1
17:35:30:febtest:INFO: 0-4 | XA-000-08-003-000-001-142-03 | 50.4 | 1159.7
17:35:30:febtest:INFO: 0-5 | XA-000-08-003-000-001-157-04 | 69.6 | 1100.2
17:35:30:febtest:INFO: 0-6 | XA-000-08-003-000-001-131-03 | 60.0 | 1130.0
17:35:30:febtest:INFO: 0-7 | XA-000-08-003-000-001-128-03 | 37.7 | 1212.7
17:35:30:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
17:35:34:ST3_smx:INFO: chip: 0-1 56.797143 C 1118.096875 mV
17:35:34:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
17:35:34:ST3_smx:INFO: Electrons
17:35:34:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
17:35:36:ST3_smx:INFO: ----> Checking Analog response
17:35:36:ST3_smx:INFO: ----> Checking broken channels
17:35:37:ST3_smx:INFO: Total # broken ch: 1
17:35:37:ST3_smx:INFO: List FAST: [119]
17:35:37:ST3_smx:INFO: List SLOW: []
17:35:37:ST3_smx:INFO: Holes
17:35:37:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
17:35:39:ST3_smx:INFO: ----> Checking Analog response
17:35:39:ST3_smx:INFO: ----> Checking broken channels
17:35:39:ST3_smx:INFO: Total # broken ch: 1
17:35:39:ST3_smx:INFO: List FAST: [119]
17:35:39:ST3_smx:INFO: List SLOW: []
17:35:39:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
17:35:39:febtest:INFO: 0-1 | XA-000-08-003-000-001-163-13 | 60.0 | 1118.1
17:35:39:febtest:INFO: 0-2 | XA-000-08-003-000-001-134-03 | 50.4 | 1153.7
17:35:40:febtest:INFO: 0-3 | XA-000-08-003-000-001-167-13 | 63.2 | 1118.1
17:35:40:febtest:INFO: 0-4 | XA-000-08-003-000-001-142-03 | 53.6 | 1159.7
17:35:40:febtest:INFO: 0-5 | XA-000-08-003-000-001-157-04 | 69.6 | 1100.2
17:35:40:febtest:INFO: 0-6 | XA-000-08-003-000-001-131-03 | 63.2 | 1130.0
17:35:40:febtest:INFO: 0-7 | XA-000-08-003-000-001-128-03 | 40.9 | 1206.9
17:35:41:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
17:35:45:ST3_smx:INFO: chip: 0-2 56.797143 C 1124.048640 mV
17:35:45:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
17:35:45:ST3_smx:INFO: Electrons
17:35:45:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
17:35:47:ST3_smx:INFO: ----> Checking Analog response
17:35:47:ST3_smx:INFO: ----> Checking broken channels
17:35:47:ST3_smx:INFO: Total # broken ch: 2
17:35:47:ST3_smx:INFO: List FAST: [43, 102]
17:35:47:ST3_smx:INFO: List SLOW: []
17:35:47:ST3_smx:INFO: Holes
17:35:47:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
17:35:49:ST3_smx:INFO: ----> Checking Analog response
17:35:49:ST3_smx:INFO: ----> Checking broken channels
17:35:50:ST3_smx:INFO: Total # broken ch: 2
17:35:50:ST3_smx:INFO: List FAST: [43, 102]
17:35:50:ST3_smx:INFO: List SLOW: []
17:35:50:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
17:35:50:febtest:INFO: 0-1 | XA-000-08-003-000-001-163-13 | 60.0 | 1118.1
17:35:50:febtest:INFO: 0-2 | XA-000-08-003-000-001-134-03 | 60.0 | 1118.1
17:35:50:febtest:INFO: 0-3 | XA-000-08-003-000-001-167-13 | 66.4 | 1118.1
17:35:50:febtest:INFO: 0-4 | XA-000-08-003-000-001-142-03 | 56.8 | 1153.7
17:35:51:febtest:INFO: 0-5 | XA-000-08-003-000-001-157-04 | 72.8 | 1094.2
17:35:51:febtest:INFO: 0-6 | XA-000-08-003-000-001-131-03 | 66.4 | 1124.0
17:35:51:febtest:INFO: 0-7 | XA-000-08-003-000-001-128-03 | 40.9 | 1212.7
17:35:52:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
17:35:55:ST3_smx:INFO: chip: 0-3 66.365920 C 1106.178435 mV
17:35:55:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
17:35:55:ST3_smx:INFO: Electrons
17:35:55:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
17:35:57:ST3_smx:INFO: ----> Checking Analog response
17:35:57:ST3_smx:INFO: ----> Checking broken channels
17:35:58:ST3_smx:INFO: Total # broken ch: 2
17:35:58:ST3_smx:INFO: List FAST: [23, 75]
17:35:58:ST3_smx:INFO: List SLOW: []
17:35:58:ST3_smx:INFO: Holes
17:35:58:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
17:36:00:ST3_smx:INFO: ----> Checking Analog response
17:36:00:ST3_smx:INFO: ----> Checking broken channels
17:36:00:ST3_smx:INFO: Total # broken ch: 2
17:36:00:ST3_smx:INFO: List FAST: [23, 75]
17:36:00:ST3_smx:INFO: List SLOW: []
17:36:00:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
17:36:00:febtest:INFO: 0-1 | XA-000-08-003-000-001-163-13 | 63.2 | 1118.1
17:36:00:febtest:INFO: 0-2 | XA-000-08-003-000-001-134-03 | 63.2 | 1118.1
17:36:01:febtest:INFO: 0-3 | XA-000-08-003-000-001-167-13 | 69.6 | 1100.2
17:36:01:febtest:INFO: 0-4 | XA-000-08-003-000-001-142-03 | 60.0 | 1153.7
17:36:01:febtest:INFO: 0-5 | XA-000-08-003-000-001-157-04 | 72.8 | 1094.2
17:36:01:febtest:INFO: 0-6 | XA-000-08-003-000-001-131-03 | 66.4 | 1124.0
17:36:02:febtest:INFO: 0-7 | XA-000-08-003-000-001-128-03 | 44.1 | 1206.9
17:36:02:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
17:36:06:ST3_smx:INFO: chip: 0-4 56.797143 C 1153.732915 mV
17:36:06:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
17:36:06:ST3_smx:INFO: Electrons
17:36:06:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
17:36:08:ST3_smx:INFO: ----> Checking Analog response
17:36:08:ST3_smx:INFO: ----> Checking broken channels
17:36:08:ST3_smx:INFO: Total # broken ch: 1
17:36:08:ST3_smx:INFO: List FAST: [34]
17:36:08:ST3_smx:INFO: List SLOW: []
17:36:08:ST3_smx:INFO: Holes
17:36:08:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
17:36:10:ST3_smx:INFO: ----> Checking Analog response
17:36:10:ST3_smx:INFO: ----> Checking broken channels
17:36:11:ST3_smx:INFO: Total # broken ch: 1
17:36:11:ST3_smx:INFO: List FAST: [34]
17:36:11:ST3_smx:INFO: List SLOW: []
17:36:11:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
17:36:11:febtest:INFO: 0-1 | XA-000-08-003-000-001-163-13 | 66.4 | 1118.1
17:36:11:febtest:INFO: 0-2 | XA-000-08-003-000-001-134-03 | 66.4 | 1118.1
17:36:11:febtest:INFO: 0-3 | XA-000-08-003-000-001-167-13 | 72.8 | 1100.2
17:36:11:febtest:INFO: 0-4 | XA-000-08-003-000-001-142-03 | 60.0 | 1153.7
17:36:12:febtest:INFO: 0-5 | XA-000-08-003-000-001-157-04 | 76.0 | 1094.2
17:36:12:febtest:INFO: 0-6 | XA-000-08-003-000-001-131-03 | 69.6 | 1124.0
17:36:12:febtest:INFO: 0-7 | XA-000-08-003-000-001-128-03 | 47.3 | 1206.9
17:36:13:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
17:36:16:ST3_smx:INFO: chip: 0-5 69.560482 C 1100.211760 mV
17:36:16:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
17:36:16:ST3_smx:INFO: Electrons
17:36:16:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
17:36:18:ST3_smx:INFO: ----> Checking Analog response
17:36:18:ST3_smx:INFO: ----> Checking broken channels
17:36:19:ST3_smx:INFO: Total # broken ch: 4
17:36:19:ST3_smx:INFO: List FAST: [5, 42, 81, 85]
17:36:19:ST3_smx:INFO: List SLOW: []
17:36:19:ST3_smx:INFO: Holes
17:36:19:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
17:36:21:ST3_smx:INFO: ----> Checking Analog response
17:36:21:ST3_smx:INFO: ----> Checking broken channels
17:36:21:ST3_smx:INFO: Total # broken ch: 4
17:36:21:ST3_smx:INFO: List FAST: [5, 42, 81, 85]
17:36:21:ST3_smx:INFO: List SLOW: []
17:36:21:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
17:36:21:febtest:INFO: 0-1 | XA-000-08-003-000-001-163-13 | 66.4 | 1112.1
17:36:21:febtest:INFO: 0-2 | XA-000-08-003-000-001-134-03 | 66.4 | 1118.1
17:36:22:febtest:INFO: 0-3 | XA-000-08-003-000-001-167-13 | 72.8 | 1100.2
17:36:22:febtest:INFO: 0-4 | XA-000-08-003-000-001-142-03 | 60.0 | 1153.7
17:36:22:febtest:INFO: 0-5 | XA-000-08-003-000-001-157-04 | 72.8 | 1100.2
17:36:22:febtest:INFO: 0-6 | XA-000-08-003-000-001-131-03 | 72.8 | 1124.0
17:36:23:febtest:INFO: 0-7 | XA-000-08-003-000-001-128-03 | 47.3 | 1206.9
17:36:23:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
17:36:27:ST3_smx:INFO: chip: 0-6 75.957063 C 1106.178435 mV
17:36:27:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
17:36:27:ST3_smx:INFO: Electrons
17:36:27:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
17:36:29:ST3_smx:INFO: ----> Checking Analog response
17:36:29:ST3_smx:INFO: ----> Checking broken channels
17:36:29:ST3_smx:INFO: Total # broken ch: 1
17:36:29:ST3_smx:INFO: List FAST: [80]
17:36:29:ST3_smx:INFO: List SLOW: []
17:36:29:ST3_smx:INFO: Holes
17:36:29:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
17:36:31:ST3_smx:INFO: ----> Checking Analog response
17:36:31:ST3_smx:INFO: ----> Checking broken channels
17:36:31:ST3_smx:INFO: Total # broken ch: 1
17:36:31:ST3_smx:INFO: List FAST: [80]
17:36:31:ST3_smx:INFO: List SLOW: []
17:36:31:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
17:36:32:febtest:INFO: 0-1 | XA-000-08-003-000-001-163-13 | 69.6 | 1112.1
17:36:32:febtest:INFO: 0-2 | XA-000-08-003-000-001-134-03 | 69.6 | 1112.1
17:36:32:febtest:INFO: 0-3 | XA-000-08-003-000-001-167-13 | 76.0 | 1094.2
17:36:32:febtest:INFO: 0-4 | XA-000-08-003-000-001-142-03 | 63.2 | 1147.8
17:36:33:febtest:INFO: 0-5 | XA-000-08-003-000-001-157-04 | 76.0 | 1100.2
17:36:33:febtest:INFO: 0-6 | XA-000-08-003-000-001-131-03 | 76.0 | 1100.2
17:36:33:febtest:INFO: 0-7 | XA-000-08-003-000-001-128-03 | 50.4 | 1201.0
17:36:34:ST3_smx:INFO: PROCESS 1: Configuring AFE with typical values
17:36:37:ST3_smx:INFO: chip: 0-7 59.984250 C 1159.654860 mV
17:36:37:ST3_smx:INFO: PROCESS 2: Checking channel response with internal pulse
17:36:37:ST3_smx:INFO: Electrons
17:36:37:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
17:36:39:ST3_smx:INFO: ----> Checking Analog response
17:36:39:ST3_smx:INFO: ----> Checking broken channels
17:36:40:ST3_smx:INFO: Total # broken ch: 6
17:36:40:ST3_smx:INFO: List FAST: [37, 45, 54, 63, 127]
17:36:40:ST3_smx:INFO: List SLOW: [54]
17:36:40:ST3_smx:INFO: Holes
17:36:40:ST3_smx:INFO: Injected pulses: 110LSB, amp_cal 6.160000 fC
17:36:42:ST3_smx:INFO: ----> Checking Analog response
17:36:42:ST3_smx:INFO: ----> Checking broken channels
17:36:42:ST3_smx:INFO: Total # broken ch: 6
17:36:42:ST3_smx:INFO: List FAST: [37, 45, 54, 63, 127]
17:36:42:ST3_smx:INFO: List SLOW: [54]
17:36:42:febtest:INFO: Add. | ASIC-ID | T [C] | Vddm [mV]
17:36:42:febtest:INFO: 0-1 | XA-000-08-003-000-001-163-13 | 69.6 | 1112.1
17:36:42:febtest:INFO: 0-2 | XA-000-08-003-000-001-134-03 | 69.6 | 1112.1
17:36:42:febtest:INFO: 0-3 | XA-000-08-003-000-001-167-13 | 79.2 | 1094.2
17:36:43:febtest:INFO: 0-4 | XA-000-08-003-000-001-142-03 | 66.4 | 1147.8
17:36:43:febtest:INFO: 0-5 | XA-000-08-003-000-001-157-04 | 79.2 | 1100.2
17:36:43:febtest:INFO: 0-6 | XA-000-08-003-000-001-131-03 | 79.2 | 1100.2
17:36:43:febtest:INFO: 0-7 | XA-000-08-003-000-001-128-03 | 63.2 | 1159.7
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '2023_10_10-17_35_16', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'Test', 'SITE': 'GSI', 'SETUP': 'GSI_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-003-000-001-128-03', 'FUSED_ID': 6359364699384977411, 'HW_ADDR': 7, 'VERS_NO': '2.2', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 6, 'N_BROKEN_FAST': '[37, 45, 54, 63, 127]', 'N_BROKEN_SLOW': '[54]', 'P_BROKEN_DISC': 6, 'P_BROKEN_FAST': '[37, 45, 54, 63, 127]', 'P_BROKEN_SLOW': '[54]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'VI_bInit': ['2.800', '1.6190', '2.200', '1.9260', '0.000', '0.0000', '7.000', '0.7803'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 110, 'PlsLoop': 3, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': '54 FAST ', 'N_ANA_FAIL_CH': '1', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': '54 FAST ', 'P_ANA_FAIL_CH': '1'}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 15, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 110, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 15, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
17:36:47:ST3_Shared:INFO: /home/cbm/public_html/Test_LogDir//FEB/FEB_3000/TestDate_2023_10_10-17_35_16/