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FEB_3000 22.02.24 14:56:27
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14:52:28:ST3_hmp4040:INFO: ROHDE&SCHWARZ,HMP4040,110099,HW50020003/SW2.72
14:52:28:febtest:INFO: FEB 8-2 selected
14:52:28:smx_tester:INFO: Setting Elink clock mode to 160 MHz
14:52:28:febtest:INFO: FEB type: 8.2
14:52:28:febtest:INFO: FEB SN: 2035
14:52:28:febtest:INFO: FEB A: 0
14:52:28:febtest:INFO: FEB B: 1
14:52:29:febtest:INFO: FEB 8-2 selected
14:52:29:smx_tester:INFO: Setting Elink clock mode to 160 MHz
14:52:33:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:52:33:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
14:52:33:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:52:34:febtest:INFO: Testing FEB with SN 2035
14:52:36:smx_tester:INFO: Scanning setup
14:52:36:elinks:INFO: Disabling clock on downlink 0
14:52:36:elinks:INFO: Disabling clock on downlink 1
14:52:36:elinks:INFO: Disabling clock on downlink 2
14:52:36:elinks:INFO: Disabling clock on downlink 3
14:52:36:elinks:INFO: Disabling clock on downlink 4
14:52:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:52:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:52:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:52:37:elinks:INFO: Disabling clock on downlink 0
14:52:37:elinks:INFO: Disabling clock on downlink 1
14:52:37:elinks:INFO: Disabling clock on downlink 2
14:52:37:elinks:INFO: Disabling clock on downlink 3
14:52:37:elinks:INFO: Disabling clock on downlink 4
14:52:37:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:52:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:52:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:52:37:elinks:INFO: Disabling clock on downlink 0
14:52:37:elinks:INFO: Disabling clock on downlink 1
14:52:37:elinks:INFO: Disabling clock on downlink 2
14:52:37:elinks:INFO: Disabling clock on downlink 3
14:52:37:elinks:INFO: Disabling clock on downlink 4
14:52:37:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:52:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:52:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
14:52:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
14:52:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
14:52:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
14:52:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
14:52:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
14:52:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
14:52:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
14:52:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
14:52:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
14:52:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
14:52:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
14:52:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
14:52:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
14:52:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
14:52:37:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
14:52:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:52:37:elinks:INFO: Disabling clock on downlink 0
14:52:37:elinks:INFO: Disabling clock on downlink 1
14:52:37:elinks:INFO: Disabling clock on downlink 2
14:52:37:elinks:INFO: Disabling clock on downlink 3
14:52:37:elinks:INFO: Disabling clock on downlink 4
14:52:37:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:52:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:52:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:52:37:elinks:INFO: Disabling clock on downlink 0
14:52:37:elinks:INFO: Disabling clock on downlink 1
14:52:37:elinks:INFO: Disabling clock on downlink 2
14:52:37:elinks:INFO: Disabling clock on downlink 3
14:52:37:elinks:INFO: Disabling clock on downlink 4
14:52:37:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:52:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:52:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:52:37:setup_element:INFO: Scanning clock phase
14:52:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:52:37:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:52:37:setup_element:INFO: Clock phase scan results for group 0, downlink 2
14:52:37:setup_element:INFO: Eye window for uplink 16: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:52:37:setup_element:INFO: Eye window for uplink 17: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:52:37:setup_element:INFO: Eye window for uplink 18: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:52:37:setup_element:INFO: Eye window for uplink 19: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:52:37:setup_element:INFO: Eye window for uplink 20: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:52:37:setup_element:INFO: Eye window for uplink 21: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:52:37:setup_element:INFO: Eye window for uplink 22: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:52:37:setup_element:INFO: Eye window for uplink 23: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:52:37:setup_element:INFO: Eye window for uplink 24: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:52:37:setup_element:INFO: Eye window for uplink 25: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:52:37:setup_element:INFO: Eye window for uplink 26: _______________________________________________________________________XXXXXX___
Clock Delay: 33
14:52:37:setup_element:INFO: Eye window for uplink 27: _______________________________________________________________________XXXXXX___
Clock Delay: 33
14:52:37:setup_element:INFO: Eye window for uplink 28: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:52:37:setup_element:INFO: Eye window for uplink 29: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:52:37:setup_element:INFO: Eye window for uplink 30: _________________________________________________________________________XXXXXX_
Clock Delay: 35
14:52:37:setup_element:INFO: Eye window for uplink 31: _________________________________________________________________________XXXXXX_
Clock Delay: 35
14:52:37:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 2
14:52:37:setup_element:INFO: Scanning data phases
14:52:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:52:38:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:52:43:setup_element:INFO: Data phase scan results for group 0, downlink 2
14:52:43:setup_element:INFO: Eye window for uplink 16: X_________________________________XXXXXX
Data delay found: 17
14:52:43:setup_element:INFO: Eye window for uplink 17: ________________________________XXXX____
Data delay found: 13
14:52:43:setup_element:INFO: Eye window for uplink 18: ___________________________________XXXXX
Data delay found: 17
14:52:43:setup_element:INFO: Eye window for uplink 19: _______________________________XXXXX____
Data delay found: 13
14:52:43:setup_element:INFO: Eye window for uplink 20: _______________________________XXXX_____
Data delay found: 12
14:52:43:setup_element:INFO: Eye window for uplink 21: _____________________________XXXXX______
Data delay found: 11
14:52:43:setup_element:INFO: Eye window for uplink 22: _________________________________XXXX___
Data delay found: 14
14:52:43:setup_element:INFO: Eye window for uplink 23: _____________________________XXXX_______
Data delay found: 10
14:52:43:setup_element:INFO: Eye window for uplink 24: __XXXXXX________________________________
Data delay found: 24
14:52:43:setup_element:INFO: Eye window for uplink 25: ______XXXXX_____________________________
Data delay found: 28
14:52:43:setup_element:INFO: Eye window for uplink 26: __XXXXX_________________________________
Data delay found: 24
14:52:43:setup_element:INFO: Eye window for uplink 27: ______XXXXXX____________________________
Data delay found: 28
14:52:43:setup_element:INFO: Eye window for uplink 28: ________XXXXX___________________________
Data delay found: 30
14:52:43:setup_element:INFO: Eye window for uplink 29: __________XXXXX_________________________
Data delay found: 32
14:52:43:setup_element:INFO: Eye window for uplink 30: ___________XXXXXX_______________________
Data delay found: 33
14:52:43:setup_element:INFO: Eye window for uplink 31: ____________XXXX________________________
Data delay found: 33
14:52:43:setup_element:INFO: Setting the data phase to 17 for uplink 16
14:52:43:setup_element:INFO: Setting the data phase to 13 for uplink 17
14:52:43:setup_element:INFO: Setting the data phase to 17 for uplink 18
14:52:43:setup_element:INFO: Setting the data phase to 13 for uplink 19
14:52:43:setup_element:INFO: Setting the data phase to 12 for uplink 20
14:52:43:setup_element:INFO: Setting the data phase to 11 for uplink 21
14:52:43:setup_element:INFO: Setting the data phase to 14 for uplink 22
14:52:43:setup_element:INFO: Setting the data phase to 10 for uplink 23
14:52:43:setup_element:INFO: Setting the data phase to 24 for uplink 24
14:52:43:setup_element:INFO: Setting the data phase to 28 for uplink 25
14:52:43:setup_element:INFO: Setting the data phase to 24 for uplink 26
14:52:43:setup_element:INFO: Setting the data phase to 28 for uplink 27
14:52:43:setup_element:INFO: Setting the data phase to 30 for uplink 28
14:52:43:setup_element:INFO: Setting the data phase to 32 for uplink 29
14:52:43:setup_element:INFO: Setting the data phase to 33 for uplink 30
14:52:43:setup_element:INFO: Setting the data phase to 33 for uplink 31
14:52:43:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 72
Eye Windows:
Uplink 16: __________________________________________________________________________XXXXX_
Uplink 17: __________________________________________________________________________XXXXX_
Uplink 18: __________________________________________________________________________XXXXX_
Uplink 19: __________________________________________________________________________XXXXX_
Uplink 20: ________________________________________________________________________XXXXXX__
Uplink 21: ________________________________________________________________________XXXXXX__
Uplink 22: ________________________________________________________________________XXXXXX__
Uplink 23: ________________________________________________________________________XXXXXX__
Uplink 24: _________________________________________________________________________XXXXX__
Uplink 25: _________________________________________________________________________XXXXX__
Uplink 26: _______________________________________________________________________XXXXXX___
Uplink 27: _______________________________________________________________________XXXXXX___
Uplink 28: _________________________________________________________________________XXXXX__
Uplink 29: _________________________________________________________________________XXXXX__
Uplink 30: _________________________________________________________________________XXXXXX_
Uplink 31: _________________________________________________________________________XXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXXX
Uplink 17:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 18:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 19:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 20:
Optimal Phase: 12
Window Length: 36
Eye Window: _______________________________XXXX_____
Uplink 21:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 22:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 23:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 24:
Optimal Phase: 24
Window Length: 34
Eye Window: __XXXXXX________________________________
Uplink 25:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 26:
Optimal Phase: 24
Window Length: 35
Eye Window: __XXXXX_________________________________
Uplink 27:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 28:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 29:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 30:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 31:
Optimal Phase: 33
Window Length: 36
Eye Window: ____________XXXX________________________
]
14:52:43:setup_element:INFO: Beginning SMX ASICs map scan
14:52:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:52:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:52:43:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
14:52:43:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
14:52:43:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
14:52:43:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
14:52:43:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
14:52:43:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
14:52:43:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
14:52:43:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
14:52:43:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
14:52:43:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
14:52:43:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
14:52:43:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
14:52:44:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
14:52:44:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
14:52:44:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
14:52:44:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
14:52:44:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
14:52:44:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
14:52:44:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
14:52:45:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 72
Eye Windows:
Uplink 16: __________________________________________________________________________XXXXX_
Uplink 17: __________________________________________________________________________XXXXX_
Uplink 18: __________________________________________________________________________XXXXX_
Uplink 19: __________________________________________________________________________XXXXX_
Uplink 20: ________________________________________________________________________XXXXXX__
Uplink 21: ________________________________________________________________________XXXXXX__
Uplink 22: ________________________________________________________________________XXXXXX__
Uplink 23: ________________________________________________________________________XXXXXX__
Uplink 24: _________________________________________________________________________XXXXX__
Uplink 25: _________________________________________________________________________XXXXX__
Uplink 26: _______________________________________________________________________XXXXXX___
Uplink 27: _______________________________________________________________________XXXXXX___
Uplink 28: _________________________________________________________________________XXXXX__
Uplink 29: _________________________________________________________________________XXXXX__
Uplink 30: _________________________________________________________________________XXXXXX_
Uplink 31: _________________________________________________________________________XXXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 17
Window Length: 33
Eye Window: X_________________________________XXXXXX
Uplink 17:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 18:
Optimal Phase: 17
Window Length: 35
Eye Window: ___________________________________XXXXX
Uplink 19:
Optimal Phase: 13
Window Length: 35
Eye Window: _______________________________XXXXX____
Uplink 20:
Optimal Phase: 12
Window Length: 36
Eye Window: _______________________________XXXX_____
Uplink 21:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 22:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 23:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 24:
Optimal Phase: 24
Window Length: 34
Eye Window: __XXXXXX________________________________
Uplink 25:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
Uplink 26:
Optimal Phase: 24
Window Length: 35
Eye Window: __XXXXX_________________________________
Uplink 27:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 28:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 29:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 30:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 31:
Optimal Phase: 33
Window Length: 36
Eye Window: ____________XXXX________________________
14:52:45:setup_element:INFO: Performing Elink synchronization
14:52:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:52:45:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:52:45:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
14:52:45:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
14:52:45:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
14:52:45:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
14:52:46:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
FEB type: B FEB_A: 0 FEB_B: 1
14:52:47:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:52:47:febtest:INFO: 23-00 | XA-000-08-002-000-007-008-06 | 50.4 | 1165.6
14:52:47:febtest:INFO: 30-01 | XA-000-08-002-000-007-199-09 | 47.3 | 1183.3
14:52:48:febtest:INFO: 21-02 | XA-000-08-002-000-007-031-01 | 31.4 | 1236.2
14:52:48:febtest:INFO: 28-03 | XA-000-08-002-000-007-198-09 | 47.3 | 1183.3
14:52:48:febtest:INFO: 19-04 | XA-000-08-002-000-007-041-08 | 21.9 | 1253.7
14:52:48:febtest:INFO: 26-05 | XA-000-08-002-000-007-127-10 | 44.1 | 1189.2
14:52:49:febtest:INFO: 17-06 | XA-000-08-002-000-007-047-08 | 15.6 | 1282.9
14:52:49:febtest:INFO: 24-07 | XA-000-08-002-000-007-083-04 | 37.7 | 1206.9
14:52:49:ST3_smx:INFO: Configuring SMX FAST
14:52:51:ST3_smx:INFO: chip: 23-0 47.250730 C 1177.390875 mV
14:52:51:ST3_smx:INFO: Electrons
14:52:51:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:52:53:ST3_smx:INFO: ----> Checking Analog response
14:52:53:ST3_smx:INFO: ----> Checking broken channels
14:52:54:ST3_smx:INFO: Total # broken ch: 0
14:52:54:ST3_smx:INFO: List FAST: []
14:52:54:ST3_smx:INFO: List SLOW: []
14:52:54:ST3_smx:INFO: Holes
14:52:54:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:52:56:ST3_smx:INFO: ----> Checking Analog response
14:52:56:ST3_smx:INFO: ----> Checking broken channels
14:52:56:ST3_smx:INFO: Total # broken ch: 0
14:52:56:ST3_smx:INFO: List FAST: []
14:52:56:ST3_smx:INFO: List SLOW: []
14:52:56:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:52:56:febtest:INFO: 23-00 | XA-000-08-002-000-007-008-06 | 50.4 | 1171.5
14:52:56:febtest:INFO: 30-01 | XA-000-08-002-000-007-199-09 | 47.3 | 1183.3
14:52:57:febtest:INFO: 21-02 | XA-000-08-002-000-007-031-01 | 31.4 | 1236.2
14:52:57:febtest:INFO: 28-03 | XA-000-08-002-000-007-198-09 | 47.3 | 1183.3
14:52:57:febtest:INFO: 19-04 | XA-000-08-002-000-007-041-08 | 21.9 | 1259.6
14:52:57:febtest:INFO: 26-05 | XA-000-08-002-000-007-127-10 | 47.3 | 1189.2
14:52:57:febtest:INFO: 17-06 | XA-000-08-002-000-007-047-08 | 18.7 | 1282.9
14:52:58:febtest:INFO: 24-07 | XA-000-08-002-000-007-083-04 | 37.7 | 1206.9
14:52:58:ST3_smx:INFO: Configuring SMX FAST
14:53:00:ST3_smx:INFO: chip: 30-1 50.430383 C 1177.390875 mV
14:53:00:ST3_smx:INFO: Electrons
14:53:00:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:02:ST3_smx:INFO: ----> Checking Analog response
14:53:02:ST3_smx:INFO: ----> Checking broken channels
14:53:02:ST3_smx:INFO: Total # broken ch: 0
14:53:02:ST3_smx:INFO: List FAST: []
14:53:02:ST3_smx:INFO: List SLOW: []
14:53:02:ST3_smx:INFO: Holes
14:53:02:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:04:ST3_smx:INFO: ----> Checking Analog response
14:53:04:ST3_smx:INFO: ----> Checking broken channels
14:53:05:ST3_smx:INFO: Total # broken ch: 0
14:53:05:ST3_smx:INFO: List FAST: []
14:53:05:ST3_smx:INFO: List SLOW: []
14:53:05:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:53:05:febtest:INFO: 23-00 | XA-000-08-002-000-007-008-06 | 47.3 | 1171.5
14:53:05:febtest:INFO: 30-01 | XA-000-08-002-000-007-199-09 | 53.6 | 1171.5
14:53:05:febtest:INFO: 21-02 | XA-000-08-002-000-007-031-01 | 31.4 | 1236.2
14:53:05:febtest:INFO: 28-03 | XA-000-08-002-000-007-198-09 | 47.3 | 1183.3
14:53:06:febtest:INFO: 19-04 | XA-000-08-002-000-007-041-08 | 25.1 | 1253.7
14:53:06:febtest:INFO: 26-05 | XA-000-08-002-000-007-127-10 | 44.1 | 1189.2
14:53:06:febtest:INFO: 17-06 | XA-000-08-002-000-007-047-08 | 18.7 | 1282.9
14:53:06:febtest:INFO: 24-07 | XA-000-08-002-000-007-083-04 | 37.7 | 1212.7
14:53:07:ST3_smx:INFO: Configuring SMX FAST
14:53:09:ST3_smx:INFO: chip: 21-2 44.073563 C 1206.851500 mV
14:53:09:ST3_smx:INFO: Electrons
14:53:09:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:11:ST3_smx:INFO: ----> Checking Analog response
14:53:11:ST3_smx:INFO: ----> Checking broken channels
14:53:11:ST3_smx:INFO: Total # broken ch: 0
14:53:11:ST3_smx:INFO: List FAST: []
14:53:11:ST3_smx:INFO: List SLOW: []
14:53:11:ST3_smx:INFO: Holes
14:53:11:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:13:ST3_smx:INFO: ----> Checking Analog response
14:53:13:ST3_smx:INFO: ----> Checking broken channels
14:53:14:ST3_smx:INFO: Total # broken ch: 0
14:53:14:ST3_smx:INFO: List FAST: []
14:53:14:ST3_smx:INFO: List SLOW: []
14:53:14:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:53:14:febtest:INFO: 23-00 | XA-000-08-002-000-007-008-06 | 47.3 | 1177.4
14:53:14:febtest:INFO: 30-01 | XA-000-08-002-000-007-199-09 | 53.6 | 1171.5
14:53:14:febtest:INFO: 21-02 | XA-000-08-002-000-007-031-01 | 44.1 | 1201.0
14:53:14:febtest:INFO: 28-03 | XA-000-08-002-000-007-198-09 | 47.3 | 1183.3
14:53:15:febtest:INFO: 19-04 | XA-000-08-002-000-007-041-08 | 25.1 | 1253.7
14:53:15:febtest:INFO: 26-05 | XA-000-08-002-000-007-127-10 | 47.3 | 1189.2
14:53:15:febtest:INFO: 17-06 | XA-000-08-002-000-007-047-08 | 18.7 | 1288.7
14:53:15:febtest:INFO: 24-07 | XA-000-08-002-000-007-083-04 | 37.7 | 1206.9
14:53:16:ST3_smx:INFO: Configuring SMX FAST
14:53:18:ST3_smx:INFO: chip: 28-3 50.430383 C 1171.483840 mV
14:53:18:ST3_smx:INFO: Electrons
14:53:18:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:20:ST3_smx:INFO: ----> Checking Analog response
14:53:20:ST3_smx:INFO: ----> Checking broken channels
14:53:20:ST3_smx:INFO: Total # broken ch: 0
14:53:20:ST3_smx:INFO: List FAST: []
14:53:20:ST3_smx:INFO: List SLOW: []
14:53:20:ST3_smx:INFO: Holes
14:53:20:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:22:ST3_smx:INFO: ----> Checking Analog response
14:53:22:ST3_smx:INFO: ----> Checking broken channels
14:53:22:ST3_smx:INFO: Total # broken ch: 0
14:53:22:ST3_smx:INFO: List FAST: []
14:53:22:ST3_smx:INFO: List SLOW: []
14:53:22:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:53:23:febtest:INFO: 23-00 | XA-000-08-002-000-007-008-06 | 50.4 | 1177.4
14:53:23:febtest:INFO: 30-01 | XA-000-08-002-000-007-199-09 | 53.6 | 1171.5
14:53:23:febtest:INFO: 21-02 | XA-000-08-002-000-007-031-01 | 44.1 | 1201.0
14:53:23:febtest:INFO: 28-03 | XA-000-08-002-000-007-198-09 | 53.6 | 1171.5
14:53:23:febtest:INFO: 19-04 | XA-000-08-002-000-007-041-08 | 25.1 | 1259.6
14:53:24:febtest:INFO: 26-05 | XA-000-08-002-000-007-127-10 | 47.3 | 1189.2
14:53:24:febtest:INFO: 17-06 | XA-000-08-002-000-007-047-08 | 18.7 | 1288.7
14:53:24:febtest:INFO: 24-07 | XA-000-08-002-000-007-083-04 | 37.7 | 1212.7
14:53:25:ST3_smx:INFO: Configuring SMX FAST
14:53:27:ST3_smx:INFO: chip: 19-4 25.062742 C 1259.567515 mV
14:53:27:ST3_smx:INFO: Electrons
14:53:27:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:29:ST3_smx:INFO: ----> Checking Analog response
14:53:29:ST3_smx:INFO: ----> Checking broken channels
14:53:29:ST3_smx:INFO: Total # broken ch: 0
14:53:29:ST3_smx:INFO: List FAST: []
14:53:29:ST3_smx:INFO: List SLOW: []
14:53:29:ST3_smx:INFO: Holes
14:53:29:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:31:ST3_smx:INFO: ----> Checking Analog response
14:53:31:ST3_smx:INFO: ----> Checking broken channels
14:53:31:ST3_smx:INFO: Total # broken ch: 0
14:53:31:ST3_smx:INFO: List FAST: []
14:53:31:ST3_smx:INFO: List SLOW: []
14:53:31:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:53:31:febtest:INFO: 23-00 | XA-000-08-002-000-007-008-06 | 50.4 | 1177.4
14:53:31:febtest:INFO: 30-01 | XA-000-08-002-000-007-199-09 | 53.6 | 1171.5
14:53:32:febtest:INFO: 21-02 | XA-000-08-002-000-007-031-01 | 44.1 | 1206.9
14:53:32:febtest:INFO: 28-03 | XA-000-08-002-000-007-198-09 | 53.6 | 1171.5
14:53:32:febtest:INFO: 19-04 | XA-000-08-002-000-007-041-08 | 28.2 | 1253.7
14:53:32:febtest:INFO: 26-05 | XA-000-08-002-000-007-127-10 | 47.3 | 1189.2
14:53:32:febtest:INFO: 17-06 | XA-000-08-002-000-007-047-08 | 18.7 | 1288.7
14:53:33:febtest:INFO: 24-07 | XA-000-08-002-000-007-083-04 | 37.7 | 1212.7
14:53:33:ST3_smx:INFO: Configuring SMX FAST
14:53:35:ST3_smx:INFO: chip: 26-5 47.250730 C 1195.082160 mV
14:53:35:ST3_smx:INFO: Electrons
14:53:35:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:37:ST3_smx:INFO: ----> Checking Analog response
14:53:37:ST3_smx:INFO: ----> Checking broken channels
14:53:37:ST3_smx:INFO: Total # broken ch: 0
14:53:37:ST3_smx:INFO: List FAST: []
14:53:37:ST3_smx:INFO: List SLOW: []
14:53:37:ST3_smx:INFO: Holes
14:53:37:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:39:ST3_smx:INFO: ----> Checking Analog response
14:53:39:ST3_smx:INFO: ----> Checking broken channels
14:53:39:ST3_smx:INFO: Total # broken ch: 0
14:53:39:ST3_smx:INFO: List FAST: []
14:53:39:ST3_smx:INFO: List SLOW: []
14:53:39:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:53:39:febtest:INFO: 23-00 | XA-000-08-002-000-007-008-06 | 50.4 | 1177.4
14:53:40:febtest:INFO: 30-01 | XA-000-08-002-000-007-199-09 | 53.6 | 1171.5
14:53:40:febtest:INFO: 21-02 | XA-000-08-002-000-007-031-01 | 44.1 | 1206.9
14:53:40:febtest:INFO: 28-03 | XA-000-08-002-000-007-198-09 | 53.6 | 1171.5
14:53:40:febtest:INFO: 19-04 | XA-000-08-002-000-007-041-08 | 28.2 | 1259.6
14:53:41:febtest:INFO: 26-05 | XA-000-08-002-000-007-127-10 | 47.3 | 1195.1
14:53:41:febtest:INFO: 17-06 | XA-000-08-002-000-007-047-08 | 21.9 | 1288.7
14:53:41:febtest:INFO: 24-07 | XA-000-08-002-000-007-083-04 | 37.7 | 1212.7
14:53:42:ST3_smx:INFO: Configuring SMX FAST
14:53:44:ST3_smx:INFO: chip: 17-6 28.225000 C 1253.730060 mV
14:53:44:ST3_smx:INFO: Electrons
14:53:44:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:46:ST3_smx:INFO: ----> Checking Analog response
14:53:46:ST3_smx:INFO: ----> Checking broken channels
14:53:46:ST3_smx:INFO: Total # broken ch: 0
14:53:46:ST3_smx:INFO: List FAST: []
14:53:46:ST3_smx:INFO: List SLOW: []
14:53:46:ST3_smx:INFO: Holes
14:53:46:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:48:ST3_smx:INFO: ----> Checking Analog response
14:53:48:ST3_smx:INFO: ----> Checking broken channels
14:53:48:ST3_smx:INFO: Total # broken ch: 0
14:53:48:ST3_smx:INFO: List FAST: []
14:53:48:ST3_smx:INFO: List SLOW: []
14:53:48:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:53:48:febtest:INFO: 23-00 | XA-000-08-002-000-007-008-06 | 50.4 | 1177.4
14:53:48:febtest:INFO: 30-01 | XA-000-08-002-000-007-199-09 | 53.6 | 1177.4
14:53:48:febtest:INFO: 21-02 | XA-000-08-002-000-007-031-01 | 44.1 | 1206.9
14:53:49:febtest:INFO: 28-03 | XA-000-08-002-000-007-198-09 | 53.6 | 1171.5
14:53:49:febtest:INFO: 19-04 | XA-000-08-002-000-007-041-08 | 28.2 | 1259.6
14:53:49:febtest:INFO: 26-05 | XA-000-08-002-000-007-127-10 | 47.3 | 1195.1
14:53:49:febtest:INFO: 17-06 | XA-000-08-002-000-007-047-08 | 31.4 | 1253.7
14:53:50:febtest:INFO: 24-07 | XA-000-08-002-000-007-083-04 | 37.7 | 1212.7
14:53:50:ST3_smx:INFO: Configuring SMX FAST
14:53:52:ST3_smx:INFO: chip: 24-7 47.250730 C 1189.190035 mV
14:53:52:ST3_smx:INFO: Electrons
14:53:52:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:54:ST3_smx:INFO: ----> Checking Analog response
14:53:54:ST3_smx:INFO: ----> Checking broken channels
14:53:54:ST3_smx:INFO: Total # broken ch: 0
14:53:54:ST3_smx:INFO: List FAST: []
14:53:54:ST3_smx:INFO: List SLOW: []
14:53:54:ST3_smx:INFO: Holes
14:53:54:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:53:56:ST3_smx:INFO: ----> Checking Analog response
14:53:56:ST3_smx:INFO: ----> Checking broken channels
14:53:56:ST3_smx:INFO: Total # broken ch: 0
14:53:56:ST3_smx:INFO: List FAST: []
14:53:56:ST3_smx:INFO: List SLOW: []
14:53:56:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:53:56:febtest:INFO: 23-00 | XA-000-08-002-000-007-008-06 | 50.4 | 1177.4
14:53:57:febtest:INFO: 30-01 | XA-000-08-002-000-007-199-09 | 53.6 | 1177.4
14:53:57:febtest:INFO: 21-02 | XA-000-08-002-000-007-031-01 | 44.1 | 1206.9
14:53:57:febtest:INFO: 28-03 | XA-000-08-002-000-007-198-09 | 53.6 | 1171.5
14:53:57:febtest:INFO: 19-04 | XA-000-08-002-000-007-041-08 | 28.2 | 1259.6
14:53:57:febtest:INFO: 26-05 | XA-000-08-002-000-007-127-10 | 47.3 | 1195.1
14:53:58:febtest:INFO: 17-06 | XA-000-08-002-000-007-047-08 | 31.4 | 1253.7
14:53:58:febtest:INFO: 24-07 | XA-000-08-002-000-007-083-04 | 47.3 | 1183.3
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '24_02_22-14_52_33', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'KIT', 'SITE': 'KIT', 'SETUP': 'KIT_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-007-083-04', 'FUSED_ID': 6359364699116565812, 'HW_ADDR': 7, 'UPLINK': 24, 'VERS_NO': '', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'FEB_SN': '2035', 'FEB_TYPE': 8.2, 'FEB_UPLINKS': 2, 'FEB_A': 0, 'FEB_B': 1, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.800', '1.8920', '2.200', '2.5240', '0.000', '0.0000', '7.001', '1.6690'], 'VI_aInit': ['0', '0', '0', '0', '0', '0'], 'VI_atEnd': ['0', '0', '0', '0', '0', '0'], 'AMP_CAL': 150, 'PlsLoop': 500, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 24_02_22-14_52_33
OPERATOR : Alois Alzheimer
SITE : KIT
SETUP : KIT_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME :
FEB_SN : 2035
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 0
FEB_B : 1
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.800', '1.8920', '2.200', '2.5240', '0.000', '0.0000', '7.001', '1.6690']
VI_after__Init : ['2.800', '1.9910', '2.200', '0.3194', '0.000', '0.0000', '7.000', '1.6630']
VI_at__the_End : ['2.800', '1.9910', '2.200', '0.3194', '0.000', '0.0000', '7.000', '1.6630']
14:55:17:ST3_Shared:INFO: cp -r tar/KIT/ /home/cbm/public_html/tests/
14:55:33:febtest:INFO: FEB 8-2 selected
14:55:33:smx_tester:INFO: Setting Elink clock mode to 160 MHz
14:55:33:febtest:INFO: FEB type: 8.2
14:55:33:febtest:INFO: FEB SN: 3000
14:55:33:febtest:INFO: FEB A: 1
14:55:33:febtest:INFO: FEB B: 0
14:55:43:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:55:43:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
14:55:43:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:55:43:febtest:INFO: Testing FEB with SN 3000
14:55:46:smx_tester:INFO: Scanning setup
14:55:46:elinks:INFO: Disabling clock on downlink 0
14:55:46:elinks:INFO: Disabling clock on downlink 1
14:55:46:elinks:INFO: Disabling clock on downlink 2
14:55:46:elinks:INFO: Disabling clock on downlink 3
14:55:46:elinks:INFO: Disabling clock on downlink 4
14:55:46:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:55:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:55:46:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:55:46:elinks:INFO: Disabling clock on downlink 0
14:55:46:elinks:INFO: Disabling clock on downlink 1
14:55:46:elinks:INFO: Disabling clock on downlink 2
14:55:46:elinks:INFO: Disabling clock on downlink 3
14:55:46:elinks:INFO: Disabling clock on downlink 4
14:55:46:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:55:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:55:46:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:55:46:elinks:INFO: Disabling clock on downlink 0
14:55:46:elinks:INFO: Disabling clock on downlink 1
14:55:46:elinks:INFO: Disabling clock on downlink 2
14:55:46:elinks:INFO: Disabling clock on downlink 3
14:55:46:elinks:INFO: Disabling clock on downlink 4
14:55:46:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:55:46:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:55:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
14:55:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
14:55:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
14:55:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
14:55:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
14:55:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
14:55:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
14:55:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
14:55:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
14:55:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
14:55:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
14:55:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
14:55:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
14:55:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
14:55:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
14:55:46:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
14:55:47:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:55:47:elinks:INFO: Disabling clock on downlink 0
14:55:47:elinks:INFO: Disabling clock on downlink 1
14:55:47:elinks:INFO: Disabling clock on downlink 2
14:55:47:elinks:INFO: Disabling clock on downlink 3
14:55:47:elinks:INFO: Disabling clock on downlink 4
14:55:47:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:55:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:55:47:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:55:47:elinks:INFO: Disabling clock on downlink 0
14:55:47:elinks:INFO: Disabling clock on downlink 1
14:55:47:elinks:INFO: Disabling clock on downlink 2
14:55:47:elinks:INFO: Disabling clock on downlink 3
14:55:47:elinks:INFO: Disabling clock on downlink 4
14:55:47:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:55:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:55:47:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:55:47:setup_element:INFO: Scanning clock phase
14:55:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:55:47:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:55:47:setup_element:INFO: Clock phase scan results for group 0, downlink 2
14:55:47:setup_element:INFO: Eye window for uplink 16: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:55:47:setup_element:INFO: Eye window for uplink 17: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:55:47:setup_element:INFO: Eye window for uplink 18: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:55:47:setup_element:INFO: Eye window for uplink 19: _________________________________________________________________________XXXXXX_
Clock Delay: 35
14:55:47:setup_element:INFO: Eye window for uplink 20: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:55:47:setup_element:INFO: Eye window for uplink 21: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:55:47:setup_element:INFO: Eye window for uplink 22: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:55:47:setup_element:INFO: Eye window for uplink 23: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:55:47:setup_element:INFO: Eye window for uplink 24: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:55:47:setup_element:INFO: Eye window for uplink 25: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:55:47:setup_element:INFO: Eye window for uplink 26: _______________________________________________________________________XXXXXX___
Clock Delay: 33
14:55:47:setup_element:INFO: Eye window for uplink 27: _______________________________________________________________________XXXXXX___
Clock Delay: 33
14:55:47:setup_element:INFO: Eye window for uplink 28: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:55:47:setup_element:INFO: Eye window for uplink 29: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:55:47:setup_element:INFO: Eye window for uplink 30: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:55:47:setup_element:INFO: Eye window for uplink 31: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:55:47:setup_element:INFO: Setting the clock phase to 34 for group 0, downlink 2
14:55:47:setup_element:INFO: Scanning data phases
14:55:47:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:55:47:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:55:52:setup_element:INFO: Data phase scan results for group 0, downlink 2
14:55:52:setup_element:INFO: Eye window for uplink 16: XX_________________________________XXXXX
Data delay found: 18
14:55:52:setup_element:INFO: Eye window for uplink 17: ________________________________XXXX____
Data delay found: 13
14:55:52:setup_element:INFO: Eye window for uplink 18: ___________________________________XXXX_
Data delay found: 16
14:55:52:setup_element:INFO: Eye window for uplink 19: ________________________________XXXX____
Data delay found: 13
14:55:52:setup_element:INFO: Eye window for uplink 20: _______________________________XXXX_____
Data delay found: 12
14:55:52:setup_element:INFO: Eye window for uplink 21: _____________________________XXXXX______
Data delay found: 11
14:55:52:setup_element:INFO: Eye window for uplink 22: _________________________________XXXX___
Data delay found: 14
14:55:52:setup_element:INFO: Eye window for uplink 23: _____________________________XXXX_______
Data delay found: 10
14:55:52:setup_element:INFO: Eye window for uplink 24: __XXXXXX________________________________
Data delay found: 24
14:55:52:setup_element:INFO: Eye window for uplink 25: _____XXXXXX_____________________________
Data delay found: 27
14:55:52:setup_element:INFO: Eye window for uplink 26: _XXXXXX_________________________________
Data delay found: 23
14:55:52:setup_element:INFO: Eye window for uplink 27: ______XXXXXX____________________________
Data delay found: 28
14:55:52:setup_element:INFO: Eye window for uplink 28: ________XXXXX___________________________
Data delay found: 30
14:55:52:setup_element:INFO: Eye window for uplink 29: __________XXXXX_________________________
Data delay found: 32
14:55:52:setup_element:INFO: Eye window for uplink 30: ___________XXXXXX_______________________
Data delay found: 33
14:55:52:setup_element:INFO: Eye window for uplink 31: ____________XXXX________________________
Data delay found: 33
14:55:52:setup_element:INFO: Setting the data phase to 18 for uplink 16
14:55:52:setup_element:INFO: Setting the data phase to 13 for uplink 17
14:55:52:setup_element:INFO: Setting the data phase to 16 for uplink 18
14:55:52:setup_element:INFO: Setting the data phase to 13 for uplink 19
14:55:52:setup_element:INFO: Setting the data phase to 12 for uplink 20
14:55:52:setup_element:INFO: Setting the data phase to 11 for uplink 21
14:55:52:setup_element:INFO: Setting the data phase to 14 for uplink 22
14:55:52:setup_element:INFO: Setting the data phase to 10 for uplink 23
14:55:52:setup_element:INFO: Setting the data phase to 24 for uplink 24
14:55:52:setup_element:INFO: Setting the data phase to 27 for uplink 25
14:55:52:setup_element:INFO: Setting the data phase to 23 for uplink 26
14:55:52:setup_element:INFO: Setting the data phase to 28 for uplink 27
14:55:52:setup_element:INFO: Setting the data phase to 30 for uplink 28
14:55:52:setup_element:INFO: Setting the data phase to 32 for uplink 29
14:55:52:setup_element:INFO: Setting the data phase to 33 for uplink 30
14:55:52:setup_element:INFO: Setting the data phase to 33 for uplink 31
14:55:52:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 72
Eye Windows:
Uplink 16: __________________________________________________________________________XXXXX_
Uplink 17: __________________________________________________________________________XXXXX_
Uplink 18: _________________________________________________________________________XXXXX__
Uplink 19: _________________________________________________________________________XXXXXX_
Uplink 20: ________________________________________________________________________XXXXXX__
Uplink 21: ________________________________________________________________________XXXXXX__
Uplink 22: ________________________________________________________________________XXXXXX__
Uplink 23: ________________________________________________________________________XXXXXX__
Uplink 24: _________________________________________________________________________XXXXX__
Uplink 25: _________________________________________________________________________XXXXX__
Uplink 26: _______________________________________________________________________XXXXXX___
Uplink 27: _______________________________________________________________________XXXXXX___
Uplink 28: _________________________________________________________________________XXXXX__
Uplink 29: _________________________________________________________________________XXXXX__
Uplink 30: __________________________________________________________________________XXXXX_
Uplink 31: __________________________________________________________________________XXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 17:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 18:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 19:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 20:
Optimal Phase: 12
Window Length: 36
Eye Window: _______________________________XXXX_____
Uplink 21:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 22:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 23:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 24:
Optimal Phase: 24
Window Length: 34
Eye Window: __XXXXXX________________________________
Uplink 25:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 26:
Optimal Phase: 23
Window Length: 34
Eye Window: _XXXXXX_________________________________
Uplink 27:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 28:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 29:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 30:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 31:
Optimal Phase: 33
Window Length: 36
Eye Window: ____________XXXX________________________
]
14:55:52:setup_element:INFO: Beginning SMX ASICs map scan
14:55:52:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:55:52:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:55:52:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
14:55:52:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
14:55:52:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
14:55:52:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
14:55:52:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
14:55:53:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
14:55:53:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
14:55:53:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
14:55:53:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
14:55:53:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
14:55:53:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
14:55:53:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
14:55:53:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
14:55:53:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
14:55:53:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
14:55:53:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
14:55:54:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
14:55:54:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
14:55:54:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
14:55:55:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 34
Window Length: 72
Eye Windows:
Uplink 16: __________________________________________________________________________XXXXX_
Uplink 17: __________________________________________________________________________XXXXX_
Uplink 18: _________________________________________________________________________XXXXX__
Uplink 19: _________________________________________________________________________XXXXXX_
Uplink 20: ________________________________________________________________________XXXXXX__
Uplink 21: ________________________________________________________________________XXXXXX__
Uplink 22: ________________________________________________________________________XXXXXX__
Uplink 23: ________________________________________________________________________XXXXXX__
Uplink 24: _________________________________________________________________________XXXXX__
Uplink 25: _________________________________________________________________________XXXXX__
Uplink 26: _______________________________________________________________________XXXXXX___
Uplink 27: _______________________________________________________________________XXXXXX___
Uplink 28: _________________________________________________________________________XXXXX__
Uplink 29: _________________________________________________________________________XXXXX__
Uplink 30: __________________________________________________________________________XXXXX_
Uplink 31: __________________________________________________________________________XXXXX_
Data phase characteristics:
Uplink 16:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 17:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 18:
Optimal Phase: 16
Window Length: 36
Eye Window: ___________________________________XXXX_
Uplink 19:
Optimal Phase: 13
Window Length: 36
Eye Window: ________________________________XXXX____
Uplink 20:
Optimal Phase: 12
Window Length: 36
Eye Window: _______________________________XXXX_____
Uplink 21:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 22:
Optimal Phase: 14
Window Length: 36
Eye Window: _________________________________XXXX___
Uplink 23:
Optimal Phase: 10
Window Length: 36
Eye Window: _____________________________XXXX_______
Uplink 24:
Optimal Phase: 24
Window Length: 34
Eye Window: __XXXXXX________________________________
Uplink 25:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 26:
Optimal Phase: 23
Window Length: 34
Eye Window: _XXXXXX_________________________________
Uplink 27:
Optimal Phase: 28
Window Length: 34
Eye Window: ______XXXXXX____________________________
Uplink 28:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
Uplink 29:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 30:
Optimal Phase: 33
Window Length: 34
Eye Window: ___________XXXXXX_______________________
Uplink 31:
Optimal Phase: 33
Window Length: 36
Eye Window: ____________XXXX________________________
14:55:55:setup_element:INFO: Performing Elink synchronization
14:55:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:55:55:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
14:55:55:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
14:55:55:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
14:55:55:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
14:55:55:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
14:55:55:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
FEB type: B FEB_A: 1 FEB_B: 0
14:55:56:febtest:ERROR: You have entered FEB A number and connected to B
14:56:27:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:56:27:ST3_Shared:INFO: --------------------------FEB-ASIC--------------------------
14:56:27:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:56:28:febtest:INFO: Testing FEB with SN 3000
14:56:30:smx_tester:INFO: Scanning setup
14:56:30:elinks:INFO: Disabling clock on downlink 0
14:56:30:elinks:INFO: Disabling clock on downlink 1
14:56:30:elinks:INFO: Disabling clock on downlink 2
14:56:30:elinks:INFO: Disabling clock on downlink 3
14:56:30:elinks:INFO: Disabling clock on downlink 4
14:56:30:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:56:30:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:56:31:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 0
14:56:31:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 1
14:56:31:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 2
14:56:31:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 3
14:56:31:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 4
14:56:31:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 5
14:56:31:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 6
14:56:31:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 7
14:56:31:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 8
14:56:31:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 9
14:56:31:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 10
14:56:31:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 11
14:56:31:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 12
14:56:31:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 13
14:56:31:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 14
14:56:31:setup_element:INFO: SOS detected for group 0, downlink 0, uplink 15
14:56:31:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:56:31:elinks:INFO: Disabling clock on downlink 0
14:56:31:elinks:INFO: Disabling clock on downlink 1
14:56:31:elinks:INFO: Disabling clock on downlink 2
14:56:31:elinks:INFO: Disabling clock on downlink 3
14:56:31:elinks:INFO: Disabling clock on downlink 4
14:56:31:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:56:31:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:56:31:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:56:31:elinks:INFO: Disabling clock on downlink 0
14:56:31:elinks:INFO: Disabling clock on downlink 1
14:56:31:elinks:INFO: Disabling clock on downlink 2
14:56:31:elinks:INFO: Disabling clock on downlink 3
14:56:31:elinks:INFO: Disabling clock on downlink 4
14:56:31:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:56:31:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:56:31:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:56:31:elinks:INFO: Disabling clock on downlink 0
14:56:31:elinks:INFO: Disabling clock on downlink 1
14:56:31:elinks:INFO: Disabling clock on downlink 2
14:56:31:elinks:INFO: Disabling clock on downlink 3
14:56:31:elinks:INFO: Disabling clock on downlink 4
14:56:31:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:56:31:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:56:31:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:56:31:elinks:INFO: Disabling clock on downlink 0
14:56:31:elinks:INFO: Disabling clock on downlink 1
14:56:31:elinks:INFO: Disabling clock on downlink 2
14:56:31:elinks:INFO: Disabling clock on downlink 3
14:56:31:elinks:INFO: Disabling clock on downlink 4
14:56:31:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:56:31:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:56:31:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:56:31:setup_element:INFO: Scanning clock phase
14:56:31:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:56:31:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
14:56:31:setup_element:INFO: Clock phase scan results for group 0, downlink 0
14:56:31:setup_element:INFO: Eye window for uplink 0 : ___________________________________________________________________________XXXXX
Clock Delay: 37
14:56:31:setup_element:INFO: Eye window for uplink 1 : ___________________________________________________________________________XXXXX
Clock Delay: 37
14:56:31:setup_element:INFO: Eye window for uplink 2 : __________________________________________________________________________XXXXXX
Clock Delay: 36
14:56:31:setup_element:INFO: Eye window for uplink 3 : __________________________________________________________________________XXXXXX
Clock Delay: 36
14:56:31:setup_element:INFO: Eye window for uplink 4 : ________________________________________________________________________________
Clock Delay: 40
14:56:31:setup_element:INFO: Eye window for uplink 5 : ________________________________________________________________________________
Clock Delay: 40
14:56:31:setup_element:INFO: Eye window for uplink 6 : _________________________________________________________________________XXXXXX_
Clock Delay: 35
14:56:31:setup_element:INFO: Eye window for uplink 7 : _________________________________________________________________________XXXXXX_
Clock Delay: 35
14:56:31:setup_element:INFO: Eye window for uplink 8 : __________________________________________________________________________XXXXX_
Clock Delay: 36
14:56:31:setup_element:INFO: Eye window for uplink 9 : __________________________________________________________________________XXXXX_
Clock Delay: 36
14:56:31:setup_element:INFO: Eye window for uplink 10: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:56:31:setup_element:INFO: Eye window for uplink 11: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:56:31:setup_element:INFO: Eye window for uplink 12: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:56:31:setup_element:INFO: Eye window for uplink 13: __________________________________________________________________________XXXXX_
Clock Delay: 36
14:56:31:setup_element:INFO: Eye window for uplink 14: __________________________________________________________________________XXXXXX
Clock Delay: 36
14:56:31:setup_element:INFO: Eye window for uplink 15: __________________________________________________________________________XXXXXX
Clock Delay: 36
14:56:31:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 0
14:56:31:setup_element:INFO: Scanning data phases
14:56:31:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:56:32:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
14:56:37:setup_element:INFO: Data phase scan results for group 0, downlink 0
14:56:37:setup_element:INFO: Eye window for uplink 0 : ______________________________XXXXX_____
Data delay found: 12
14:56:37:setup_element:INFO: Eye window for uplink 1 : ___________________________XXXXX________
Data delay found: 9
14:56:37:setup_element:INFO: Eye window for uplink 2 : _____________________________XXXXX______
Data delay found: 11
14:56:37:setup_element:INFO: Eye window for uplink 3 : __________________________XXXX__________
Data delay found: 7
14:56:37:setup_element:INFO: Eye window for uplink 4 : __________________________XXXXX_________
Data delay found: 8
14:56:37:setup_element:INFO: Eye window for uplink 5 : _______________________XXXXX____________
Data delay found: 5
14:56:37:setup_element:INFO: Eye window for uplink 6 : _________________________XXXX___________
Data delay found: 6
14:56:37:setup_element:INFO: Eye window for uplink 7 : ______________________XXXX______________
Data delay found: 3
14:56:37:setup_element:INFO: Eye window for uplink 8 : _______________________________XXXXXX___
Data delay found: 13
14:56:37:setup_element:INFO: Eye window for uplink 9 : XX_________________________________XXXXX
Data delay found: 18
14:56:37:setup_element:INFO: Eye window for uplink 10: _________________________________XXXXX__
Data delay found: 15
14:56:37:setup_element:INFO: Eye window for uplink 11: XXX_________________________________XXXX
Data delay found: 19
14:56:37:setup_element:INFO: Eye window for uplink 12: XXXX________XXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 7
14:56:37:setup_element:INFO: Eye window for uplink 13: __XXXXX_____XXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 9
14:56:37:setup_element:INFO: Eye window for uplink 14: ___XXXXX________________________________
Data delay found: 25
14:56:37:setup_element:INFO: Eye window for uplink 15: ______XXXXX_____________________________
Data delay found: 28
14:56:37:setup_element:INFO: Setting the data phase to 12 for uplink 0
14:56:37:setup_element:INFO: Setting the data phase to 9 for uplink 1
14:56:37:setup_element:INFO: Setting the data phase to 11 for uplink 2
14:56:37:setup_element:INFO: Setting the data phase to 7 for uplink 3
14:56:37:setup_element:INFO: Setting the data phase to 8 for uplink 4
14:56:37:setup_element:INFO: Setting the data phase to 5 for uplink 5
14:56:37:setup_element:INFO: Setting the data phase to 6 for uplink 6
14:56:37:setup_element:INFO: Setting the data phase to 3 for uplink 7
14:56:37:setup_element:INFO: Setting the data phase to 13 for uplink 8
14:56:37:setup_element:INFO: Setting the data phase to 18 for uplink 9
14:56:37:setup_element:INFO: Setting the data phase to 15 for uplink 10
14:56:37:setup_element:INFO: Setting the data phase to 19 for uplink 11
14:56:37:setup_element:INFO: Setting the data phase to 7 for uplink 12
14:56:37:setup_element:INFO: Setting the data phase to 9 for uplink 13
14:56:37:setup_element:INFO: Setting the data phase to 25 for uplink 14
14:56:37:setup_element:INFO: Setting the data phase to 28 for uplink 15
14:56:37:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 0
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 72
Eye Windows:
Uplink 0: ___________________________________________________________________________XXXXX
Uplink 1: ___________________________________________________________________________XXXXX
Uplink 2: __________________________________________________________________________XXXXXX
Uplink 3: __________________________________________________________________________XXXXXX
Uplink 4: ________________________________________________________________________________
Uplink 5: ________________________________________________________________________________
Uplink 6: _________________________________________________________________________XXXXXX_
Uplink 7: _________________________________________________________________________XXXXXX_
Uplink 8: __________________________________________________________________________XXXXX_
Uplink 9: __________________________________________________________________________XXXXX_
Uplink 10: ________________________________________________________________________XXXXXX__
Uplink 11: ________________________________________________________________________XXXXXX__
Uplink 12: __________________________________________________________________________XXXXX_
Uplink 13: __________________________________________________________________________XXXXX_
Uplink 14: __________________________________________________________________________XXXXXX
Uplink 15: __________________________________________________________________________XXXXXX
Data phase characteristics:
Uplink 0:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 1:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 2:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 3:
Optimal Phase: 7
Window Length: 36
Eye Window: __________________________XXXX__________
Uplink 4:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 5:
Optimal Phase: 5
Window Length: 35
Eye Window: _______________________XXXXX____________
Uplink 6:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 7:
Optimal Phase: 3
Window Length: 36
Eye Window: ______________________XXXX______________
Uplink 8:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 9:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 10:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 11:
Optimal Phase: 19
Window Length: 33
Eye Window: XXX_________________________________XXXX
Uplink 12:
Optimal Phase: 7
Window Length: 8
Eye Window: XXXX________XXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 13:
Optimal Phase: 9
Window Length: 5
Eye Window: __XXXXX_____XXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 14:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 15:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
]
14:56:37:setup_element:INFO: Beginning SMX ASICs map scan
14:56:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:56:37:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
14:56:37:master:INFO: Setting encoding mode EOS for groups [0], downlinks [0]
14:56:37:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [0]
14:56:37:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
14:56:37:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 7
14:56:37:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 6
14:56:37:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 14
14:56:37:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 15
14:56:37:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 5
14:56:37:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 4
14:56:37:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 12
14:56:38:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 13
14:56:38:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 3
14:56:38:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 2
14:56:38:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 10
14:56:38:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 11
14:56:38:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 1
14:56:38:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 0
14:56:38:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 8
14:56:38:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 9
14:56:40:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 0
Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 7), (1, 6)
ASIC address 0x1: (ASIC uplink, uplink): (0, 14), (1, 15)
ASIC address 0x2: (ASIC uplink, uplink): (0, 5), (1, 4)
ASIC address 0x3: (ASIC uplink, uplink): (0, 12), (1, 13)
ASIC address 0x4: (ASIC uplink, uplink): (0, 3), (1, 2)
ASIC address 0x5: (ASIC uplink, uplink): (0, 10), (1, 11)
ASIC address 0x6: (ASIC uplink, uplink): (0, 1), (1, 0)
ASIC address 0x7: (ASIC uplink, uplink): (0, 8), (1, 9)
Clock Phase Characteristic:
Optimal Phase: 35
Window Length: 72
Eye Windows:
Uplink 0: ___________________________________________________________________________XXXXX
Uplink 1: ___________________________________________________________________________XXXXX
Uplink 2: __________________________________________________________________________XXXXXX
Uplink 3: __________________________________________________________________________XXXXXX
Uplink 4: ________________________________________________________________________________
Uplink 5: ________________________________________________________________________________
Uplink 6: _________________________________________________________________________XXXXXX_
Uplink 7: _________________________________________________________________________XXXXXX_
Uplink 8: __________________________________________________________________________XXXXX_
Uplink 9: __________________________________________________________________________XXXXX_
Uplink 10: ________________________________________________________________________XXXXXX__
Uplink 11: ________________________________________________________________________XXXXXX__
Uplink 12: __________________________________________________________________________XXXXX_
Uplink 13: __________________________________________________________________________XXXXX_
Uplink 14: __________________________________________________________________________XXXXXX
Uplink 15: __________________________________________________________________________XXXXXX
Data phase characteristics:
Uplink 0:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 1:
Optimal Phase: 9
Window Length: 35
Eye Window: ___________________________XXXXX________
Uplink 2:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 3:
Optimal Phase: 7
Window Length: 36
Eye Window: __________________________XXXX__________
Uplink 4:
Optimal Phase: 8
Window Length: 35
Eye Window: __________________________XXXXX_________
Uplink 5:
Optimal Phase: 5
Window Length: 35
Eye Window: _______________________XXXXX____________
Uplink 6:
Optimal Phase: 6
Window Length: 36
Eye Window: _________________________XXXX___________
Uplink 7:
Optimal Phase: 3
Window Length: 36
Eye Window: ______________________XXXX______________
Uplink 8:
Optimal Phase: 13
Window Length: 34
Eye Window: _______________________________XXXXXX___
Uplink 9:
Optimal Phase: 18
Window Length: 33
Eye Window: XX_________________________________XXXXX
Uplink 10:
Optimal Phase: 15
Window Length: 35
Eye Window: _________________________________XXXXX__
Uplink 11:
Optimal Phase: 19
Window Length: 33
Eye Window: XXX_________________________________XXXX
Uplink 12:
Optimal Phase: 7
Window Length: 8
Eye Window: XXXX________XXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 13:
Optimal Phase: 9
Window Length: 5
Eye Window: __XXXXX_____XXXXXXXXXXXXXXXXXXXXXXXXXXXX
Uplink 14:
Optimal Phase: 25
Window Length: 35
Eye Window: ___XXXXX________________________________
Uplink 15:
Optimal Phase: 28
Window Length: 35
Eye Window: ______XXXXX_____________________________
14:56:40:setup_element:INFO: Performing Elink synchronization
14:56:40:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:56:40:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [0]
14:56:40:master:INFO: Setting encoding mode EOS for groups [0], downlinks [0]
14:56:40:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [0]
14:56:40:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 0
14:56:40:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
14:56:40:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 0 | 0 | [7] | [(0, 7), (1, 6)]
1 | [0] | 0 | 0 | [14] | [(0, 14), (1, 15)]
2 | [0] | 0 | 0 | [5] | [(0, 5), (1, 4)]
3 | [0] | 0 | 0 | [12] | [(0, 12), (1, 13)]
4 | [0] | 0 | 0 | [3] | [(0, 3), (1, 2)]
5 | [0] | 0 | 0 | [10] | [(0, 10), (1, 11)]
6 | [0] | 0 | 0 | [1] | [(0, 1), (1, 0)]
7 | [0] | 0 | 0 | [8] | [(0, 8), (1, 9)]
FEB type: A FEB_A: 1 FEB_B: 0
14:56:41:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:56:41:febtest:INFO: 07-00 | XA-000-08-002-000-007-008-06 | 50.4 | 1159.7
14:56:41:febtest:INFO: 14-01 | XA-000-08-002-000-007-199-09 | 56.8 | 1153.7
14:56:42:febtest:INFO: 05-02 | XA-000-08-002-000-007-031-01 | 31.4 | 1236.2
14:56:42:febtest:INFO: 12-03 | XA-000-08-002-000-007-198-09 | 47.3 | 1189.2
14:56:42:febtest:INFO: 03-04 | XA-000-08-002-000-007-041-08 | 25.1 | 1253.7
14:56:42:febtest:INFO: 10-05 | XA-000-08-002-000-007-127-10 | 47.3 | 1189.2
14:56:43:febtest:INFO: 01-06 | XA-000-08-002-000-007-047-08 | 18.7 | 1282.9
14:56:43:febtest:INFO: 08-07 | XA-000-08-002-000-007-083-04 | 37.7 | 1212.7
14:56:43:ST3_smx:INFO: Configuring SMX FAST
14:56:45:ST3_smx:INFO: chip: 7-0 47.250730 C 1177.390875 mV
14:56:45:ST3_smx:INFO: Electrons
14:56:45:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:56:47:ST3_smx:INFO: ----> Checking Analog response
14:56:47:ST3_smx:INFO: ----> Checking broken channels
14:56:48:ST3_smx:INFO: Total # broken ch: 0
14:56:48:ST3_smx:INFO: List FAST: []
14:56:48:ST3_smx:INFO: List SLOW: []
14:56:48:ST3_smx:INFO: Holes
14:56:48:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:56:50:ST3_smx:INFO: ----> Checking Analog response
14:56:50:ST3_smx:INFO: ----> Checking broken channels
14:56:50:ST3_smx:INFO: Total # broken ch: 0
14:56:50:ST3_smx:INFO: List FAST: []
14:56:50:ST3_smx:INFO: List SLOW: []
14:56:50:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:56:50:febtest:INFO: 07-00 | XA-000-08-002-000-007-008-06 | 50.4 | 1171.5
14:56:51:febtest:INFO: 14-01 | XA-000-08-002-000-007-199-09 | 56.8 | 1153.7
14:56:51:febtest:INFO: 05-02 | XA-000-08-002-000-007-031-01 | 31.4 | 1242.0
14:56:51:febtest:INFO: 12-03 | XA-000-08-002-000-007-198-09 | 47.3 | 1183.3
14:56:51:febtest:INFO: 03-04 | XA-000-08-002-000-007-041-08 | 25.1 | 1259.6
14:56:51:febtest:INFO: 10-05 | XA-000-08-002-000-007-127-10 | 47.3 | 1189.2
14:56:52:febtest:INFO: 01-06 | XA-000-08-002-000-007-047-08 | 18.7 | 1282.9
14:56:52:febtest:INFO: 08-07 | XA-000-08-002-000-007-083-04 | 37.7 | 1206.9
14:56:52:ST3_smx:INFO: Configuring SMX FAST
14:56:55:ST3_smx:INFO: chip: 14-1 53.612520 C 1177.390875 mV
14:56:55:ST3_smx:INFO: Electrons
14:56:55:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:56:57:ST3_smx:INFO: ----> Checking Analog response
14:56:57:ST3_smx:INFO: ----> Checking broken channels
14:56:57:ST3_smx:INFO: Total # broken ch: 0
14:56:57:ST3_smx:INFO: List FAST: []
14:56:57:ST3_smx:INFO: List SLOW: []
14:56:57:ST3_smx:INFO: Holes
14:56:57:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:57:00:ST3_smx:INFO: ----> Checking Analog response
14:57:00:ST3_smx:INFO: ----> Checking broken channels
14:57:00:ST3_smx:INFO: Total # broken ch: 0
14:57:00:ST3_smx:INFO: List FAST: []
14:57:00:ST3_smx:INFO: List SLOW: []
14:57:00:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:57:00:febtest:INFO: 07-00 | XA-000-08-002-000-007-008-06 | 50.4 | 1171.5
14:57:00:febtest:INFO: 14-01 | XA-000-08-002-000-007-199-09 | 53.6 | 1171.5
14:57:01:febtest:INFO: 05-02 | XA-000-08-002-000-007-031-01 | 34.6 | 1242.0
14:57:01:febtest:INFO: 12-03 | XA-000-08-002-000-007-198-09 | 50.4 | 1189.2
14:57:01:febtest:INFO: 03-04 | XA-000-08-002-000-007-041-08 | 25.1 | 1259.6
14:57:01:febtest:INFO: 10-05 | XA-000-08-002-000-007-127-10 | 47.3 | 1189.2
14:57:02:febtest:INFO: 01-06 | XA-000-08-002-000-007-047-08 | 21.9 | 1282.9
14:57:02:febtest:INFO: 08-07 | XA-000-08-002-000-007-083-04 | 37.7 | 1212.7
14:57:02:ST3_smx:INFO: Configuring SMX FAST
14:57:05:ST3_smx:INFO: chip: 5-2 44.073563 C 1206.851500 mV
14:57:05:ST3_smx:INFO: Electrons
14:57:05:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:57:07:ST3_smx:INFO: ----> Checking Analog response
14:57:07:ST3_smx:INFO: ----> Checking broken channels
14:57:07:ST3_smx:INFO: Total # broken ch: 0
14:57:07:ST3_smx:INFO: List FAST: []
14:57:07:ST3_smx:INFO: List SLOW: []
14:57:07:ST3_smx:INFO: Holes
14:57:07:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:57:09:ST3_smx:INFO: ----> Checking Analog response
14:57:09:ST3_smx:INFO: ----> Checking broken channels
14:57:10:ST3_smx:INFO: Total # broken ch: 0
14:57:10:ST3_smx:INFO: List FAST: []
14:57:10:ST3_smx:INFO: List SLOW: []
14:57:10:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:57:10:febtest:INFO: 07-00 | XA-000-08-002-000-007-008-06 | 50.4 | 1177.4
14:57:10:febtest:INFO: 14-01 | XA-000-08-002-000-007-199-09 | 53.6 | 1177.4
14:57:10:febtest:INFO: 05-02 | XA-000-08-002-000-007-031-01 | 47.3 | 1206.9
14:57:11:febtest:INFO: 12-03 | XA-000-08-002-000-007-198-09 | 47.3 | 1189.2
14:57:11:febtest:INFO: 03-04 | XA-000-08-002-000-007-041-08 | 25.1 | 1253.7
14:57:11:febtest:INFO: 10-05 | XA-000-08-002-000-007-127-10 | 50.4 | 1189.2
14:57:11:febtest:INFO: 01-06 | XA-000-08-002-000-007-047-08 | 21.9 | 1288.7
14:57:11:febtest:INFO: 08-07 | XA-000-08-002-000-007-083-04 | 40.9 | 1212.7
14:57:12:ST3_smx:INFO: Configuring SMX FAST
14:57:14:ST3_smx:INFO: chip: 12-3 50.430383 C 1177.390875 mV
14:57:14:ST3_smx:INFO: Electrons
14:57:14:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:57:17:ST3_smx:INFO: ----> Checking Analog response
14:57:17:ST3_smx:INFO: ----> Checking broken channels
14:57:17:ST3_smx:INFO: Total # broken ch: 0
14:57:17:ST3_smx:INFO: List FAST: []
14:57:17:ST3_smx:INFO: List SLOW: []
14:57:17:ST3_smx:INFO: Holes
14:57:17:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:57:19:ST3_smx:INFO: ----> Checking Analog response
14:57:19:ST3_smx:INFO: ----> Checking broken channels
14:57:20:ST3_smx:INFO: Total # broken ch: 0
14:57:20:ST3_smx:INFO: List FAST: []
14:57:20:ST3_smx:INFO: List SLOW: []
14:57:20:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:57:20:febtest:INFO: 07-00 | XA-000-08-002-000-007-008-06 | 50.4 | 1177.4
14:57:20:febtest:INFO: 14-01 | XA-000-08-002-000-007-199-09 | 53.6 | 1177.4
14:57:20:febtest:INFO: 05-02 | XA-000-08-002-000-007-031-01 | 47.3 | 1206.9
14:57:21:febtest:INFO: 12-03 | XA-000-08-002-000-007-198-09 | 53.6 | 1171.5
14:57:21:febtest:INFO: 03-04 | XA-000-08-002-000-007-041-08 | 28.2 | 1259.6
14:57:21:febtest:INFO: 10-05 | XA-000-08-002-000-007-127-10 | 47.3 | 1189.2
14:57:21:febtest:INFO: 01-06 | XA-000-08-002-000-007-047-08 | 21.9 | 1288.7
14:57:21:febtest:INFO: 08-07 | XA-000-08-002-000-007-083-04 | 40.9 | 1212.7
14:57:22:ST3_smx:INFO: Configuring SMX FAST
14:57:24:ST3_smx:INFO: chip: 3-4 28.225000 C 1259.567515 mV
14:57:24:ST3_smx:INFO: Electrons
14:57:24:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:57:27:ST3_smx:INFO: ----> Checking Analog response
14:57:27:ST3_smx:INFO: ----> Checking broken channels
14:57:27:ST3_smx:INFO: Total # broken ch: 0
14:57:27:ST3_smx:INFO: List FAST: []
14:57:27:ST3_smx:INFO: List SLOW: []
14:57:27:ST3_smx:INFO: Holes
14:57:27:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:57:29:ST3_smx:INFO: ----> Checking Analog response
14:57:29:ST3_smx:INFO: ----> Checking broken channels
14:57:29:ST3_smx:INFO: Total # broken ch: 0
14:57:29:ST3_smx:INFO: List FAST: []
14:57:29:ST3_smx:INFO: List SLOW: []
14:57:29:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:57:30:febtest:INFO: 07-00 | XA-000-08-002-000-007-008-06 | 50.4 | 1177.4
14:57:30:febtest:INFO: 14-01 | XA-000-08-002-000-007-199-09 | 56.8 | 1177.4
14:57:30:febtest:INFO: 05-02 | XA-000-08-002-000-007-031-01 | 47.3 | 1206.9
14:57:30:febtest:INFO: 12-03 | XA-000-08-002-000-007-198-09 | 53.6 | 1171.5
14:57:30:febtest:INFO: 03-04 | XA-000-08-002-000-007-041-08 | 31.4 | 1253.7
14:57:31:febtest:INFO: 10-05 | XA-000-08-002-000-007-127-10 | 50.4 | 1195.1
14:57:31:febtest:INFO: 01-06 | XA-000-08-002-000-007-047-08 | 21.9 | 1288.7
14:57:31:febtest:INFO: 08-07 | XA-000-08-002-000-007-083-04 | 40.9 | 1212.7
14:57:32:ST3_smx:INFO: Configuring SMX FAST
14:57:34:ST3_smx:INFO: chip: 10-5 47.250730 C 1200.969315 mV
14:57:34:ST3_smx:INFO: Electrons
14:57:34:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:57:37:ST3_smx:INFO: ----> Checking Analog response
14:57:37:ST3_smx:INFO: ----> Checking broken channels
14:57:37:ST3_smx:INFO: Total # broken ch: 0
14:57:37:ST3_smx:INFO: List FAST: []
14:57:37:ST3_smx:INFO: List SLOW: []
14:57:37:ST3_smx:INFO: Holes
14:57:37:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:57:39:ST3_smx:INFO: ----> Checking Analog response
14:57:39:ST3_smx:INFO: ----> Checking broken channels
14:57:40:ST3_smx:INFO: Total # broken ch: 0
14:57:40:ST3_smx:INFO: List FAST: []
14:57:40:ST3_smx:INFO: List SLOW: []
14:57:40:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:57:40:febtest:INFO: 07-00 | XA-000-08-002-000-007-008-06 | 53.6 | 1177.4
14:57:40:febtest:INFO: 14-01 | XA-000-08-002-000-007-199-09 | 53.6 | 1177.4
14:57:40:febtest:INFO: 05-02 | XA-000-08-002-000-007-031-01 | 47.3 | 1206.9
14:57:40:febtest:INFO: 12-03 | XA-000-08-002-000-007-198-09 | 53.6 | 1171.5
14:57:41:febtest:INFO: 03-04 | XA-000-08-002-000-007-041-08 | 28.2 | 1259.6
14:57:41:febtest:INFO: 10-05 | XA-000-08-002-000-007-127-10 | 50.4 | 1195.1
14:57:41:febtest:INFO: 01-06 | XA-000-08-002-000-007-047-08 | 21.9 | 1288.7
14:57:41:febtest:INFO: 08-07 | XA-000-08-002-000-007-083-04 | 40.9 | 1212.7
14:57:42:ST3_smx:INFO: Configuring SMX FAST
14:57:44:ST3_smx:INFO: chip: 1-6 31.389742 C 1253.730060 mV
14:57:44:ST3_smx:INFO: Electrons
14:57:44:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:57:47:ST3_smx:INFO: ----> Checking Analog response
14:57:47:ST3_smx:INFO: ----> Checking broken channels
14:57:47:ST3_smx:INFO: Total # broken ch: 0
14:57:47:ST3_smx:INFO: List FAST: []
14:57:47:ST3_smx:INFO: List SLOW: []
14:57:47:ST3_smx:INFO: Holes
14:57:47:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:57:49:ST3_smx:INFO: ----> Checking Analog response
14:57:49:ST3_smx:INFO: ----> Checking broken channels
14:57:50:ST3_smx:INFO: Total # broken ch: 0
14:57:50:ST3_smx:INFO: List FAST: []
14:57:50:ST3_smx:INFO: List SLOW: []
14:57:50:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:57:50:febtest:INFO: 07-00 | XA-000-08-002-000-007-008-06 | 53.6 | 1177.4
14:57:50:febtest:INFO: 14-01 | XA-000-08-002-000-007-199-09 | 53.6 | 1177.4
14:57:50:febtest:INFO: 05-02 | XA-000-08-002-000-007-031-01 | 47.3 | 1212.7
14:57:50:febtest:INFO: 12-03 | XA-000-08-002-000-007-198-09 | 53.6 | 1171.5
14:57:51:febtest:INFO: 03-04 | XA-000-08-002-000-007-041-08 | 28.2 | 1253.7
14:57:51:febtest:INFO: 10-05 | XA-000-08-002-000-007-127-10 | 50.4 | 1195.1
14:57:51:febtest:INFO: 01-06 | XA-000-08-002-000-007-047-08 | 34.6 | 1247.9
14:57:51:febtest:INFO: 08-07 | XA-000-08-002-000-007-083-04 | 40.9 | 1212.7
14:57:52:ST3_smx:INFO: Configuring SMX FAST
14:57:54:ST3_smx:INFO: chip: 8-7 47.250730 C 1189.190035 mV
14:57:54:ST3_smx:INFO: Electrons
14:57:54:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:57:57:ST3_smx:INFO: ----> Checking Analog response
14:57:57:ST3_smx:INFO: ----> Checking broken channels
14:57:57:ST3_smx:INFO: Total # broken ch: 0
14:57:57:ST3_smx:INFO: List FAST: []
14:57:57:ST3_smx:INFO: List SLOW: []
14:57:57:ST3_smx:INFO: Holes
14:57:57:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
14:57:59:ST3_smx:INFO: ----> Checking Analog response
14:57:59:ST3_smx:INFO: ----> Checking broken channels
14:57:59:ST3_smx:INFO: Total # broken ch: 0
14:57:59:ST3_smx:INFO: List FAST: []
14:57:59:ST3_smx:INFO: List SLOW: []
14:57:59:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:58:00:febtest:INFO: 07-00 | XA-000-08-002-000-007-008-06 | 53.6 | 1177.4
14:58:00:febtest:INFO: 14-01 | XA-000-08-002-000-007-199-09 | 56.8 | 1177.4
14:58:00:febtest:INFO: 05-02 | XA-000-08-002-000-007-031-01 | 47.3 | 1212.7
14:58:00:febtest:INFO: 12-03 | XA-000-08-002-000-007-198-09 | 53.6 | 1177.4
14:58:00:febtest:INFO: 03-04 | XA-000-08-002-000-007-041-08 | 28.2 | 1259.6
14:58:01:febtest:INFO: 10-05 | XA-000-08-002-000-007-127-10 | 50.4 | 1201.0
14:58:01:febtest:INFO: 01-06 | XA-000-08-002-000-007-047-08 | 34.6 | 1247.9
14:58:01:febtest:INFO: 08-07 | XA-000-08-002-000-007-083-04 | 50.4 | 1189.2
############################################################
# S U M M A R Y #
############################################################
{'TEST_NAME': 'FEB-ASIC', 'TEST_DATE': '24_02_22-14_56_27', 'OPERATOR': 'Alois Alzheimer', 'PROJECT': 'KIT', 'SITE': 'KIT', 'SETUP': 'KIT_TEST_SETUP_1', 'ASIC_ID': 'XA-000-08-002-000-007-083-04', 'FUSED_ID': 6359364699116565812, 'HW_ADDR': 7, 'UPLINK': 8, 'VERS_NO': '', 'CABLE_SET_ID': '', 'IC_TEMP': '0', 'VDDM': '0', 'AUX': '0', 'CSABIAS': '0', 'VDDM_INT': '0', 'ADC_Chi2': 0.0, 'ADC_NDF': 0, 'ADC_P0': 0.0, 'ADC_P1': 0.006824, 'ADC_P2': -2.485e-06, 'ADC_P0err': 0.001, 'ADC_P1err': 0.001, 'ADC_P2err': 1e-05, 'ADC_VREF_P': 58, 'ADC_VREF_N': 30, 'ADC_VREF_T': 128, 'ADC_VREF_TR': 122, 'THR2_GLB': 30, 'LOOP__PLS': 100, 'CALIB_PLS': 250, 'SnsLoop': 5, 'IFED': 31, 'CSA_BIAS': 15, 'CSA_Chi2': 0.0, 'CSA_NDF': 0, 'CSA_P0': 0.0, 'CSA_P1': 0.0, 'CSA_P2': 0.0, 'CSA_P0err': 0.0, 'CSA_P1err': 0.0, 'CSA_P2err': 0.0, 'CONF_FAIL_REG': 0, 'N_BROKEN_DISC': 0, 'N_BROKEN_FAST': '[]', 'N_BROKEN_SLOW': '[]', 'P_BROKEN_DISC': 0, 'P_BROKEN_FAST': '[]', 'P_BROKEN_SLOW': '[]', 'ASIC_QA_category': '', 'N_BROKEN_CABLE': 0, 'LIST_OF_BROKEN_CABLES': 0, 'FEB_SN': '3000', 'FEB_TYPE': 8.2, 'FEB_UPLINKS': 2, 'FEB_A': 1, 'FEB_B': 0, 'ADDR_0': '', 'ADDR_1': '', 'ADDR_2': '', 'ADDR_3': '', 'ADDR_4': '', 'ADDR_5': '', 'ADDR_6': '', 'ADDR_7': '', 'SENSOR_ID': '', 'MODULE_NAME': '', 'MODULE_LADDER': '', 'MODULE_MODULE': '', 'MODULE_SIZE': '', 'MODULE_GRADE': '', 'MODULE_TYPE': '', 'VI_bInit': ['2.800', '1.5000', '2.200', '2.4490', '0.000', '0.0000', '6.999', '1.6580'], 'VI_aInit': ['2.800', '1.9910', '2.200', '0.3194', '0.000', '0.0000', '7.000', '1.6630'], 'VI_atEnd': ['2.800', '1.9910', '2.200', '0.3194', '0.000', '0.0000', '7.000', '1.6630'], 'AMP_CAL': 150, 'PlsLoop': 500, 'N_ANA_PRESENT': 'Analog response OK', 'N_DISC_FAIL_CH': 0, 'N_ANA_FAIL_CH': '0', 'P_ANA_PRESENT': 'Analog response OK', 'P_DISC_FAIL_CH': 0, 'P_ANA_FAIL_CH': '0'}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 24_02_22-14_56_27
OPERATOR : Alois Alzheimer
SITE : KIT
SETUP : KIT_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME :
FEB_SN : 3000
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['2.800', '1.5000', '2.200', '2.4490', '0.000', '0.0000', '6.999', '1.6580']
VI_after__Init : ['2.800', '1.9940', '2.200', '0.3198', '0.000', '0.0000', '7.000', '1.6630']
VI_at__the_End : ['2.800', '1.9940', '2.200', '0.3198', '0.000', '0.0000', '7.000', '1.6630']