14:04:54:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:04:54:ST3_Shared:INFO:	                       FEB-Microcable                       
14:04:54:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:04:55:febtest:INFO:	Testing FEB with SN 3006
14:04:57:smx_tester:INFO:	Scanning setup
14:04:57:elinks:INFO:	Disabling clock on downlink 0
14:04:57:elinks:INFO:	Disabling clock on downlink 1
14:04:57:elinks:INFO:	Disabling clock on downlink 2
14:04:57:elinks:INFO:	Disabling clock on downlink 3
14:04:57:elinks:INFO:	Disabling clock on downlink 4
14:04:58:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:04:58:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
14:04:58:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:04:58:elinks:INFO:	Disabling clock on downlink 0
14:04:58:elinks:INFO:	Disabling clock on downlink 1
14:04:58:elinks:INFO:	Disabling clock on downlink 2
14:04:58:elinks:INFO:	Disabling clock on downlink 3
14:04:58:elinks:INFO:	Disabling clock on downlink 4
14:04:58:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:04:58:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:04:58:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 0
14:04:58:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 1
14:04:58:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 2
14:04:58:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 3
14:04:58:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 6
14:04:58:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 7
14:04:58:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 8
14:04:58:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 9
14:04:58:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 10
14:04:58:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 11
14:04:58:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 12
14:04:58:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 13
14:04:58:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 14
14:04:58:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 15
14:04:58:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:04:58:elinks:INFO:	Disabling clock on downlink 0
14:04:58:elinks:INFO:	Disabling clock on downlink 1
14:04:58:elinks:INFO:	Disabling clock on downlink 2
14:04:58:elinks:INFO:	Disabling clock on downlink 3
14:04:58:elinks:INFO:	Disabling clock on downlink 4
14:04:58:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:04:58:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:04:58:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:04:58:elinks:INFO:	Disabling clock on downlink 0
14:04:58:elinks:INFO:	Disabling clock on downlink 1
14:04:58:elinks:INFO:	Disabling clock on downlink 2
14:04:58:elinks:INFO:	Disabling clock on downlink 3
14:04:58:elinks:INFO:	Disabling clock on downlink 4
14:04:58:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:04:58:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
14:04:58:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:04:58:elinks:INFO:	Disabling clock on downlink 0
14:04:58:elinks:INFO:	Disabling clock on downlink 1
14:04:58:elinks:INFO:	Disabling clock on downlink 2
14:04:58:elinks:INFO:	Disabling clock on downlink 3
14:04:58:elinks:INFO:	Disabling clock on downlink 4
14:04:58:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:04:58:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
14:04:58:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:04:58:setup_element:INFO:	Scanning clock phase
14:04:58:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:04:58:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:04:59:setup_element:INFO:	Clock phase scan results for group 0, downlink 1
14:04:59:setup_element:INFO:	Eye window for uplink 0 : _______________________________________________________________________XXXX_____
Clock Delay: 32
14:04:59:setup_element:INFO:	Eye window for uplink 1 : _______________________________________________________________________XXXX_____
Clock Delay: 32
14:04:59:setup_element:INFO:	Eye window for uplink 2 : _______________________________________________________________________XXXX_____
Clock Delay: 32
14:04:59:setup_element:INFO:	Eye window for uplink 3 : _______________________________________________________________________XXXX_____
Clock Delay: 32
14:04:59:setup_element:INFO:	Eye window for uplink 6 : _______________________________________________________________________XXXX_____
Clock Delay: 32
14:04:59:setup_element:INFO:	Eye window for uplink 7 : _______________________________________________________________________XXXX_____
Clock Delay: 32
14:04:59:setup_element:INFO:	Eye window for uplink 8 : _____________________________________________________________________XXXXX______
Clock Delay: 31
14:04:59:setup_element:INFO:	Eye window for uplink 9 : _____________________________________________________________________XXXXX______
Clock Delay: 31
14:04:59:setup_element:INFO:	Eye window for uplink 10: _____________________________________________________________________XXXXX______
Clock Delay: 31
14:04:59:setup_element:INFO:	Eye window for uplink 11: _____________________________________________________________________XXXXX______
Clock Delay: 31
14:04:59:setup_element:INFO:	Eye window for uplink 12: XXXXXXXXXXXXXXXXXXXXXXXXX_X_XXX_X_X_____________________________________________
Clock Delay: 57
14:04:59:setup_element:INFO:	Eye window for uplink 13: XXXXXXXXXXXXXXXXXXXXXXXXX_X_XXX_X_X_____________________________________________
Clock Delay: 57
14:04:59:setup_element:INFO:	Eye window for uplink 14: ______________________________________________________________________XXXX______
Clock Delay: 31
14:04:59:setup_element:INFO:	Eye window for uplink 15: ______________________________________________________________________XXXX______
Clock Delay: 31
14:04:59:setup_element:INFO:	Setting the clock phase to 51 for group 0, downlink 1
14:04:59:setup_element:INFO:	Scanning data phases
14:04:59:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:04:59:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:05:04:setup_element:INFO:	Data phase scan results for group 0, downlink 1
14:05:04:setup_element:INFO:	Eye window for uplink 0 : _____________________XXXXXXX____________
Data delay found: 4
14:05:04:setup_element:INFO:	Eye window for uplink 1 : __________________XXXXXX________________
Data delay found: 0
14:05:04:setup_element:INFO:	Eye window for uplink 2 : ___________________XXXXXX_______________
Data delay found: 1
14:05:04:setup_element:INFO:	Eye window for uplink 3 : _______________XXXXXX___________________
Data delay found: 37
14:05:04:setup_element:INFO:	Eye window for uplink 6 : ________XXXXXX__________________________
Data delay found: 30
14:05:04:setup_element:INFO:	Eye window for uplink 7 : ____XXXXXX______________________________
Data delay found: 26
14:05:04:setup_element:INFO:	Eye window for uplink 8 : X________________________________XXXXXXX
Data delay found: 16
14:05:04:setup_element:INFO:	Eye window for uplink 9 : XXXXX_________________________________XX
Data delay found: 21
14:05:04:setup_element:INFO:	Eye window for uplink 10: XXX________________________________XXXXX
Data delay found: 18
14:05:04:setup_element:INFO:	Eye window for uplink 11: XXXXXX________________________________XX
Data delay found: 21
14:05:04:setup_element:INFO:	Eye window for uplink 12: XXX___X__XX________X____XX___________XXX
Data delay found: 31
14:05:04:setup_element:INFO:	Eye window for uplink 13: _XXXXXX__XX________X____XX_____________X
Data delay found: 32
14:05:04:setup_element:INFO:	Eye window for uplink 14: XXXX___________________________________X
Data delay found: 21
14:05:04:setup_element:INFO:	Eye window for uplink 15: XXXXXXX_________________________________
Data delay found: 23
14:05:04:setup_element:INFO:	Setting the data phase to 4 for uplink 0
14:05:04:setup_element:INFO:	Setting the data phase to 0 for uplink 1
14:05:04:setup_element:INFO:	Setting the data phase to 1 for uplink 2
14:05:04:setup_element:INFO:	Setting the data phase to 37 for uplink 3
14:05:04:setup_element:INFO:	Setting the data phase to 30 for uplink 6
14:05:04:setup_element:INFO:	Setting the data phase to 26 for uplink 7
14:05:04:setup_element:INFO:	Setting the data phase to 16 for uplink 8
14:05:04:setup_element:INFO:	Setting the data phase to 21 for uplink 9
14:05:04:setup_element:INFO:	Setting the data phase to 18 for uplink 10
14:05:04:setup_element:INFO:	Setting the data phase to 21 for uplink 11
14:05:04:setup_element:INFO:	Setting the data phase to 31 for uplink 12
14:05:04:setup_element:INFO:	Setting the data phase to 32 for uplink 13
14:05:04:setup_element:INFO:	Setting the data phase to 21 for uplink 14
14:05:04:setup_element:INFO:	Setting the data phase to 23 for uplink 15
14:05:04:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 1
  Uplinks: [0, 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 51
    Window Length: 34
    Eye Windows:
      Uplink  0: _______________________________________________________________________XXXX_____
      Uplink  1: _______________________________________________________________________XXXX_____
      Uplink  2: _______________________________________________________________________XXXX_____
      Uplink  3: _______________________________________________________________________XXXX_____
      Uplink  6: _______________________________________________________________________XXXX_____
      Uplink  7: _______________________________________________________________________XXXX_____
      Uplink  8: _____________________________________________________________________XXXXX______
      Uplink  9: _____________________________________________________________________XXXXX______
      Uplink 10: _____________________________________________________________________XXXXX______
      Uplink 11: _____________________________________________________________________XXXXX______
      Uplink 12: XXXXXXXXXXXXXXXXXXXXXXXXX_X_XXX_X_X_____________________________________________
      Uplink 13: XXXXXXXXXXXXXXXXXXXXXXXXX_X_XXX_X_X_____________________________________________
      Uplink 14: ______________________________________________________________________XXXX______
      Uplink 15: ______________________________________________________________________XXXX______
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 4
      Window Length: 33
      Eye Window: _____________________XXXXXXX____________
    Uplink 1:
      Optimal Phase: 0
      Window Length: 34
      Eye Window: __________________XXXXXX________________
    Uplink 2:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 3:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 6:
      Optimal Phase: 30
      Window Length: 34
      Eye Window: ________XXXXXX__________________________
    Uplink 7:
      Optimal Phase: 26
      Window Length: 34
      Eye Window: ____XXXXXX______________________________
    Uplink 8:
      Optimal Phase: 16
      Window Length: 32
      Eye Window: X________________________________XXXXXXX
    Uplink 9:
      Optimal Phase: 21
      Window Length: 33
      Eye Window: XXXXX_________________________________XX
    Uplink 10:
      Optimal Phase: 18
      Window Length: 32
      Eye Window: XXX________________________________XXXXX
    Uplink 11:
      Optimal Phase: 21
      Window Length: 32
      Eye Window: XXXXXX________________________________XX
    Uplink 12:
      Optimal Phase: 31
      Window Length: 11
      Eye Window: XXX___X__XX________X____XX___________XXX
    Uplink 13:
      Optimal Phase: 32
      Window Length: 13
      Eye Window: _XXXXXX__XX________X____XX_____________X
    Uplink 14:
      Optimal Phase: 21
      Window Length: 35
      Eye Window: XXXX___________________________________X
    Uplink 15:
      Optimal Phase: 23
      Window Length: 33
      Eye Window: XXXXXXX_________________________________
]
14:05:04:setup_element:INFO:	Beginning SMX ASICs map scan
14:05:04:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:05:04:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:05:04:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
14:05:04:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
14:05:04:uplink:INFO:	Setting uplinks mask [0, 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
14:05:04:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 1
14:05:04:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 0
14:05:04:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 8
14:05:04:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 9
14:05:04:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 3
14:05:04:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 2
14:05:05:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 10
14:05:05:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 11
14:05:05:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 12
14:05:05:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 13
14:05:05:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 7
14:05:05:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 6
14:05:05:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 14
14:05:05:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 15
14:05:07:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 1
  Uplinks: [0, 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
  Clock Phase Characteristic:
    Optimal Phase: 51
    Window Length: 34
    Eye Windows:
      Uplink  0: _______________________________________________________________________XXXX_____
      Uplink  1: _______________________________________________________________________XXXX_____
      Uplink  2: _______________________________________________________________________XXXX_____
      Uplink  3: _______________________________________________________________________XXXX_____
      Uplink  6: _______________________________________________________________________XXXX_____
      Uplink  7: _______________________________________________________________________XXXX_____
      Uplink  8: _____________________________________________________________________XXXXX______
      Uplink  9: _____________________________________________________________________XXXXX______
      Uplink 10: _____________________________________________________________________XXXXX______
      Uplink 11: _____________________________________________________________________XXXXX______
      Uplink 12: XXXXXXXXXXXXXXXXXXXXXXXXX_X_XXX_X_X_____________________________________________
      Uplink 13: XXXXXXXXXXXXXXXXXXXXXXXXX_X_XXX_X_X_____________________________________________
      Uplink 14: ______________________________________________________________________XXXX______
      Uplink 15: ______________________________________________________________________XXXX______
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 4
      Window Length: 33
      Eye Window: _____________________XXXXXXX____________
    Uplink 1:
      Optimal Phase: 0
      Window Length: 34
      Eye Window: __________________XXXXXX________________
    Uplink 2:
      Optimal Phase: 1
      Window Length: 34
      Eye Window: ___________________XXXXXX_______________
    Uplink 3:
      Optimal Phase: 37
      Window Length: 34
      Eye Window: _______________XXXXXX___________________
    Uplink 6:
      Optimal Phase: 30
      Window Length: 34
      Eye Window: ________XXXXXX__________________________
    Uplink 7:
      Optimal Phase: 26
      Window Length: 34
      Eye Window: ____XXXXXX______________________________
    Uplink 8:
      Optimal Phase: 16
      Window Length: 32
      Eye Window: X________________________________XXXXXXX
    Uplink 9:
      Optimal Phase: 21
      Window Length: 33
      Eye Window: XXXXX_________________________________XX
    Uplink 10:
      Optimal Phase: 18
      Window Length: 32
      Eye Window: XXX________________________________XXXXX
    Uplink 11:
      Optimal Phase: 21
      Window Length: 32
      Eye Window: XXXXXX________________________________XX
    Uplink 12:
      Optimal Phase: 31
      Window Length: 11
      Eye Window: XXX___X__XX________X____XX___________XXX
    Uplink 13:
      Optimal Phase: 32
      Window Length: 13
      Eye Window: _XXXXXX__XX________X____XX_____________X
    Uplink 14:
      Optimal Phase: 21
      Window Length: 35
      Eye Window: XXXX___________________________________X
    Uplink 15:
      Optimal Phase: 23
      Window Length: 33
      Eye Window: XXXXXXX_________________________________

14:05:07:setup_element:INFO:	Performing Elink synchronization
14:05:07:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:05:07:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:05:07:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
14:05:07:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
14:05:07:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 1
14:05:07:uplink:INFO:	Enabling uplinks [0, 1, 2, 3, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
14:05:07:ST3_emu:INFO:	Number of chips: 7
addr  |  upli  |  dwnli  |  grp |  uplinks | uplinks_map
   0  |   [0]   |  1  |  0  |     [1]      |   [(0, 1), (1, 0)] 
   1  |   [0]   |  1  |  0  |     [8]      |   [(0, 8), (1, 9)] 
   2  |   [0]   |  1  |  0  |     [3]      |   [(0, 3), (1, 2)] 
   3  |   [0]   |  1  |  0  |     [10]     |  [(0, 10), (1, 11)]
   5  |   [0]   |  1  |  0  |     [12]     |  [(0, 12), (1, 13)]
   6  |   [0]   |  1  |  0  |     [7]      |   [(0, 7), (1, 6)] 
   7  |   [0]   |  1  |  0  |     [14]     |  [(0, 14), (1, 15)]
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_0_1 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_0_1 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_0__upli_1
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_1_8 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_1_8 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_1__upli_8
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_2_3 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_2_3 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_2__upli_3
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_3_10 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_3_10 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_A__addr_3__upli_10
FEB type: A FEB_A: 1 FEB_B: 0
14:05:07:febtest:ERROR:	HW addres 5 != 4
14:05:13:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:05:13:febtest:INFO:	01-00 | XA-000-08-003-000-001-072-12 |  34.6 | 1247.9
14:05:14:febtest:INFO:	08-01 | XA-000-08-003-000-001-067-12 |  28.2 | 1271.2
14:05:14:febtest:INFO:	03-02 | XA-000-08-003-000-001-068-12 |  31.4 | 1253.7
14:05:14:febtest:INFO:	10-03 | XA-000-08-003-000-001-074-12 |  31.4 | 1271.2
14:05:14:febtest:INFO:	12-05 | XA-000-08-003-000-001-070-12 |  28.2 | 1277.1
14:05:14:febtest:INFO:	07-06 | XA-000-08-003-000-001-071-12 |  18.7 | 1288.7
14:05:15:febtest:INFO:	14-07 | XA-000-08-003-000-001-066-12 |   6.1 | 1363.8
14:05:15:ST3_smx:INFO:	Configuring SMX FAST
14:05:17:ST3_smx:INFO:	chip: 1-0 	 34.556970 C 	 1236.187875 mV
14:05:17:ST3_smx:INFO:		Electrons
14:05:17:ST3_smx:INFO:	# loops 0
14:05:19:ST3_smx:INFO:	# loops 1
14:05:22:ST3_smx:INFO:	# loops 2
14:05:23:ST3_smx:INFO:	Total # of broken channels: 0
14:05:23:ST3_smx:INFO:	List of broken channels: []
14:05:23:ST3_smx:INFO:	Total # of broken channels: 0
14:05:23:ST3_smx:INFO:	List of broken channels: []
14:05:24:ST3_smx:INFO:	Configuring SMX FAST
14:05:26:ST3_smx:INFO:	chip: 8-1 	 28.225000 C 	 1277.050060 mV
14:05:26:ST3_smx:INFO:		Electrons
14:05:26:ST3_smx:INFO:	# loops 0
14:05:29:ST3_smx:INFO:	# loops 1
14:05:31:ST3_smx:INFO:	# loops 2
14:05:33:ST3_smx:INFO:	Total # of broken channels: 0
14:05:33:ST3_smx:INFO:	List of broken channels: []
14:05:33:ST3_smx:INFO:	Total # of broken channels: 0
14:05:33:ST3_smx:INFO:	List of broken channels: []
14:05:34:ST3_smx:INFO:	Configuring SMX FAST
14:05:37:ST3_smx:INFO:	chip: 3-2 	 37.726682 C 	 1242.040240 mV
14:05:37:ST3_smx:INFO:		Electrons
14:05:37:ST3_smx:INFO:	# loops 0
14:05:39:ST3_smx:INFO:	# loops 1
14:05:41:ST3_smx:INFO:	# loops 2
14:05:43:ST3_smx:INFO:	Total # of broken channels: 0
14:05:43:ST3_smx:INFO:	List of broken channels: []
14:05:43:ST3_smx:INFO:	Total # of broken channels: 0
14:05:43:ST3_smx:INFO:	List of broken channels: []
14:05:44:ST3_smx:INFO:	Configuring SMX FAST
14:05:46:ST3_smx:INFO:	chip: 10-3 	 25.062742 C 	 1288.680240 mV
14:05:46:ST3_smx:INFO:		Electrons
14:05:46:ST3_smx:INFO:	# loops 0
14:05:48:ST3_smx:INFO:	# loops 1
14:05:50:ST3_smx:INFO:	# loops 2
14:05:52:ST3_smx:INFO:	Total # of broken channels: 0
14:05:52:ST3_smx:INFO:	List of broken channels: []
14:05:52:ST3_smx:INFO:	Total # of broken channels: 0
14:05:52:ST3_smx:INFO:	List of broken channels: []
Traceback (most recent call last):
  File "febtest.py", line 442, in DoFEB_MicrocableTest
    self.EMU.mysmx[i].MicroCableTest()
  File "/home/cbm/ST3_v2.29.16/lib/ST3_smx.py", line 623, in MicroCableTest
    self.smx.write(130,  3,  1) # reg  3,  shaper current Typ: 31, Max: 63
  File "/home/cbm/ST3_BASE/smx_software_FEB8_2_20MHz/python/smx_tester/smx.py", line 51, in write
    return self.ack_monitor.check_write()
  File "/home/cbm/ST3_BASE/smx_software_FEB8_2_20MHz/python/hctsp/ack_monitor.py", line 63, in check_write
    return self._check(self._check_write, timeout)
  File "/home/cbm/ST3_BASE/smx_software_FEB8_2_20MHz/python/hctsp/ack_monitor.py", line 55, in _check
    return check_function()
  File "/home/cbm/ST3_BASE/smx_software_FEB8_2_20MHz/python/hctsp/ack_monitor.py", line 69, in _check_write
    frame = self._parse_frame(frame)
  File "/home/cbm/ST3_BASE/smx_software_FEB8_2_20MHz/python/hctsp/ack_monitor.py", line 116, in _parse_frame
    raise AckMissed()
hctsp.ack_monitor.AckMissed: At least one Ack frame missed