09:02:15:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:02:15:ST3_Shared:INFO:	                         FEB-Sensor                         
09:02:15:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:02:16:ST3_ModuleSelector:INFO:	L5UL101016 M5UL1B3010163A2 124 B

09:02:16:ST3_ModuleSelector:INFO:	28214

09:02:17:febtest:INFO:	Testing FEB with SN 3029
09:02:19:smx_tester:INFO:	Scanning setup
09:02:19:elinks:INFO:	Disabling clock on downlink 0
09:02:19:elinks:INFO:	Disabling clock on downlink 1
09:02:19:elinks:INFO:	Disabling clock on downlink 2
09:02:19:elinks:INFO:	Disabling clock on downlink 3
09:02:20:elinks:INFO:	Disabling clock on downlink 4
09:02:20:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:02:20:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
09:02:20:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:02:20:elinks:INFO:	Disabling clock on downlink 0
09:02:20:elinks:INFO:	Disabling clock on downlink 1
09:02:20:elinks:INFO:	Disabling clock on downlink 2
09:02:20:elinks:INFO:	Disabling clock on downlink 3
09:02:20:elinks:INFO:	Disabling clock on downlink 4
09:02:20:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:02:20:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
09:02:20:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 0
09:02:20:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 1
09:02:20:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 2
09:02:20:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 3
09:02:20:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 4
09:02:20:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 5
09:02:20:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 6
09:02:20:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 7
09:02:20:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 8
09:02:20:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 9
09:02:20:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 10
09:02:20:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 11
09:02:20:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 12
09:02:20:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 13
09:02:20:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 14
09:02:20:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 15
09:02:20:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:02:20:elinks:INFO:	Disabling clock on downlink 0
09:02:20:elinks:INFO:	Disabling clock on downlink 1
09:02:20:elinks:INFO:	Disabling clock on downlink 2
09:02:20:elinks:INFO:	Disabling clock on downlink 3
09:02:20:elinks:INFO:	Disabling clock on downlink 4
09:02:20:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:02:20:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:02:20:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:02:20:elinks:INFO:	Disabling clock on downlink 0
09:02:20:elinks:INFO:	Disabling clock on downlink 1
09:02:20:elinks:INFO:	Disabling clock on downlink 2
09:02:20:elinks:INFO:	Disabling clock on downlink 3
09:02:20:elinks:INFO:	Disabling clock on downlink 4
09:02:20:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:02:20:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
09:02:20:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:02:20:elinks:INFO:	Disabling clock on downlink 0
09:02:20:elinks:INFO:	Disabling clock on downlink 1
09:02:20:elinks:INFO:	Disabling clock on downlink 2
09:02:20:elinks:INFO:	Disabling clock on downlink 3
09:02:20:elinks:INFO:	Disabling clock on downlink 4
09:02:20:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:02:20:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
09:02:20:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:02:20:setup_element:INFO:	Scanning clock phase
09:02:20:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
09:02:20:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
09:02:20:setup_element:INFO:	Clock phase scan results for group 0, downlink 1
09:02:20:setup_element:INFO:	Eye window for uplink 0 : ___________________________________________________________________________XXXXX
Clock Delay: 37
09:02:21:setup_element:INFO:	Eye window for uplink 1 : ___________________________________________________________________________XXXXX
Clock Delay: 37
09:02:21:setup_element:INFO:	Eye window for uplink 2 : __________________________________________________________________________XXXXX_
Clock Delay: 36
09:02:21:setup_element:INFO:	Eye window for uplink 3 : __________________________________________________________________________XXXXX_
Clock Delay: 36
09:02:21:setup_element:INFO:	Eye window for uplink 4 : __________________________________________________________________________XXXXX_
Clock Delay: 36
09:02:21:setup_element:INFO:	Eye window for uplink 5 : __________________________________________________________________________XXXXX_
Clock Delay: 36
09:02:21:setup_element:INFO:	Eye window for uplink 6 : ____________________________________________________________________________XXXX
Clock Delay: 37
09:02:21:setup_element:INFO:	Eye window for uplink 7 : ____________________________________________________________________________XXXX
Clock Delay: 37
09:02:21:setup_element:INFO:	Eye window for uplink 8 : ________________________________________________________________________________
Clock Delay: 40
09:02:21:setup_element:INFO:	Eye window for uplink 9 : ________________________________________________________________________________
Clock Delay: 40
09:02:21:setup_element:INFO:	Eye window for uplink 10: _________________________________________________________________________XXXXX__
Clock Delay: 35
09:02:21:setup_element:INFO:	Eye window for uplink 11: _________________________________________________________________________XXXXX__
Clock Delay: 35
09:02:21:setup_element:INFO:	Eye window for uplink 12: _________________________________________________________________________XXXXX__
Clock Delay: 35
09:02:21:setup_element:INFO:	Eye window for uplink 13: _________________________________________________________________________XXXXX__
Clock Delay: 35
09:02:21:setup_element:INFO:	Eye window for uplink 14: ________________________________________________________________________XXXXXX__
Clock Delay: 34
09:02:21:setup_element:INFO:	Eye window for uplink 15: ________________________________________________________________________XXXXXX__
Clock Delay: 34
09:02:21:setup_element:INFO:	Setting the clock phase to 35 for group 0, downlink 1
09:02:21:setup_element:INFO:	Scanning data phases
09:02:21:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
09:02:21:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
09:02:26:setup_element:INFO:	Data phase scan results for group 0, downlink 1
09:02:26:setup_element:INFO:	Eye window for uplink 0 : ________XXXX____________________________
Data delay found: 29
09:02:26:setup_element:INFO:	Eye window for uplink 1 : ___XXXXX________________________________
Data delay found: 25
09:02:26:setup_element:INFO:	Eye window for uplink 2 : ____XXXXX_______________________________
Data delay found: 26
09:02:26:setup_element:INFO:	Eye window for uplink 3 : _XXXX__________________________________X
Data delay found: 21
09:02:26:setup_element:INFO:	Eye window for uplink 4 : XXXX__________________________________XX
Data delay found: 20
09:02:26:setup_element:INFO:	Eye window for uplink 5 : ___________________________________XXXX_
Data delay found: 16
09:02:26:setup_element:INFO:	Eye window for uplink 6 : XX__________________________________XXXX
Data delay found: 18
09:02:26:setup_element:INFO:	Eye window for uplink 7 : ________________________________XXXX____
Data delay found: 13
09:02:26:setup_element:INFO:	Eye window for uplink 8 : ____________________XXXXXX______________
Data delay found: 2
09:02:26:setup_element:INFO:	Eye window for uplink 9 : _________________________XXXXXX_________
Data delay found: 7
09:02:26:setup_element:INFO:	Eye window for uplink 10: ____________________XXXXXX______________
Data delay found: 2
09:02:26:setup_element:INFO:	Eye window for uplink 11: ________________________XXXXXX__________
Data delay found: 6
09:02:26:setup_element:INFO:	Eye window for uplink 12: _____________________XXXX_______________
Data delay found: 2
09:02:26:setup_element:INFO:	Eye window for uplink 13: _________________________XXXX___________
Data delay found: 6
09:02:26:setup_element:INFO:	Eye window for uplink 14: _____________________XXXXX______________
Data delay found: 3
09:02:26:setup_element:INFO:	Eye window for uplink 15: _______________________XXXXX____________
Data delay found: 5
09:02:26:setup_element:INFO:	Setting the data phase to 29 for uplink 0
09:02:26:setup_element:INFO:	Setting the data phase to 25 for uplink 1
09:02:26:setup_element:INFO:	Setting the data phase to 26 for uplink 2
09:02:26:setup_element:INFO:	Setting the data phase to 21 for uplink 3
09:02:26:setup_element:INFO:	Setting the data phase to 20 for uplink 4
09:02:26:setup_element:INFO:	Setting the data phase to 16 for uplink 5
09:02:26:setup_element:INFO:	Setting the data phase to 18 for uplink 6
09:02:26:setup_element:INFO:	Setting the data phase to 13 for uplink 7
09:02:26:setup_element:INFO:	Setting the data phase to 2 for uplink 8
09:02:26:setup_element:INFO:	Setting the data phase to 7 for uplink 9
09:02:26:setup_element:INFO:	Setting the data phase to 2 for uplink 10
09:02:26:setup_element:INFO:	Setting the data phase to 6 for uplink 11
09:02:26:setup_element:INFO:	Setting the data phase to 2 for uplink 12
09:02:26:setup_element:INFO:	Setting the data phase to 6 for uplink 13
09:02:26:setup_element:INFO:	Setting the data phase to 3 for uplink 14
09:02:26:setup_element:INFO:	Setting the data phase to 5 for uplink 15
09:02:26:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 1
  Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 35
    Window Length: 72
    Eye Windows:
      Uplink  0: ___________________________________________________________________________XXXXX
      Uplink  1: ___________________________________________________________________________XXXXX
      Uplink  2: __________________________________________________________________________XXXXX_
      Uplink  3: __________________________________________________________________________XXXXX_
      Uplink  4: __________________________________________________________________________XXXXX_
      Uplink  5: __________________________________________________________________________XXXXX_
      Uplink  6: ____________________________________________________________________________XXXX
      Uplink  7: ____________________________________________________________________________XXXX
      Uplink  8: ________________________________________________________________________________
      Uplink  9: ________________________________________________________________________________
      Uplink 10: _________________________________________________________________________XXXXX__
      Uplink 11: _________________________________________________________________________XXXXX__
      Uplink 12: _________________________________________________________________________XXXXX__
      Uplink 13: _________________________________________________________________________XXXXX__
      Uplink 14: ________________________________________________________________________XXXXXX__
      Uplink 15: ________________________________________________________________________XXXXXX__
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 29
      Window Length: 36
      Eye Window: ________XXXX____________________________
    Uplink 1:
      Optimal Phase: 25
      Window Length: 35
      Eye Window: ___XXXXX________________________________
    Uplink 2:
      Optimal Phase: 26
      Window Length: 35
      Eye Window: ____XXXXX_______________________________
    Uplink 3:
      Optimal Phase: 21
      Window Length: 34
      Eye Window: _XXXX__________________________________X
    Uplink 4:
      Optimal Phase: 20
      Window Length: 34
      Eye Window: XXXX__________________________________XX
    Uplink 5:
      Optimal Phase: 16
      Window Length: 36
      Eye Window: ___________________________________XXXX_
    Uplink 6:
      Optimal Phase: 18
      Window Length: 34
      Eye Window: XX__________________________________XXXX
    Uplink 7:
      Optimal Phase: 13
      Window Length: 36
      Eye Window: ________________________________XXXX____
    Uplink 8:
      Optimal Phase: 2
      Window Length: 34
      Eye Window: ____________________XXXXXX______________
    Uplink 9:
      Optimal Phase: 7
      Window Length: 34
      Eye Window: _________________________XXXXXX_________
    Uplink 10:
      Optimal Phase: 2
      Window Length: 34
      Eye Window: ____________________XXXXXX______________
    Uplink 11:
      Optimal Phase: 6
      Window Length: 34
      Eye Window: ________________________XXXXXX__________
    Uplink 12:
      Optimal Phase: 2
      Window Length: 36
      Eye Window: _____________________XXXX_______________
    Uplink 13:
      Optimal Phase: 6
      Window Length: 36
      Eye Window: _________________________XXXX___________
    Uplink 14:
      Optimal Phase: 3
      Window Length: 35
      Eye Window: _____________________XXXXX______________
    Uplink 15:
      Optimal Phase: 5
      Window Length: 35
      Eye Window: _______________________XXXXX____________
]
09:02:26:setup_element:INFO:	Beginning SMX ASICs map scan
09:02:26:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
09:02:26:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
09:02:26:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
09:02:26:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
09:02:26:uplink:INFO:	Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
09:02:26:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 1
09:02:26:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 0
09:02:26:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 8
09:02:26:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 9
09:02:26:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 3
09:02:26:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 2
09:02:27:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 10
09:02:27:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 11
09:02:27:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 5
09:02:27:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 4
09:02:27:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 12
09:02:27:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 13
09:02:27:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 7
09:02:27:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 6
09:02:27:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 14
09:02:27:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 15
09:02:29:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 1
  Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
  Clock Phase Characteristic:
    Optimal Phase: 35
    Window Length: 72
    Eye Windows:
      Uplink  0: ___________________________________________________________________________XXXXX
      Uplink  1: ___________________________________________________________________________XXXXX
      Uplink  2: __________________________________________________________________________XXXXX_
      Uplink  3: __________________________________________________________________________XXXXX_
      Uplink  4: __________________________________________________________________________XXXXX_
      Uplink  5: __________________________________________________________________________XXXXX_
      Uplink  6: ____________________________________________________________________________XXXX
      Uplink  7: ____________________________________________________________________________XXXX
      Uplink  8: ________________________________________________________________________________
      Uplink  9: ________________________________________________________________________________
      Uplink 10: _________________________________________________________________________XXXXX__
      Uplink 11: _________________________________________________________________________XXXXX__
      Uplink 12: _________________________________________________________________________XXXXX__
      Uplink 13: _________________________________________________________________________XXXXX__
      Uplink 14: ________________________________________________________________________XXXXXX__
      Uplink 15: ________________________________________________________________________XXXXXX__
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 29
      Window Length: 36
      Eye Window: ________XXXX____________________________
    Uplink 1:
      Optimal Phase: 25
      Window Length: 35
      Eye Window: ___XXXXX________________________________
    Uplink 2:
      Optimal Phase: 26
      Window Length: 35
      Eye Window: ____XXXXX_______________________________
    Uplink 3:
      Optimal Phase: 21
      Window Length: 34
      Eye Window: _XXXX__________________________________X
    Uplink 4:
      Optimal Phase: 20
      Window Length: 34
      Eye Window: XXXX__________________________________XX
    Uplink 5:
      Optimal Phase: 16
      Window Length: 36
      Eye Window: ___________________________________XXXX_
    Uplink 6:
      Optimal Phase: 18
      Window Length: 34
      Eye Window: XX__________________________________XXXX
    Uplink 7:
      Optimal Phase: 13
      Window Length: 36
      Eye Window: ________________________________XXXX____
    Uplink 8:
      Optimal Phase: 2
      Window Length: 34
      Eye Window: ____________________XXXXXX______________
    Uplink 9:
      Optimal Phase: 7
      Window Length: 34
      Eye Window: _________________________XXXXXX_________
    Uplink 10:
      Optimal Phase: 2
      Window Length: 34
      Eye Window: ____________________XXXXXX______________
    Uplink 11:
      Optimal Phase: 6
      Window Length: 34
      Eye Window: ________________________XXXXXX__________
    Uplink 12:
      Optimal Phase: 2
      Window Length: 36
      Eye Window: _____________________XXXX_______________
    Uplink 13:
      Optimal Phase: 6
      Window Length: 36
      Eye Window: _________________________XXXX___________
    Uplink 14:
      Optimal Phase: 3
      Window Length: 35
      Eye Window: _____________________XXXXX______________
    Uplink 15:
      Optimal Phase: 5
      Window Length: 35
      Eye Window: _______________________XXXXX____________

09:02:29:setup_element:INFO:	Performing Elink synchronization
09:02:29:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
09:02:29:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
09:02:29:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
09:02:29:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
09:02:29:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 1
09:02:29:uplink:INFO:	Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
09:02:29:ST3_emu:INFO:	Number of chips: 8
addr  |  upli  |  dwnli  |  grp |  uplinks | uplinks_map
   0  |   [0]   |  1  |  0  |     [1]      |   [(0, 1), (1, 0)] 
   1  |   [0]   |  1  |  0  |     [8]      |   [(0, 8), (1, 9)] 
   2  |   [0]   |  1  |  0  |     [3]      |   [(0, 3), (1, 2)] 
   3  |   [0]   |  1  |  0  |     [10]     |  [(0, 10), (1, 11)]
   4  |   [0]   |  1  |  0  |     [5]      |   [(0, 5), (1, 4)] 
   5  |   [0]   |  1  |  0  |     [12]     |  [(0, 12), (1, 13)]
   6  |   [0]   |  1  |  0  |     [7]      |   [(0, 7), (1, 6)] 
   7  |   [0]   |  1  |  0  |     [14]     |  [(0, 14), (1, 15)]
FEB type: A FEB_A: 1 FEB_B: 0
09:02:30:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:02:30:febtest:INFO:	01-00 | XA-000-08-003-000-000-032-10 |  63.2 | 1112.1
09:02:30:febtest:INFO:	08-01 | XA-000-08-003-000-000-035-10 |  50.4 | 1165.6
09:02:31:febtest:INFO:	03-02 | XA-000-08-003-000-000-030-03 |  47.3 | 1165.6
09:02:31:febtest:INFO:	10-03 | XA-000-08-003-000-000-036-10 |  44.1 | 1183.3
09:02:31:febtest:INFO:	05-04 | XA-000-08-003-000-000-029-03 |  47.3 | 1165.6
09:02:31:febtest:INFO:	12-05 | XA-000-08-003-000-000-037-10 |  50.4 | 1147.8
09:02:31:febtest:INFO:	07-06 | XA-000-08-003-000-000-034-10 |  44.1 | 1171.5
09:02:32:febtest:INFO:	14-07 | XA-000-08-003-000-000-038-10 |  47.3 | 1177.4
09:02:32:ST3_smx:INFO:	Configuring SMX FAST
09:02:35:ST3_smx:INFO:	chip: 1-0 	 69.560482 C 	 1094.240115 mV
09:02:35:ST3_smx:INFO:		Electrons
09:02:35:ST3_smx:INFO:	# loops 0
09:02:37:ST3_smx:INFO:	# loops 1
09:02:38:ST3_smx:INFO:	# loops 2
09:02:40:ST3_smx:INFO:	Total # of broken channels: 0
09:02:40:ST3_smx:INFO:	List of broken channels: []
09:02:40:ST3_smx:INFO:	Total # of broken channels: 0
09:02:40:ST3_smx:INFO:	List of broken channels: []
09:02:41:ST3_smx:INFO:	Configuring SMX FAST
09:02:43:ST3_smx:INFO:	chip: 8-1 	 56.797143 C 	 1141.874115 mV
09:02:43:ST3_smx:INFO:		Electrons
09:02:43:ST3_smx:INFO:	# loops 0
09:02:45:ST3_smx:INFO:	# loops 1
09:02:47:ST3_smx:INFO:	# loops 2
09:02:49:ST3_smx:INFO:	Total # of broken channels: 0
09:02:49:ST3_smx:INFO:	List of broken channels: []
09:02:49:ST3_smx:INFO:	Total # of broken channels: 0
09:02:49:ST3_smx:INFO:	List of broken channels: []
09:02:50:ST3_smx:INFO:	Configuring SMX FAST
09:02:52:ST3_smx:INFO:	chip: 3-2 	 50.430383 C 	 1153.732915 mV
09:02:53:ST3_smx:INFO:		Electrons
09:02:53:ST3_smx:INFO:	# loops 0
09:02:55:ST3_smx:INFO:	# loops 1
09:02:57:ST3_smx:INFO:	# loops 2
09:02:59:ST3_smx:INFO:	Total # of broken channels: 0
09:02:59:ST3_smx:INFO:	List of broken channels: []
09:02:59:ST3_smx:INFO:	Total # of broken channels: 0
09:02:59:ST3_smx:INFO:	List of broken channels: []
09:02:59:ST3_smx:INFO:	Configuring SMX FAST
09:03:02:ST3_smx:INFO:	chip: 10-3 	 50.430383 C 	 1159.654860 mV
09:03:02:ST3_smx:INFO:		Electrons
09:03:02:ST3_smx:INFO:	# loops 0
09:03:04:ST3_smx:INFO:	# loops 1
09:03:06:ST3_smx:INFO:	# loops 2
09:03:08:ST3_smx:INFO:	Total # of broken channels: 0
09:03:08:ST3_smx:INFO:	List of broken channels: []
09:03:08:ST3_smx:INFO:	Total # of broken channels: 0
09:03:08:ST3_smx:INFO:	List of broken channels: []
09:03:09:ST3_smx:INFO:	Configuring SMX FAST
09:03:11:ST3_smx:INFO:	chip: 5-4 	 59.984250 C 	 1124.048640 mV
09:03:11:ST3_smx:INFO:		Electrons
09:03:11:ST3_smx:INFO:	# loops 0
09:03:13:ST3_smx:INFO:	# loops 1
09:03:15:ST3_smx:INFO:	# loops 2
09:03:17:ST3_smx:INFO:	Total # of broken channels: 0
09:03:17:ST3_smx:INFO:	List of broken channels: []
09:03:17:ST3_smx:INFO:	Total # of broken channels: 0
09:03:17:ST3_smx:INFO:	List of broken channels: []
09:03:18:ST3_smx:INFO:	Configuring SMX FAST
09:03:20:ST3_smx:INFO:	chip: 12-5 	 53.612520 C 	 1147.806000 mV
09:03:20:ST3_smx:INFO:		Electrons
09:03:20:ST3_smx:INFO:	# loops 0
09:03:22:ST3_smx:INFO:	# loops 1
09:03:24:ST3_smx:INFO:	# loops 2
09:03:26:ST3_smx:INFO:	Total # of broken channels: 0
09:03:26:ST3_smx:INFO:	List of broken channels: []
09:03:26:ST3_smx:INFO:	Total # of broken channels: 0
09:03:26:ST3_smx:INFO:	List of broken channels: []
09:03:27:ST3_smx:INFO:	Configuring SMX FAST
09:03:29:ST3_smx:INFO:	chip: 7-6 	 50.430383 C 	 1153.732915 mV
09:03:29:ST3_smx:INFO:		Electrons
09:03:29:ST3_smx:INFO:	# loops 0
09:03:31:ST3_smx:INFO:	# loops 1
09:03:33:ST3_smx:INFO:	# loops 2
09:03:35:ST3_smx:INFO:	Total # of broken channels: 0
09:03:35:ST3_smx:INFO:	List of broken channels: []
09:03:35:ST3_smx:INFO:	Total # of broken channels: 0
09:03:35:ST3_smx:INFO:	List of broken channels: []
09:03:36:ST3_smx:INFO:	Configuring SMX FAST
09:03:38:ST3_smx:INFO:	chip: 14-7 	 50.430383 C 	 1171.483840 mV
09:03:38:ST3_smx:INFO:		Electrons
09:03:38:ST3_smx:INFO:	# loops 0
09:03:40:ST3_smx:INFO:	# loops 1
09:03:42:ST3_smx:INFO:	# loops 2
09:03:44:ST3_smx:INFO:	Total # of broken channels: 0
09:03:44:ST3_smx:INFO:	List of broken channels: []
09:03:44:ST3_smx:INFO:	Total # of broken channels: 0
09:03:44:ST3_smx:INFO:	List of broken channels: []
09:03:45:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:03:45:febtest:INFO:	01-00 | XA-000-08-003-000-000-032-10 |  72.8 | 1094.2
09:03:45:febtest:INFO:	08-01 | XA-000-08-003-000-000-035-10 |  56.8 | 1147.8
09:03:45:febtest:INFO:	03-02 | XA-000-08-003-000-000-030-03 |  53.6 | 1153.7
09:03:46:febtest:INFO:	10-03 | XA-000-08-003-000-000-036-10 |  53.6 | 1159.7
09:03:46:febtest:INFO:	05-04 | XA-000-08-003-000-000-029-03 |  60.0 | 1130.0
09:03:46:febtest:INFO:	12-05 | XA-000-08-003-000-000-037-10 |  56.8 | 1147.8
09:03:46:febtest:INFO:	07-06 | XA-000-08-003-000-000-034-10 |  53.6 | 1153.7
09:03:47:febtest:INFO:	14-07 | XA-000-08-003-000-000-038-10 |  53.6 | 1171.5
############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Sensor
TEST_DATE : 24_06_13-09_02_15
OPERATOR  : Benjamin; 
SITE      : KIT
SETUP     : KIT_TEST_SETUP_1
Set-ID    : 
---------------------------------------
MODULE_NAME : L5UL101016 M5UL1B3010163A2 124 B

FEB_SN : 3029
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 1
FEB_B : 0
---------------------------------------
SENSOR_ID:	28214

MODULE_NAME:	L5UL101016 M5UL1B3010163A2 124 B

MODULE_TYPE:	
MODULE_LADDER:	L5UL101016
MODULE_MODULE:	M5UL1B2010162A2
MODULE_SIZE:	62
MODULE_GRADE:	A
---------------------------------------
VI_before_Init : ['2.450', '1.7740', '1.850', '0.4201', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0170', '1.850', '0.5900', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '2.0030', '1.850', '0.3216', '0.000', '0.0000', '0.000', '0.0000']