09:33:10:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:33:10:ST3_Shared:INFO:	                         FEB-Sensor                         
09:33:10:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:33:12:ST3_ModuleSelector:INFO:	L6UL201035 M6UL2B1010351A2 42 A

09:33:12:ST3_ModuleSelector:INFO:	15292

09:33:12:febtest:INFO:	Testing FEB with SN 3037
09:33:15:smx_tester:INFO:	Scanning setup
09:33:15:elinks:INFO:	Disabling clock on downlink 0
09:33:15:elinks:INFO:	Disabling clock on downlink 1
09:33:15:elinks:INFO:	Disabling clock on downlink 2
09:33:15:elinks:INFO:	Disabling clock on downlink 3
09:33:15:elinks:INFO:	Disabling clock on downlink 4
09:33:15:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:33:15:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
09:33:15:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:33:15:elinks:INFO:	Disabling clock on downlink 0
09:33:15:elinks:INFO:	Disabling clock on downlink 1
09:33:15:elinks:INFO:	Disabling clock on downlink 2
09:33:15:elinks:INFO:	Disabling clock on downlink 3
09:33:15:elinks:INFO:	Disabling clock on downlink 4
09:33:15:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:33:15:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
09:33:15:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 0
09:33:15:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 1
09:33:15:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 2
09:33:15:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 3
09:33:15:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 4
09:33:15:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 5
09:33:15:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 6
09:33:15:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 7
09:33:15:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 8
09:33:15:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 9
09:33:15:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 10
09:33:15:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 11
09:33:15:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 12
09:33:15:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 13
09:33:15:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 14
09:33:15:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 15
09:33:15:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:33:15:elinks:INFO:	Disabling clock on downlink 0
09:33:15:elinks:INFO:	Disabling clock on downlink 1
09:33:15:elinks:INFO:	Disabling clock on downlink 2
09:33:15:elinks:INFO:	Disabling clock on downlink 3
09:33:15:elinks:INFO:	Disabling clock on downlink 4
09:33:15:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:33:15:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
09:33:15:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:33:15:elinks:INFO:	Disabling clock on downlink 0
09:33:15:elinks:INFO:	Disabling clock on downlink 1
09:33:15:elinks:INFO:	Disabling clock on downlink 2
09:33:15:elinks:INFO:	Disabling clock on downlink 3
09:33:15:elinks:INFO:	Disabling clock on downlink 4
09:33:15:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:33:15:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
09:33:15:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:33:15:elinks:INFO:	Disabling clock on downlink 0
09:33:15:elinks:INFO:	Disabling clock on downlink 1
09:33:15:elinks:INFO:	Disabling clock on downlink 2
09:33:15:elinks:INFO:	Disabling clock on downlink 3
09:33:15:elinks:INFO:	Disabling clock on downlink 4
09:33:15:setup_element:INFO:	Checking SOS, encoding_mode: SOS
09:33:15:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
09:33:15:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
09:33:15:setup_element:INFO:	Scanning clock phase
09:33:15:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
09:33:16:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
09:33:16:setup_element:INFO:	Clock phase scan results for group 0, downlink 1
09:33:16:setup_element:INFO:	Eye window for uplink 0 : XXXXXXXXXXXXXXXXXXXXXXX_X_______________________________________________XXXXXXXX
Clock Delay: 48
09:33:16:setup_element:INFO:	Eye window for uplink 1 : XXXXXXXXXXXXXXXXXXXXXXX_X_______________________________________________XXXXXXXX
Clock Delay: 48
09:33:16:setup_element:INFO:	Eye window for uplink 2 : XX______________________________________________________________________________
Clock Delay: 40
09:33:16:setup_element:INFO:	Eye window for uplink 3 : XX______________________________________________________________________________
Clock Delay: 40
09:33:16:setup_element:INFO:	Eye window for uplink 4 : XXXXXXXXXXXXXXXXXXXXX____________________________________________________XXXXXXX
Clock Delay: 46
09:33:16:setup_element:INFO:	Eye window for uplink 5 : XXXXXXXXXXXXXXXXXXXXX____________________________________________________XXXXXXX
Clock Delay: 46
09:33:16:setup_element:INFO:	Eye window for uplink 6 : XXXXXXXXXXXXXX________________________________________________________XXXXXXXXXX
Clock Delay: 41
09:33:16:setup_element:INFO:	Eye window for uplink 7 : XXXXXXXXXXXXXX________________________________________________________XXXXXXXXXX
Clock Delay: 41
09:33:16:setup_element:INFO:	Eye window for uplink 8 : XXXXXXXXXX______________________________________________________________________
Clock Delay: 44
09:33:16:setup_element:INFO:	Eye window for uplink 9 : XXXXXXXXXX______________________________________________________________________
Clock Delay: 44
09:33:16:setup_element:INFO:	Eye window for uplink 10: X_______________________________________________________________________________
Clock Delay: 40
09:33:16:setup_element:INFO:	Eye window for uplink 11: X_______________________________________________________________________________
Clock Delay: 40
09:33:16:setup_element:INFO:	Eye window for uplink 12: XXXXXXXXXX______________________________________________________________________
Clock Delay: 44
09:33:16:setup_element:INFO:	Eye window for uplink 13: XXXXXXXXXX______________________________________________________________________
Clock Delay: 44
09:33:16:setup_element:INFO:	Eye window for uplink 14: XXXXXXXXXXX_X__________________________________________________________XXXXXXXXX
Clock Delay: 41
09:33:16:setup_element:INFO:	Eye window for uplink 15: XXXXXXXXXXX_X__________________________________________________________XXXXXXXXX
Clock Delay: 41
09:33:16:setup_element:INFO:	Setting the clock phase to 47 for group 0, downlink 1
09:33:16:setup_element:INFO:	Scanning data phases
09:33:16:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
09:33:16:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
09:33:21:setup_element:INFO:	Data phase scan results for group 0, downlink 1
09:33:21:setup_element:INFO:	Eye window for uplink 0 : ____________XXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 5
09:33:21:setup_element:INFO:	Eye window for uplink 1 : ____________XXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 5
09:33:21:setup_element:INFO:	Eye window for uplink 2 : _______XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 3
09:33:21:setup_element:INFO:	Eye window for uplink 3 : _______XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 3
09:33:21:setup_element:INFO:	Eye window for uplink 4 : __________________________XXXXXXXXXXXXXX
Data delay found: 12
09:33:21:setup_element:INFO:	Eye window for uplink 5 : ___________________X__XXXXXXXXXXXXXXXXXX
Data delay found: 9
09:33:21:setup_element:INFO:	Eye window for uplink 6 : ______________XXXXXXXXXX________________
Data delay found: 38
09:33:21:setup_element:INFO:	Eye window for uplink 7 : ________XXXXXXXXXX______________________
Data delay found: 32
09:33:21:setup_element:INFO:	Eye window for uplink 8 : _____XXXXXXXX___________________________
Data delay found: 28
09:33:21:setup_element:INFO:	Eye window for uplink 9 : __________XXXXXXX_______________________
Data delay found: 33
09:33:21:setup_element:INFO:	Eye window for uplink 10: ______XXXXXXXX__________________________
Data delay found: 29
09:33:21:setup_element:INFO:	Eye window for uplink 11: _________XXXXXXXXX______________________
Data delay found: 33
09:33:21:setup_element:INFO:	Eye window for uplink 12: _______XXXXXXXXXX_______________________
Data delay found: 31
09:33:21:setup_element:INFO:	Eye window for uplink 13: __________XXXXXXXXXXX___________________
Data delay found: 35
09:33:21:setup_element:INFO:	Eye window for uplink 14: _____X_XXXXXXXXX________________________
Data delay found: 30
09:33:21:setup_element:INFO:	Eye window for uplink 15: _______XXXXXXXXXXXX_____________________
Data delay found: 32
09:33:21:setup_element:INFO:	Setting the data phase to 5 for uplink 0
09:33:21:setup_element:INFO:	Setting the data phase to 5 for uplink 1
09:33:21:setup_element:INFO:	Setting the data phase to 3 for uplink 2
09:33:21:setup_element:INFO:	Setting the data phase to 3 for uplink 3
09:33:21:setup_element:INFO:	Setting the data phase to 12 for uplink 4
09:33:21:setup_element:INFO:	Setting the data phase to 9 for uplink 5
09:33:21:setup_element:INFO:	Setting the data phase to 38 for uplink 6
09:33:21:setup_element:INFO:	Setting the data phase to 32 for uplink 7
09:33:21:setup_element:INFO:	Setting the data phase to 28 for uplink 8
09:33:21:setup_element:INFO:	Setting the data phase to 33 for uplink 9
09:33:21:setup_element:INFO:	Setting the data phase to 29 for uplink 10
09:33:21:setup_element:INFO:	Setting the data phase to 33 for uplink 11
09:33:21:setup_element:INFO:	Setting the data phase to 31 for uplink 12
09:33:21:setup_element:INFO:	Setting the data phase to 35 for uplink 13
09:33:21:setup_element:INFO:	Setting the data phase to 30 for uplink 14
09:33:21:setup_element:INFO:	Setting the data phase to 32 for uplink 15
09:33:21:ST3_emu:ERROR:	[
Setup Element:
  Group: 0
  Downlink: 1
  Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
  ASICs Map: None
  Clock Phase Characteristic:
    Optimal Phase: 47
    Window Length: 45
    Eye Windows:
      Uplink  0: XXXXXXXXXXXXXXXXXXXXXXX_X_______________________________________________XXXXXXXX
      Uplink  1: XXXXXXXXXXXXXXXXXXXXXXX_X_______________________________________________XXXXXXXX
      Uplink  2: XX______________________________________________________________________________
      Uplink  3: XX______________________________________________________________________________
      Uplink  4: XXXXXXXXXXXXXXXXXXXXX____________________________________________________XXXXXXX
      Uplink  5: XXXXXXXXXXXXXXXXXXXXX____________________________________________________XXXXXXX
      Uplink  6: XXXXXXXXXXXXXX________________________________________________________XXXXXXXXXX
      Uplink  7: XXXXXXXXXXXXXX________________________________________________________XXXXXXXXXX
      Uplink  8: XXXXXXXXXX______________________________________________________________________
      Uplink  9: XXXXXXXXXX______________________________________________________________________
      Uplink 10: X_______________________________________________________________________________
      Uplink 11: X_______________________________________________________________________________
      Uplink 12: XXXXXXXXXX______________________________________________________________________
      Uplink 13: XXXXXXXXXX______________________________________________________________________
      Uplink 14: XXXXXXXXXXX_X__________________________________________________________XXXXXXXXX
      Uplink 15: XXXXXXXXXXX_X__________________________________________________________XXXXXXXXX
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 5
      Window Length: 12
      Eye Window: ____________XXXXXXXXXXXXXXXXXXXXXXXXXXXX
    Uplink 1:
      Optimal Phase: 5
      Window Length: 12
      Eye Window: ____________XXXXXXXXXXXXXXXXXXXXXXXXXXXX
    Uplink 2:
      Optimal Phase: 3
      Window Length: 7
      Eye Window: _______XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
    Uplink 3:
      Optimal Phase: 3
      Window Length: 7
      Eye Window: _______XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
    Uplink 4:
      Optimal Phase: 12
      Window Length: 26
      Eye Window: __________________________XXXXXXXXXXXXXX
    Uplink 5:
      Optimal Phase: 9
      Window Length: 19
      Eye Window: ___________________X__XXXXXXXXXXXXXXXXXX
    Uplink 6:
      Optimal Phase: 38
      Window Length: 30
      Eye Window: ______________XXXXXXXXXX________________
    Uplink 7:
      Optimal Phase: 32
      Window Length: 30
      Eye Window: ________XXXXXXXXXX______________________
    Uplink 8:
      Optimal Phase: 28
      Window Length: 32
      Eye Window: _____XXXXXXXX___________________________
    Uplink 9:
      Optimal Phase: 33
      Window Length: 33
      Eye Window: __________XXXXXXX_______________________
    Uplink 10:
      Optimal Phase: 29
      Window Length: 32
      Eye Window: ______XXXXXXXX__________________________
    Uplink 11:
      Optimal Phase: 33
      Window Length: 31
      Eye Window: _________XXXXXXXXX______________________
    Uplink 12:
      Optimal Phase: 31
      Window Length: 30
      Eye Window: _______XXXXXXXXXX_______________________
    Uplink 13:
      Optimal Phase: 35
      Window Length: 29
      Eye Window: __________XXXXXXXXXXX___________________
    Uplink 14:
      Optimal Phase: 30
      Window Length: 29
      Eye Window: _____X_XXXXXXXXX________________________
    Uplink 15:
      Optimal Phase: 32
      Window Length: 28
      Eye Window: _______XXXXXXXXXXXX_____________________
]
09:33:21:setup_element:INFO:	Beginning SMX ASICs map scan
09:33:21:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
09:33:21:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
09:33:21:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
09:33:21:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
09:33:21:uplink:INFO:	Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
09:33:21:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 1
09:33:21:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 0
09:33:21:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 8
09:33:21:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 9
09:33:22:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 3
09:33:22:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 2
09:33:22:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 10
09:33:22:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 11
09:33:22:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 5
09:33:22:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 4
09:33:22:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 12
09:33:22:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 1, uplink 13
09:33:22:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 7
09:33:22:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 6
09:33:22:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 14
09:33:22:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 15
09:33:24:ST3_emu:ERROR:	
Setup Element:
  Group: 0
  Downlink: 1
  Uplinks: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
  ASICs Map:
    ASIC address 0x0: (ASIC uplink, uplink): (0, 1), (1, 0)
    ASIC address 0x1: (ASIC uplink, uplink): (0, 8), (1, 9)
    ASIC address 0x2: (ASIC uplink, uplink): (0, 3), (1, 2)
    ASIC address 0x3: (ASIC uplink, uplink): (0, 10), (1, 11)
    ASIC address 0x4: (ASIC uplink, uplink): (0, 5), (1, 4)
    ASIC address 0x5: (ASIC uplink, uplink): (0, 12), (1, 13)
    ASIC address 0x6: (ASIC uplink, uplink): (0, 7), (1, 6)
    ASIC address 0x7: (ASIC uplink, uplink): (0, 14), (1, 15)
  Clock Phase Characteristic:
    Optimal Phase: 47
    Window Length: 45
    Eye Windows:
      Uplink  0: XXXXXXXXXXXXXXXXXXXXXXX_X_______________________________________________XXXXXXXX
      Uplink  1: XXXXXXXXXXXXXXXXXXXXXXX_X_______________________________________________XXXXXXXX
      Uplink  2: XX______________________________________________________________________________
      Uplink  3: XX______________________________________________________________________________
      Uplink  4: XXXXXXXXXXXXXXXXXXXXX____________________________________________________XXXXXXX
      Uplink  5: XXXXXXXXXXXXXXXXXXXXX____________________________________________________XXXXXXX
      Uplink  6: XXXXXXXXXXXXXX________________________________________________________XXXXXXXXXX
      Uplink  7: XXXXXXXXXXXXXX________________________________________________________XXXXXXXXXX
      Uplink  8: XXXXXXXXXX______________________________________________________________________
      Uplink  9: XXXXXXXXXX______________________________________________________________________
      Uplink 10: X_______________________________________________________________________________
      Uplink 11: X_______________________________________________________________________________
      Uplink 12: XXXXXXXXXX______________________________________________________________________
      Uplink 13: XXXXXXXXXX______________________________________________________________________
      Uplink 14: XXXXXXXXXXX_X__________________________________________________________XXXXXXXXX
      Uplink 15: XXXXXXXXXXX_X__________________________________________________________XXXXXXXXX
  Data phase characteristics:
    Uplink 0:
      Optimal Phase: 5
      Window Length: 12
      Eye Window: ____________XXXXXXXXXXXXXXXXXXXXXXXXXXXX
    Uplink 1:
      Optimal Phase: 5
      Window Length: 12
      Eye Window: ____________XXXXXXXXXXXXXXXXXXXXXXXXXXXX
    Uplink 2:
      Optimal Phase: 3
      Window Length: 7
      Eye Window: _______XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
    Uplink 3:
      Optimal Phase: 3
      Window Length: 7
      Eye Window: _______XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
    Uplink 4:
      Optimal Phase: 12
      Window Length: 26
      Eye Window: __________________________XXXXXXXXXXXXXX
    Uplink 5:
      Optimal Phase: 9
      Window Length: 19
      Eye Window: ___________________X__XXXXXXXXXXXXXXXXXX
    Uplink 6:
      Optimal Phase: 38
      Window Length: 30
      Eye Window: ______________XXXXXXXXXX________________
    Uplink 7:
      Optimal Phase: 32
      Window Length: 30
      Eye Window: ________XXXXXXXXXX______________________
    Uplink 8:
      Optimal Phase: 28
      Window Length: 32
      Eye Window: _____XXXXXXXX___________________________
    Uplink 9:
      Optimal Phase: 33
      Window Length: 33
      Eye Window: __________XXXXXXX_______________________
    Uplink 10:
      Optimal Phase: 29
      Window Length: 32
      Eye Window: ______XXXXXXXX__________________________
    Uplink 11:
      Optimal Phase: 33
      Window Length: 31
      Eye Window: _________XXXXXXXXX______________________
    Uplink 12:
      Optimal Phase: 31
      Window Length: 30
      Eye Window: _______XXXXXXXXXX_______________________
    Uplink 13:
      Optimal Phase: 35
      Window Length: 29
      Eye Window: __________XXXXXXXXXXX___________________
    Uplink 14:
      Optimal Phase: 30
      Window Length: 29
      Eye Window: _____X_XXXXXXXXX________________________
    Uplink 15:
      Optimal Phase: 32
      Window Length: 28
      Eye Window: _______XXXXXXXXXXXX_____________________

09:33:24:setup_element:INFO:	Performing Elink synchronization
09:33:24:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
09:33:24:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
09:33:24:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
09:33:24:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
09:33:24:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 1
09:33:24:uplink:INFO:	Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
09:33:24:ST3_emu:INFO:	Number of chips: 8
addr  |  upli  |  dwnli  |  grp |  uplinks | uplinks_map
   0  |   [0]   |  1  |  0  |     [1]      |   [(0, 1), (1, 0)] 
   1  |   [0]   |  1  |  0  |     [8]      |   [(0, 8), (1, 9)] 
   2  |   [0]   |  1  |  0  |     [3]      |   [(0, 3), (1, 2)] 
   3  |   [0]   |  1  |  0  |     [10]     |  [(0, 10), (1, 11)]
   4  |   [0]   |  1  |  0  |     [5]      |   [(0, 5), (1, 4)] 
   5  |   [0]   |  1  |  0  |     [12]     |  [(0, 12), (1, 13)]
   6  |   [0]   |  1  |  0  |     [7]      |   [(0, 7), (1, 6)] 
   7  |   [0]   |  1  |  0  |     [14]     |  [(0, 14), (1, 15)]
FEB type: A FEB_A: 1 FEB_B: 0
09:33:25:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:33:25:febtest:INFO:	01-00 | XA-000-08-001-064-041-144-10 |  40.9 | 1177.4
09:33:26:febtest:INFO:	08-01 | XA-000-08-001-064-041-216-15 |  50.4 | 1159.7
09:33:26:febtest:INFO:	03-02 | XA-000-08-001-064-041-208-15 |  18.7 | 1247.9
09:33:26:febtest:INFO:	10-03 | XA-000-08-001-064-041-232-06 |  44.1 | 1189.2
09:33:26:febtest:INFO:	05-04 | XA-000-08-001-064-041-224-06 |  40.9 | 1201.0
09:33:26:febtest:INFO:	12-05 | XA-000-08-001-064-043-000-04 |  37.7 | 1195.1
09:33:27:febtest:INFO:	07-06 | XA-000-08-001-064-041-184-04 |  31.4 | 1224.5
09:33:27:febtest:INFO:	14-07 | XA-000-08-001-064-043-136-14 |  28.2 | 1230.3
09:33:27:ST3_smx:INFO:	Configuring SMX FAST
09:33:30:ST3_smx:INFO:	chip: 1-0 	 50.430383 C 	 1147.806000 mV
09:33:30:ST3_smx:INFO:		Electrons
09:33:30:ST3_smx:INFO:	# loops 0
09:33:32:ST3_smx:INFO:	# loops 1
09:33:34:ST3_smx:INFO:	# loops 2
09:33:36:ST3_smx:INFO:	Total # of broken channels: 0
09:33:36:ST3_smx:INFO:	List of broken channels: []
09:33:36:ST3_smx:INFO:	Total # of broken channels: 0
09:33:36:ST3_smx:INFO:	List of broken channels: []
09:33:37:ST3_smx:INFO:	Configuring SMX FAST
09:33:39:ST3_smx:INFO:	chip: 8-1 	 53.612520 C 	 1147.806000 mV
09:33:39:ST3_smx:INFO:		Electrons
09:33:39:ST3_smx:INFO:	# loops 0
09:33:41:ST3_smx:INFO:	# loops 1
09:33:43:ST3_smx:INFO:	# loops 2
09:33:45:ST3_smx:INFO:	Total # of broken channels: 0
09:33:45:ST3_smx:INFO:	List of broken channels: []
09:33:45:ST3_smx:INFO:	Total # of broken channels: 0
09:33:45:ST3_smx:INFO:	List of broken channels: []
09:33:46:ST3_smx:INFO:	Configuring SMX FAST
09:33:49:ST3_smx:INFO:	chip: 3-2 	 28.225000 C 	 1224.468235 mV
09:33:49:ST3_smx:INFO:		Electrons
09:33:49:ST3_smx:INFO:	# loops 0
09:33:51:ST3_smx:INFO:	# loops 1
09:33:53:ST3_smx:INFO:	# loops 2
09:33:55:ST3_smx:INFO:	Total # of broken channels: 0
09:33:55:ST3_smx:INFO:	List of broken channels: []
09:33:55:ST3_smx:INFO:	Total # of broken channels: 0
09:33:55:ST3_smx:INFO:	List of broken channels: []
09:33:56:ST3_smx:INFO:	Configuring SMX FAST
09:33:58:ST3_smx:INFO:	chip: 10-3 	 47.250730 C 	 1183.292940 mV
09:33:58:ST3_smx:INFO:		Electrons
09:33:58:ST3_smx:INFO:	# loops 0
09:34:00:ST3_smx:INFO:	# loops 1
09:34:02:ST3_smx:INFO:	# loops 2
09:34:04:ST3_smx:INFO:	Total # of broken channels: 0
09:34:04:ST3_smx:INFO:	List of broken channels: []
09:34:04:ST3_smx:INFO:	Total # of broken channels: 0
09:34:04:ST3_smx:INFO:	List of broken channels: []
09:34:05:ST3_smx:INFO:	Configuring SMX FAST
09:34:08:ST3_smx:INFO:	chip: 5-4 	 47.250730 C 	 1177.390875 mV
09:34:08:ST3_smx:INFO:		Electrons
09:34:08:ST3_smx:INFO:	# loops 0
09:34:10:ST3_smx:INFO:	# loops 1
09:34:12:ST3_smx:INFO:	# loops 2
09:34:14:ST3_smx:INFO:	Total # of broken channels: 0
09:34:14:ST3_smx:INFO:	List of broken channels: []
09:34:14:ST3_smx:INFO:	Total # of broken channels: 0
09:34:14:ST3_smx:INFO:	List of broken channels: []
09:34:15:ST3_smx:INFO:	Configuring SMX FAST
09:34:18:ST3_smx:INFO:	chip: 12-5 	 40.898880 C 	 1183.292940 mV
09:34:18:ST3_smx:INFO:		Electrons
09:34:18:ST3_smx:INFO:	# loops 0
09:34:20:ST3_smx:INFO:	# loops 1
09:34:22:ST3_smx:INFO:	# loops 2
09:34:24:ST3_smx:INFO:	Total # of broken channels: 0
09:34:24:ST3_smx:INFO:	List of broken channels: []
09:34:24:ST3_smx:INFO:	Total # of broken channels: 0
09:34:24:ST3_smx:INFO:	List of broken channels: []
09:34:25:ST3_smx:INFO:	Configuring SMX FAST
09:34:28:ST3_smx:INFO:	chip: 7-6 	 34.556970 C 	 1218.600960 mV
09:34:28:ST3_smx:INFO:		Electrons
09:34:28:ST3_smx:INFO:	# loops 0
09:34:30:ST3_smx:INFO:	# loops 1
Traceback (most recent call last):
  File "febtest.py", line 504, in DoFEB_SensorTest
    self.EMU.mysmx[i].MicroCableTest('e')
  File "/home/cbm/ST3_v2.29.16/lib/ST3_smx.py", line 590, in MicroCableTest
    val = self.smx.read(ch, (2*d))&0xFFF
  File "/home/cbm/ST3_BASE/smx_software_FEB8_2_20MHz/python/smx_tester/smx.py", line 39, in read
    return self.ack_monitor.check_read()
  File "/home/cbm/ST3_BASE/smx_software_FEB8_2_20MHz/python/hctsp/ack_monitor.py", line 88, in check_read
    return self._check(self._check_read, timeout)
  File "/home/cbm/ST3_BASE/smx_software_FEB8_2_20MHz/python/hctsp/ack_monitor.py", line 60, in _check
    raise AckNotReceived
hctsp.ack_monitor.AckNotReceived: Ack frame not received