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FEB_3080 22.01.25 14:08:52
Info
14:08:52:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:08:52:ST3_Shared:INFO: FEB-Microcable
14:08:52:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:08:52:febtest:INFO: Testing FEB with SN 3080
14:08:54:smx_tester:INFO: Scanning setup
14:08:54:elinks:INFO: Disabling clock on downlink 0
14:08:54:elinks:INFO: Disabling clock on downlink 1
14:08:54:elinks:INFO: Disabling clock on downlink 2
14:08:54:elinks:INFO: Disabling clock on downlink 3
14:08:54:elinks:INFO: Disabling clock on downlink 4
14:08:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:08:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:08:54:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:08:54:elinks:INFO: Disabling clock on downlink 0
14:08:54:elinks:INFO: Disabling clock on downlink 1
14:08:54:elinks:INFO: Disabling clock on downlink 2
14:08:54:elinks:INFO: Disabling clock on downlink 3
14:08:54:elinks:INFO: Disabling clock on downlink 4
14:08:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:08:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:08:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
14:08:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
14:08:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
14:08:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
14:08:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
14:08:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
14:08:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
14:08:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
14:08:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
14:08:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
14:08:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
14:08:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
14:08:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
14:08:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
14:08:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
14:08:54:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
14:08:54:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:08:54:elinks:INFO: Disabling clock on downlink 0
14:08:54:elinks:INFO: Disabling clock on downlink 1
14:08:54:elinks:INFO: Disabling clock on downlink 2
14:08:54:elinks:INFO: Disabling clock on downlink 3
14:08:54:elinks:INFO: Disabling clock on downlink 4
14:08:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:08:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:08:54:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:08:54:elinks:INFO: Disabling clock on downlink 0
14:08:54:elinks:INFO: Disabling clock on downlink 1
14:08:54:elinks:INFO: Disabling clock on downlink 2
14:08:54:elinks:INFO: Disabling clock on downlink 3
14:08:54:elinks:INFO: Disabling clock on downlink 4
14:08:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:08:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:08:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:08:55:elinks:INFO: Disabling clock on downlink 0
14:08:55:elinks:INFO: Disabling clock on downlink 1
14:08:55:elinks:INFO: Disabling clock on downlink 2
14:08:55:elinks:INFO: Disabling clock on downlink 3
14:08:55:elinks:INFO: Disabling clock on downlink 4
14:08:55:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:08:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:08:55:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:08:55:setup_element:INFO: Scanning clock phase
14:08:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:08:55:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:08:55:setup_element:INFO: Clock phase scan results for group 0, downlink 1
14:08:55:setup_element:INFO: Eye window for uplink 0 : X___________________________________________________________________________XXXX
Clock Delay: 38
14:08:55:setup_element:INFO: Eye window for uplink 1 : X___________________________________________________________________________XXXX
Clock Delay: 38
14:08:55:setup_element:INFO: Eye window for uplink 2 : __________________________________________________________________________XXXXX_
Clock Delay: 36
14:08:55:setup_element:INFO: Eye window for uplink 3 : __________________________________________________________________________XXXXX_
Clock Delay: 36
14:08:55:setup_element:INFO: Eye window for uplink 4 : ________________________________________________________________________________
Clock Delay: 40
14:08:55:setup_element:INFO: Eye window for uplink 5 : ________________________________________________________________________________
Clock Delay: 40
14:08:55:setup_element:INFO: Eye window for uplink 6 : ____________________________________________________________________________XXX_
Clock Delay: 37
14:08:55:setup_element:INFO: Eye window for uplink 7 : ____________________________________________________________________________XXX_
Clock Delay: 37
14:08:55:setup_element:INFO: Eye window for uplink 8 : __________________________________________________________________________XXXXXX
Clock Delay: 36
14:08:55:setup_element:INFO: Eye window for uplink 9 : __________________________________________________________________________XXXXXX
Clock Delay: 36
14:08:55:setup_element:INFO: Eye window for uplink 10: _________________________________________________________________________XXXXXX_
Clock Delay: 35
14:08:55:setup_element:INFO: Eye window for uplink 11: _________________________________________________________________________XXXXXX_
Clock Delay: 35
14:08:55:setup_element:INFO: Eye window for uplink 12: _________________________________________________________________________XXXXXXX
Clock Delay: 36
14:08:55:setup_element:INFO: Eye window for uplink 13: _________________________________________________________________________XXXXXXX
Clock Delay: 36
14:08:55:setup_element:INFO: Eye window for uplink 14: ___________________________________________________________________________XXXX_
Clock Delay: 36
14:08:55:setup_element:INFO: Eye window for uplink 15: ___________________________________________________________________________XXXX_
Clock Delay: 36
14:08:55:setup_element:INFO: Setting the clock phase to 36 for group 0, downlink 1
14:08:55:setup_element:INFO: Scanning data phases
14:08:55:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:08:55:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:09:00:setup_element:INFO: Data phase scan results for group 0, downlink 1
14:09:00:setup_element:INFO: Eye window for uplink 0 : ______XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 2
14:09:00:setup_element:INFO: Eye window for uplink 1 : ______XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
Data delay found: 2
14:09:00:setup_element:INFO: Eye window for uplink 2 : _____XXXXX______________________________
Data delay found: 27
14:09:00:setup_element:INFO: Eye window for uplink 3 : __XXXX__________________________________
Data delay found: 23
14:09:00:setup_element:INFO: Eye window for uplink 4 : ____XXX_________________________________
Data delay found: 25
14:09:00:setup_element:INFO: Eye window for uplink 5 : XXXX___________________________________X
Data delay found: 21
14:09:00:setup_element:INFO: Eye window for uplink 6 : XXXX___________________________________X
Data delay found: 21
14:09:00:setup_element:INFO: Eye window for uplink 7 : X___________________________________XXXX
Data delay found: 18
14:09:00:setup_element:INFO: Eye window for uplink 8 : ________________________XXXXXX__________
Data delay found: 6
14:09:00:setup_element:INFO: Eye window for uplink 9 : _____________________________XXXXX______
Data delay found: 11
14:09:00:setup_element:INFO: Eye window for uplink 10: _______________________XXXXXX___________
Data delay found: 5
14:09:00:setup_element:INFO: Eye window for uplink 11: ___________________________XXXXX________
Data delay found: 9
14:09:00:setup_element:INFO: Eye window for uplink 12: _________________________XXXXX__________
Data delay found: 7
14:09:00:setup_element:INFO: Eye window for uplink 13: ____________________________XXXXX_______
Data delay found: 10
14:09:00:setup_element:INFO: Eye window for uplink 14: ___________________________XXXXX________
Data delay found: 9
14:09:00:setup_element:INFO: Eye window for uplink 15: ____________________________XXXXXX______
Data delay found: 10
14:09:00:setup_element:INFO: Setting the data phase to 2 for uplink 0
14:09:00:setup_element:INFO: Setting the data phase to 2 for uplink 1
14:09:00:setup_element:INFO: Setting the data phase to 27 for uplink 2
14:09:00:setup_element:INFO: Setting the data phase to 23 for uplink 3
14:09:00:setup_element:INFO: Setting the data phase to 25 for uplink 4
14:09:00:setup_element:INFO: Setting the data phase to 21 for uplink 5
14:09:00:setup_element:INFO: Setting the data phase to 21 for uplink 6
14:09:00:setup_element:INFO: Setting the data phase to 18 for uplink 7
14:09:00:setup_element:INFO: Setting the data phase to 6 for uplink 8
14:09:00:setup_element:INFO: Setting the data phase to 11 for uplink 9
14:09:00:setup_element:INFO: Setting the data phase to 5 for uplink 10
14:09:00:setup_element:INFO: Setting the data phase to 9 for uplink 11
14:09:00:setup_element:INFO: Setting the data phase to 7 for uplink 12
14:09:00:setup_element:INFO: Setting the data phase to 10 for uplink 13
14:09:00:setup_element:INFO: Setting the data phase to 9 for uplink 14
14:09:00:setup_element:INFO: Setting the data phase to 10 for uplink 15
14:09:00:setup_element:INFO: Beginning SMX ASICs map scan
14:09:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:09:00:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:09:00:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
14:09:00:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
14:09:00:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
14:09:00:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
14:09:00:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
14:09:00:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
14:09:01:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
14:09:01:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
14:09:01:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
14:09:01:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
14:09:01:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
14:09:01:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
14:09:01:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
14:09:01:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
14:09:01:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
14:09:01:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
14:09:01:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
14:09:02:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
14:09:02:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
14:09:03:setup_element:INFO: Performing Elink synchronization
14:09:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:09:03:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:09:03:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
14:09:03:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
14:09:03:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
14:09:03:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 1 | 0 | [1] | 2 | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | 2 | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | 2 | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | 2 | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | 2 | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | 2 | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | 2 | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | 2 | [(0, 14), (1, 15)]
|_________________________________________________________________________|
14:09:04:febtest:INFO: Init all SMX (CSA): 30
14:09:17:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:09:17:febtest:INFO: 01-00 | XA-000-09-004-002-007-025-02 | 44.1 | 1141.9
14:09:17:febtest:INFO: 08-01 | XA-000-09-004-002-004-023-12 | 28.2 | 1201.0
14:09:18:febtest:INFO: 03-02 | XA-000-09-004-002-007-024-02 | 44.1 | 1147.8
14:09:18:febtest:INFO: 10-03 | XA-000-09-004-002-010-022-05 | 47.3 | 1135.9
14:09:18:febtest:INFO: 05-04 | XA-000-09-004-002-007-022-02 | 44.1 | 1153.7
14:09:18:febtest:INFO: 12-05 | XA-000-09-004-002-010-027-05 | 44.1 | 1147.8
14:09:18:febtest:INFO: 07-06 | XA-000-09-004-002-007-026-02 | 53.6 | 1112.1
14:09:19:febtest:INFO: 14-07 | XA-000-09-004-002-007-023-02 | 47.3 | 1130.0
14:09:20:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
14:09:22:ST3_smx:INFO: chip: 1-0 44.073563 C 1153.732915 mV
14:09:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:09:22:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:09:22:ST3_smx:INFO: Electrons
14:09:22:ST3_smx:INFO: # loops 0
14:09:23:ST3_smx:INFO: # loops 1
14:09:25:ST3_smx:INFO: # loops 2
14:09:27:ST3_smx:INFO: Total # of broken channels: 0
14:09:27:ST3_smx:INFO: List of broken channels: []
14:09:27:ST3_smx:INFO: Total # of broken channels: 0
14:09:27:ST3_smx:INFO: List of broken channels: []
14:09:28:ST3_smx:INFO: chip: 8-1 31.389742 C 1224.468235 mV
14:09:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:09:28:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:09:28:ST3_smx:INFO: Electrons
14:09:28:ST3_smx:INFO: # loops 0
14:09:30:ST3_smx:INFO: # loops 1
14:09:32:ST3_smx:INFO: # loops 2
14:09:34:ST3_smx:INFO: Total # of broken channels: 0
14:09:34:ST3_smx:INFO: List of broken channels: []
14:09:34:ST3_smx:INFO: Total # of broken channels: 0
14:09:34:ST3_smx:INFO: List of broken channels: []
14:09:35:ST3_smx:INFO: chip: 3-2 44.073563 C 1159.654860 mV
14:09:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:09:35:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:09:35:ST3_smx:INFO: Electrons
14:09:35:ST3_smx:INFO: # loops 0
14:09:37:ST3_smx:INFO: # loops 1
14:09:38:ST3_smx:INFO: # loops 2
14:09:40:ST3_smx:INFO: Total # of broken channels: 0
14:09:40:ST3_smx:INFO: List of broken channels: []
14:09:40:ST3_smx:INFO: Total # of broken channels: 0
14:09:40:ST3_smx:INFO: List of broken channels: []
14:09:42:ST3_smx:INFO: chip: 10-3 47.250730 C 1153.732915 mV
14:09:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:09:42:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:09:42:ST3_smx:INFO: Electrons
14:09:42:ST3_smx:INFO: # loops 0
14:09:44:ST3_smx:INFO: # loops 1
14:09:46:ST3_smx:INFO: # loops 2
14:09:47:ST3_smx:INFO: Total # of broken channels: 0
14:09:47:ST3_smx:INFO: List of broken channels: []
14:09:47:ST3_smx:INFO: Total # of broken channels: 0
14:09:47:ST3_smx:INFO: List of broken channels: []
14:09:49:ST3_smx:INFO: chip: 5-4 47.250730 C 1165.571835 mV
14:09:49:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:09:49:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:09:49:ST3_smx:INFO: Electrons
14:09:49:ST3_smx:INFO: # loops 0
14:09:50:ST3_smx:INFO: # loops 1
14:09:52:ST3_smx:INFO: # loops 2
14:09:53:ST3_smx:INFO: Total # of broken channels: 0
14:09:53:ST3_smx:INFO: List of broken channels: []
14:09:53:ST3_smx:INFO: Total # of broken channels: 0
14:09:53:ST3_smx:INFO: List of broken channels: []
14:09:55:ST3_smx:INFO: chip: 12-5 44.073563 C 1159.654860 mV
14:09:55:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:09:55:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:09:55:ST3_smx:INFO: Electrons
14:09:55:ST3_smx:INFO: # loops 0
14:09:57:ST3_smx:INFO: # loops 1
14:09:58:ST3_smx:INFO: # loops 2
14:10:00:ST3_smx:INFO: Total # of broken channels: 0
14:10:00:ST3_smx:INFO: List of broken channels: []
14:10:00:ST3_smx:INFO: Total # of broken channels: 0
14:10:00:ST3_smx:INFO: List of broken channels: []
14:10:01:ST3_smx:INFO: chip: 7-6 56.797143 C 1118.096875 mV
14:10:01:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:10:01:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:10:01:ST3_smx:INFO: Electrons
14:10:01:ST3_smx:INFO: # loops 0
14:10:03:ST3_smx:INFO: # loops 1
14:10:05:ST3_smx:INFO: # loops 2
14:10:06:ST3_smx:INFO: Total # of broken channels: 0
14:10:06:ST3_smx:INFO: List of broken channels: []
14:10:06:ST3_smx:INFO: Total # of broken channels: 0
14:10:06:ST3_smx:INFO: List of broken channels: []
14:10:08:ST3_smx:INFO: chip: 14-7 50.430383 C 1141.874115 mV
14:10:08:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:10:08:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:10:08:ST3_smx:INFO: Electrons
14:10:08:ST3_smx:INFO: # loops 0
14:10:09:ST3_smx:INFO: # loops 1
14:10:11:ST3_smx:INFO: # loops 2
14:10:12:ST3_smx:INFO: Total # of broken channels: 0
14:10:12:ST3_smx:INFO: List of broken channels: []
14:10:12:ST3_smx:INFO: Total # of broken channels: 0
14:10:12:ST3_smx:INFO: List of broken channels: []
14:10:13:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:10:13:febtest:INFO: 01-00 | XA-000-09-004-002-007-025-02 | 47.3 | 1171.5
14:10:13:febtest:INFO: 08-01 | XA-000-09-004-002-004-023-12 | 28.2 | 1282.9
14:10:13:febtest:INFO: 03-02 | XA-000-09-004-002-007-024-02 | 47.3 | 1183.3
14:10:13:febtest:INFO: 10-03 | XA-000-09-004-002-010-022-05 | 50.4 | 1171.5
14:10:14:febtest:INFO: 05-04 | XA-000-09-004-002-007-022-02 | 47.3 | 1183.3
14:10:14:febtest:INFO: 12-05 | XA-000-09-004-002-010-027-05 | 47.3 | 1183.3
14:10:14:febtest:INFO: 07-06 | XA-000-09-004-002-007-026-02 | 53.6 | 1147.8
14:10:14:febtest:INFO: 14-07 | XA-000-09-004-002-007-023-02 | 50.4 | 1159.7
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_01_22-14_08_52
OPERATOR : Henrik;
SITE : KIT | SETUP : KIT_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 3080| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['2.450', '1.4260', '1.850', '2.9490', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '1.9430', '1.850', '2.3650', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9580', '1.850', '0.5253', '0.000', '0.0000', '0.000', '0.0000']