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FEB_3128 19.03.25 14:27:35
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14:27:35:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:27:35:ST3_Shared:INFO: FEB-Microcable
14:27:35:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:27:35:febtest:INFO: Testing FEB with SN 3128
14:27:36:smx_tester:INFO: Scanning setup
14:27:36:elinks:INFO: Disabling clock on downlink 0
14:27:36:elinks:INFO: Disabling clock on downlink 1
14:27:36:elinks:INFO: Disabling clock on downlink 2
14:27:36:elinks:INFO: Disabling clock on downlink 3
14:27:36:elinks:INFO: Disabling clock on downlink 4
14:27:36:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:27:36:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
14:27:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:27:37:elinks:INFO: Disabling clock on downlink 0
14:27:37:elinks:INFO: Disabling clock on downlink 1
14:27:37:elinks:INFO: Disabling clock on downlink 2
14:27:37:elinks:INFO: Disabling clock on downlink 3
14:27:37:elinks:INFO: Disabling clock on downlink 4
14:27:37:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:27:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:27:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 0
14:27:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 1
14:27:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 2
14:27:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 3
14:27:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 4
14:27:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 5
14:27:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 6
14:27:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 7
14:27:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 8
14:27:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 9
14:27:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 10
14:27:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 11
14:27:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 12
14:27:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 13
14:27:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 14
14:27:37:setup_element:INFO: SOS detected for group 0, downlink 1, uplink 15
14:27:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:27:37:elinks:INFO: Disabling clock on downlink 0
14:27:37:elinks:INFO: Disabling clock on downlink 1
14:27:37:elinks:INFO: Disabling clock on downlink 2
14:27:37:elinks:INFO: Disabling clock on downlink 3
14:27:37:elinks:INFO: Disabling clock on downlink 4
14:27:37:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:27:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
14:27:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:27:37:elinks:INFO: Disabling clock on downlink 0
14:27:37:elinks:INFO: Disabling clock on downlink 1
14:27:37:elinks:INFO: Disabling clock on downlink 2
14:27:37:elinks:INFO: Disabling clock on downlink 3
14:27:37:elinks:INFO: Disabling clock on downlink 4
14:27:37:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:27:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
14:27:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:27:37:elinks:INFO: Disabling clock on downlink 0
14:27:37:elinks:INFO: Disabling clock on downlink 1
14:27:37:elinks:INFO: Disabling clock on downlink 2
14:27:37:elinks:INFO: Disabling clock on downlink 3
14:27:37:elinks:INFO: Disabling clock on downlink 4
14:27:37:setup_element:INFO: Checking SOS, encoding_mode: SOS
14:27:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
14:27:37:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
14:27:37:setup_element:INFO: Scanning clock phase
14:27:37:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:27:37:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:27:37:setup_element:INFO: Clock phase scan results for group 0, downlink 1
14:27:37:setup_element:INFO: Eye window for uplink 0 : ____________________________________________________________________________XXXX
Clock Delay: 37
14:27:37:setup_element:INFO: Eye window for uplink 1 : ____________________________________________________________________________XXXX
Clock Delay: 37
14:27:37:setup_element:INFO: Eye window for uplink 2 : ___________________________________________________________________________XXXXX
Clock Delay: 37
14:27:37:setup_element:INFO: Eye window for uplink 3 : ___________________________________________________________________________XXXXX
Clock Delay: 37
14:27:37:setup_element:INFO: Eye window for uplink 4 : ___________________________________________________________________________XXXXX
Clock Delay: 37
14:27:37:setup_element:INFO: Eye window for uplink 5 : ___________________________________________________________________________XXXXX
Clock Delay: 37
14:27:37:setup_element:INFO: Eye window for uplink 6 : ___________________________________________________________________________XXXXX
Clock Delay: 37
14:27:38:setup_element:INFO: Eye window for uplink 7 : ___________________________________________________________________________XXXXX
Clock Delay: 37
14:27:38:setup_element:INFO: Eye window for uplink 8 : ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:27:38:setup_element:INFO: Eye window for uplink 9 : ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:27:38:setup_element:INFO: Eye window for uplink 10: ________________________________________________________________________XXXXX___
Clock Delay: 34
14:27:38:setup_element:INFO: Eye window for uplink 11: ________________________________________________________________________XXXXX___
Clock Delay: 34
14:27:38:setup_element:INFO: Eye window for uplink 12: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:27:38:setup_element:INFO: Eye window for uplink 13: _________________________________________________________________________XXXXX__
Clock Delay: 35
14:27:38:setup_element:INFO: Eye window for uplink 14: __________________________________________________________________________XXXX__
Clock Delay: 35
14:27:38:setup_element:INFO: Eye window for uplink 15: __________________________________________________________________________XXXX__
Clock Delay: 35
14:27:38:setup_element:INFO: Setting the clock phase to 35 for group 0, downlink 1
14:27:38:setup_element:INFO: Scanning data phases
14:27:38:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:27:38:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:27:43:setup_element:INFO: Data phase scan results for group 0, downlink 1
14:27:43:setup_element:INFO: Eye window for uplink 0 : ____________XXXXX_______________________
Data delay found: 34
14:27:43:setup_element:INFO: Eye window for uplink 1 : ________XXXX____________________________
Data delay found: 29
14:27:43:setup_element:INFO: Eye window for uplink 2 : _________XXXXX__________________________
Data delay found: 31
14:27:43:setup_element:INFO: Eye window for uplink 3 : ______XXXX______________________________
Data delay found: 27
14:27:43:setup_element:INFO: Eye window for uplink 4 : ______XXXXX_____________________________
Data delay found: 28
14:27:43:setup_element:INFO: Eye window for uplink 5 : ___XXXXX________________________________
Data delay found: 25
14:27:43:setup_element:INFO: Eye window for uplink 6 : XXXX___________________________________X
Data delay found: 21
14:27:43:setup_element:INFO: Eye window for uplink 7 : ___________________________________XXXX_
Data delay found: 16
14:27:43:setup_element:INFO: Eye window for uplink 8 : ______________________XXXXXX____________
Data delay found: 4
14:27:43:setup_element:INFO: Eye window for uplink 9 : ___________________________XXXXX________
Data delay found: 9
14:27:43:setup_element:INFO: Eye window for uplink 10: _______________________XXXXXX___________
Data delay found: 5
14:27:43:setup_element:INFO: Eye window for uplink 11: ___________________________XXXXX________
Data delay found: 9
14:27:43:setup_element:INFO: Eye window for uplink 12: __________________________XXXX__________
Data delay found: 7
14:27:43:setup_element:INFO: Eye window for uplink 13: _____________________________XXXX_______
Data delay found: 10
14:27:43:setup_element:INFO: Eye window for uplink 14: ___________________________XXXXX________
Data delay found: 9
14:27:43:setup_element:INFO: Eye window for uplink 15: _____________________________XXXXX______
Data delay found: 11
14:27:43:setup_element:INFO: Setting the data phase to 34 for uplink 0
14:27:43:setup_element:INFO: Setting the data phase to 29 for uplink 1
14:27:43:setup_element:INFO: Setting the data phase to 31 for uplink 2
14:27:43:setup_element:INFO: Setting the data phase to 27 for uplink 3
14:27:43:setup_element:INFO: Setting the data phase to 28 for uplink 4
14:27:43:setup_element:INFO: Setting the data phase to 25 for uplink 5
14:27:43:setup_element:INFO: Setting the data phase to 21 for uplink 6
14:27:43:setup_element:INFO: Setting the data phase to 16 for uplink 7
14:27:43:setup_element:INFO: Setting the data phase to 4 for uplink 8
14:27:43:setup_element:INFO: Setting the data phase to 9 for uplink 9
14:27:43:setup_element:INFO: Setting the data phase to 5 for uplink 10
14:27:43:setup_element:INFO: Setting the data phase to 9 for uplink 11
14:27:43:setup_element:INFO: Setting the data phase to 7 for uplink 12
14:27:43:setup_element:INFO: Setting the data phase to 10 for uplink 13
14:27:43:setup_element:INFO: Setting the data phase to 9 for uplink 14
14:27:43:setup_element:INFO: Setting the data phase to 11 for uplink 15
14:27:43:setup_element:INFO: Beginning SMX ASICs map scan
14:27:43:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:27:43:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:27:43:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
14:27:43:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
14:27:43:uplink:INFO: Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
14:27:43:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 1
14:27:43:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 0
14:27:43:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 8
14:27:43:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 9
14:27:43:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 3
14:27:43:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 2
14:27:43:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 10
14:27:43:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 11
14:27:44:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 5
14:27:44:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 4
14:27:44:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 12
14:27:44:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 13
14:27:44:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 7
14:27:44:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 6
14:27:44:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 14
14:27:44:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 15
14:27:45:setup_element:INFO: Performing Elink synchronization
14:27:45:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
14:27:45:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:27:45:master:INFO: Setting encoding mode EOS for groups [0], downlinks [1]
14:27:45:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [1]
14:27:45:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 1
14:27:45:uplink:INFO: Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
0 | [0] | 1 | 0 | [1] | 2 | [(0, 1), (1, 0)]
1 | [0] | 1 | 0 | [8] | 2 | [(0, 8), (1, 9)]
2 | [0] | 1 | 0 | [3] | 2 | [(0, 3), (1, 2)]
3 | [0] | 1 | 0 | [10] | 2 | [(0, 10), (1, 11)]
4 | [0] | 1 | 0 | [5] | 2 | [(0, 5), (1, 4)]
5 | [0] | 1 | 0 | [12] | 2 | [(0, 12), (1, 13)]
6 | [0] | 1 | 0 | [7] | 2 | [(0, 7), (1, 6)]
7 | [0] | 1 | 0 | [14] | 2 | [(0, 14), (1, 15)]
|_________________________________________________________________________|
14:27:46:febtest:INFO: Init all SMX (CSA): 30
14:28:02:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:28:02:febtest:INFO: 01-00 | XA-000-09-004-005-008-016-12 | 44.1 | 1147.8
14:28:02:febtest:INFO: 08-01 | XA-000-09-004-005-014-015-14 | 34.6 | 1189.2
14:28:02:febtest:INFO: 03-02 | XA-000-09-004-005-005-016-11 | 34.6 | 1189.2
14:28:03:febtest:INFO: 10-03 | XA-000-09-004-005-011-015-05 | 40.9 | 1159.7
14:28:03:febtest:INFO: 05-04 | XA-000-09-004-005-002-016-03 | 34.6 | 1189.2
14:28:03:febtest:INFO: 12-05 | XA-000-09-004-005-008-015-11 | 40.9 | 1165.6
14:28:03:febtest:INFO: 07-06 | XA-000-09-004-005-002-015-04 | 47.3 | 1141.9
14:28:03:febtest:INFO: 14-07 | XA-000-09-004-005-005-015-12 | 28.2 | 1212.7
14:28:04:febtest:INFO: Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
14:28:06:ST3_smx:INFO: chip: 1-0 44.073563 C 1159.654860 mV
14:28:06:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:28:06:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:28:06:ST3_smx:INFO: Electrons
14:28:06:ST3_smx:INFO: # loops 0
14:28:08:ST3_smx:INFO: # loops 1
14:28:10:ST3_smx:INFO: # loops 2
14:28:11:ST3_smx:INFO: Total # of broken channels: 0
14:28:11:ST3_smx:INFO: List of broken channels: []
14:28:11:ST3_smx:INFO: Total # of broken channels: 0
14:28:11:ST3_smx:INFO: List of broken channels: []
14:28:13:ST3_smx:INFO: chip: 8-1 34.556970 C 1200.969315 mV
14:28:13:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:28:13:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:28:13:ST3_smx:INFO: Electrons
14:28:13:ST3_smx:INFO: # loops 0
14:28:14:ST3_smx:INFO: # loops 1
14:28:16:ST3_smx:INFO: # loops 2
14:28:17:ST3_smx:INFO: Total # of broken channels: 0
14:28:17:ST3_smx:INFO: List of broken channels: []
14:28:18:ST3_smx:INFO: Total # of broken channels: 0
14:28:18:ST3_smx:INFO: List of broken channels: []
14:28:19:ST3_smx:INFO: chip: 3-2 34.556970 C 1200.969315 mV
14:28:19:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:28:19:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:28:19:ST3_smx:INFO: Electrons
14:28:19:ST3_smx:INFO: # loops 0
14:28:21:ST3_smx:INFO: # loops 1
14:28:22:ST3_smx:INFO: # loops 2
14:28:24:ST3_smx:INFO: Total # of broken channels: 0
14:28:24:ST3_smx:INFO: List of broken channels: []
14:28:24:ST3_smx:INFO: Total # of broken channels: 0
14:28:24:ST3_smx:INFO: List of broken channels: []
14:28:26:ST3_smx:INFO: chip: 10-3 40.898880 C 1177.390875 mV
14:28:26:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:28:26:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:28:26:ST3_smx:INFO: Electrons
14:28:26:ST3_smx:INFO: # loops 0
14:28:27:ST3_smx:INFO: # loops 1
14:28:29:ST3_smx:INFO: # loops 2
14:28:31:ST3_smx:INFO: Total # of broken channels: 0
14:28:31:ST3_smx:INFO: List of broken channels: []
14:28:31:ST3_smx:INFO: Total # of broken channels: 0
14:28:31:ST3_smx:INFO: List of broken channels: []
14:28:32:ST3_smx:INFO: chip: 5-4 34.556970 C 1200.969315 mV
14:28:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:28:32:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:28:32:ST3_smx:INFO: Electrons
14:28:32:ST3_smx:INFO: # loops 0
14:28:34:ST3_smx:INFO: # loops 1
14:28:36:ST3_smx:INFO: # loops 2
14:28:38:ST3_smx:INFO: Total # of broken channels: 0
14:28:38:ST3_smx:INFO: List of broken channels: []
14:28:38:ST3_smx:INFO: Total # of broken channels: 0
14:28:38:ST3_smx:INFO: List of broken channels: []
14:28:39:ST3_smx:INFO: chip: 12-5 40.898880 C 1177.390875 mV
14:28:40:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:28:40:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:28:40:ST3_smx:INFO: Electrons
14:28:40:ST3_smx:INFO: # loops 0
14:28:41:ST3_smx:INFO: # loops 1
14:28:43:ST3_smx:INFO: # loops 2
14:28:44:ST3_smx:INFO: Total # of broken channels: 0
14:28:44:ST3_smx:INFO: List of broken channels: []
14:28:44:ST3_smx:INFO: Total # of broken channels: 0
14:28:44:ST3_smx:INFO: List of broken channels: []
14:28:46:ST3_smx:INFO: chip: 7-6 47.250730 C 1159.654860 mV
14:28:46:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:28:46:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:28:46:ST3_smx:INFO: Electrons
14:28:46:ST3_smx:INFO: # loops 0
14:28:48:ST3_smx:INFO: # loops 1
14:28:50:ST3_smx:INFO: # loops 2
14:28:52:ST3_smx:INFO: Total # of broken channels: 0
14:28:52:ST3_smx:INFO: List of broken channels: []
14:28:52:ST3_smx:INFO: Total # of broken channels: 0
14:28:52:ST3_smx:INFO: List of broken channels: []
14:28:53:ST3_smx:INFO: chip: 14-7 31.389742 C 1224.468235 mV
14:28:53:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:28:53:ST3_discr_histo:WARNING: Not enough entries for fit!!!
14:28:53:ST3_smx:INFO: Electrons
14:28:53:ST3_smx:INFO: # loops 0
14:28:55:ST3_smx:INFO: # loops 1
14:28:57:ST3_smx:INFO: # loops 2
14:28:58:ST3_smx:INFO: Total # of broken channels: 0
14:28:58:ST3_smx:INFO: List of broken channels: []
14:28:58:ST3_smx:INFO: Total # of broken channels: 0
14:28:58:ST3_smx:INFO: List of broken channels: []
14:28:59:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:28:59:febtest:INFO: 01-00 | XA-000-09-004-005-008-016-12 | 47.3 | 1177.4
14:28:59:febtest:INFO: 08-01 | XA-000-09-004-005-014-015-14 | 34.6 | 1236.2
14:28:59:febtest:INFO: 03-02 | XA-000-09-004-005-005-016-11 | 34.6 | 1224.5
14:28:59:febtest:INFO: 10-03 | XA-000-09-004-005-011-015-05 | 40.9 | 1201.0
14:29:00:febtest:INFO: 05-04 | XA-000-09-004-005-002-016-03 | 34.6 | 1218.6
14:29:00:febtest:INFO: 12-05 | XA-000-09-004-005-008-015-11 | 44.1 | 1201.0
14:29:00:febtest:INFO: 07-06 | XA-000-09-004-005-002-015-04 | 47.3 | 1177.4
14:29:00:febtest:INFO: 14-07 | XA-000-09-004-005-005-015-12 | 31.4 | 1247.9
############################################################
# S U M M A R Y #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_03_19-14_27_35
OPERATOR : Benjamin;
SITE : KIT | SETUP : KIT_TEST_SETUP_1
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| FEB_SN : 3128| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['2.450', '1.5820', '1.850', '2.4400', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0030', '1.850', '2.3650', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9590', '1.850', '0.5253', '0.000', '0.0000', '0.000', '0.0000']