DTL-STS tests database

FEB_3194 07.07.25 14:29:51

link: XA-000-09-004-037-016-013-12
...SMX_1.root
link: XA-000-09-004-037-010-014-15
...SMX_3.root
link: XA-000-09-004-037-013-014-07
...SMX_5.root
link: XA-000-09-004-037-016-014-12
...SMX_7.root
link: XA-000-09-004-037-012-009-10
...SMX_0.root
link: XA-000-09-004-037-009-007-01
...SMX_2.root
link: XA-000-09-004-037-003-007-14
...SMX_4.root
link: XA-000-09-004-037-006-007-05
...SMX_6.root
link: XA-000-09-004-037-006-007-05
...VddmCSAstatus.root
Info
            14:29:51:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:29:51:ST3_Shared:INFO:	                       FEB-Microcable                       
14:29:51:ST3_Shared:INFO:	oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
14:29:51:febtest:INFO:	Testing FEB with SN 3194
14:29:52:smx_tester:INFO:	Scanning setup
14:29:52:elinks:INFO:	Disabling clock on downlink 0
14:29:52:elinks:INFO:	Disabling clock on downlink 1
14:29:52:elinks:INFO:	Disabling clock on downlink 2
14:29:52:elinks:INFO:	Disabling clock on downlink 3
14:29:52:elinks:INFO:	Disabling clock on downlink 4
14:29:52:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:29:52:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [0]
14:29:53:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:29:53:elinks:INFO:	Disabling clock on downlink 0
14:29:53:elinks:INFO:	Disabling clock on downlink 1
14:29:53:elinks:INFO:	Disabling clock on downlink 2
14:29:53:elinks:INFO:	Disabling clock on downlink 3
14:29:53:elinks:INFO:	Disabling clock on downlink 4
14:29:53:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:29:53:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:29:53:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 0
14:29:53:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 1
14:29:53:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 2
14:29:53:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 3
14:29:53:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 4
14:29:53:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 5
14:29:53:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 6
14:29:53:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 7
14:29:53:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 8
14:29:53:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 9
14:29:53:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 10
14:29:53:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 11
14:29:53:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 12
14:29:53:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 13
14:29:53:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 14
14:29:53:setup_element:INFO:	SOS detected for group 0, downlink 1, uplink 15
14:29:53:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:29:53:elinks:INFO:	Disabling clock on downlink 0
14:29:53:elinks:INFO:	Disabling clock on downlink 1
14:29:53:elinks:INFO:	Disabling clock on downlink 2
14:29:53:elinks:INFO:	Disabling clock on downlink 3
14:29:53:elinks:INFO:	Disabling clock on downlink 4
14:29:53:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:29:53:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [2]
14:29:53:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:29:53:elinks:INFO:	Disabling clock on downlink 0
14:29:53:elinks:INFO:	Disabling clock on downlink 1
14:29:53:elinks:INFO:	Disabling clock on downlink 2
14:29:53:elinks:INFO:	Disabling clock on downlink 3
14:29:53:elinks:INFO:	Disabling clock on downlink 4
14:29:53:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:29:53:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [3]
14:29:53:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:29:53:elinks:INFO:	Disabling clock on downlink 0
14:29:53:elinks:INFO:	Disabling clock on downlink 1
14:29:53:elinks:INFO:	Disabling clock on downlink 2
14:29:53:elinks:INFO:	Disabling clock on downlink 3
14:29:53:elinks:INFO:	Disabling clock on downlink 4
14:29:53:setup_element:INFO:	Checking SOS, encoding_mode: SOS
14:29:53:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [4]
14:29:53:setup_element:INFO:	Reassigning uplinks to uplinks which passed SOS detection
14:29:53:setup_element:INFO:	Scanning clock phase
14:29:53:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:29:53:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:29:53:setup_element:INFO:	Clock phase scan results for group 0, downlink 1
14:29:53:setup_element:INFO:	Eye window for uplink 0 : __________________________________________________________________________XXXXX_
Clock Delay: 36
14:29:53:setup_element:INFO:	Eye window for uplink 1 : __________________________________________________________________________XXXXX_
Clock Delay: 36
14:29:53:setup_element:INFO:	Eye window for uplink 2 : _________________________________________________________________________XXXXX__
Clock Delay: 35
14:29:53:setup_element:INFO:	Eye window for uplink 3 : _________________________________________________________________________XXXXX__
Clock Delay: 35
14:29:53:setup_element:INFO:	Eye window for uplink 4 : __________________________________________________________________________XXXXX_
Clock Delay: 36
14:29:53:setup_element:INFO:	Eye window for uplink 5 : __________________________________________________________________________XXXXX_
Clock Delay: 36
14:29:53:setup_element:INFO:	Eye window for uplink 6 : ________________________________________________________________________________
Clock Delay: 40
14:29:53:setup_element:INFO:	Eye window for uplink 7 : ________________________________________________________________________________
Clock Delay: 40
14:29:53:setup_element:INFO:	Eye window for uplink 8 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
14:29:53:setup_element:INFO:	Eye window for uplink 9 : _______________________________________________________________________XXXXXXX__
Clock Delay: 34
14:29:53:setup_element:INFO:	Eye window for uplink 10: ________________________________________________________________________XXXXX___
Clock Delay: 34
14:29:53:setup_element:INFO:	Eye window for uplink 11: ________________________________________________________________________XXXXX___
Clock Delay: 34
14:29:53:setup_element:INFO:	Eye window for uplink 12: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:29:53:setup_element:INFO:	Eye window for uplink 13: ________________________________________________________________________XXXXXX__
Clock Delay: 34
14:29:53:setup_element:INFO:	Eye window for uplink 14: __________________________________________________________________________XXXX__
Clock Delay: 35
14:29:53:setup_element:INFO:	Eye window for uplink 15: __________________________________________________________________________XXXX__
Clock Delay: 35
14:29:53:setup_element:INFO:	Setting the clock phase to 34 for group 0, downlink 1
14:29:53:setup_element:INFO:	Scanning data phases
14:29:53:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:29:54:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:29:59:setup_element:INFO:	Data phase scan results for group 0, downlink 1
14:29:59:setup_element:INFO:	Eye window for uplink 0 : _________XXXXX__________________________
Data delay found: 31
14:29:59:setup_element:INFO:	Eye window for uplink 1 : _______XXXXXX___________________________
Data delay found: 29
14:29:59:setup_element:INFO:	Eye window for uplink 2 : _________XXXXXX_________________________
Data delay found: 31
14:29:59:setup_element:INFO:	Eye window for uplink 3 : ________XXXXXX__________________________
Data delay found: 30
14:29:59:setup_element:INFO:	Eye window for uplink 4 : ________XXXXX___________________________
Data delay found: 30
14:29:59:setup_element:INFO:	Eye window for uplink 5 : ______XXXXXX____________________________
Data delay found: 28
14:29:59:setup_element:INFO:	Eye window for uplink 6 : _XXXX___________________________________
Data delay found: 22
14:29:59:setup_element:INFO:	Eye window for uplink 7 : XXX___________________________________XX
Data delay found: 20
14:29:59:setup_element:INFO:	Eye window for uplink 8 : _______________________XXXXXXXXXXXXXX___
Data delay found: 9
14:29:59:setup_element:INFO:	Eye window for uplink 9 : _______________________________XXXXX____
Data delay found: 13
14:29:59:setup_element:INFO:	Eye window for uplink 10: ______________________________XXXXX_____
Data delay found: 12
14:29:59:setup_element:INFO:	Eye window for uplink 11: ______________________________XXXXXX____
Data delay found: 12
14:29:59:setup_element:INFO:	Eye window for uplink 12: ______________________________XXXXX_____
Data delay found: 12
14:29:59:setup_element:INFO:	Eye window for uplink 13: _______________________________XXXX_____
Data delay found: 12
14:29:59:setup_element:INFO:	Eye window for uplink 14: _________________________________XXXX___
Data delay found: 14
14:29:59:setup_element:INFO:	Eye window for uplink 15: _________________________________XXXXXX_
Data delay found: 15
14:29:59:setup_element:INFO:	Setting the data phase to 31 for uplink 0
14:29:59:setup_element:INFO:	Setting the data phase to 29 for uplink 1
14:29:59:setup_element:INFO:	Setting the data phase to 31 for uplink 2
14:29:59:setup_element:INFO:	Setting the data phase to 30 for uplink 3
14:29:59:setup_element:INFO:	Setting the data phase to 30 for uplink 4
14:29:59:setup_element:INFO:	Setting the data phase to 28 for uplink 5
14:29:59:setup_element:INFO:	Setting the data phase to 22 for uplink 6
14:29:59:setup_element:INFO:	Setting the data phase to 20 for uplink 7
14:29:59:setup_element:INFO:	Setting the data phase to 9 for uplink 8
14:29:59:setup_element:INFO:	Setting the data phase to 13 for uplink 9
14:29:59:setup_element:INFO:	Setting the data phase to 12 for uplink 10
14:29:59:setup_element:INFO:	Setting the data phase to 12 for uplink 11
14:29:59:setup_element:INFO:	Setting the data phase to 12 for uplink 12
14:29:59:setup_element:INFO:	Setting the data phase to 12 for uplink 13
14:29:59:setup_element:INFO:	Setting the data phase to 14 for uplink 14
14:29:59:setup_element:INFO:	Setting the data phase to 15 for uplink 15
14:29:59:setup_element:INFO:	Beginning SMX ASICs map scan
14:29:59:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:29:59:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:29:59:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
14:29:59:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
14:29:59:uplink:INFO:	Setting uplinks mask [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
14:29:59:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 0, uplink 1
14:29:59:setup_element:INFO:	Adding ASIC 0x0, ASIC uplink 1, uplink 0
14:29:59:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 0, uplink 8
14:29:59:setup_element:INFO:	Adding ASIC 0x1, ASIC uplink 1, uplink 9
14:29:59:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 0, uplink 3
14:29:59:setup_element:INFO:	Adding ASIC 0x2, ASIC uplink 1, uplink 2
14:29:59:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 0, uplink 10
14:29:59:setup_element:INFO:	Adding ASIC 0x3, ASIC uplink 1, uplink 11
14:29:59:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 0, uplink 5
14:30:00:setup_element:INFO:	Adding ASIC 0x4, ASIC uplink 1, uplink 4
14:30:00:setup_element:INFO:	Adding ASIC 0x5, ASIC uplink 0, uplink 12
14:30:00:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 0, uplink 7
14:30:00:setup_element:INFO:	Adding ASIC 0x6, ASIC uplink 1, uplink 6
14:30:00:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 0, uplink 14
14:30:00:setup_element:INFO:	Adding ASIC 0x7, ASIC uplink 1, uplink 15
14:30:01:setup_element:INFO:	Performing Elink synchronization
14:30:01:master:INFO:	Setting encoding mode SOS for groups [0], downlinks [1]
14:30:01:master:INFO:	Setting encoding mode K.28.1 for groups [0], downlinks [1]
14:30:01:master:INFO:	Setting encoding mode EOS for groups [0], downlinks [1]
14:30:01:master:INFO:	Setting encoding mode FRAME for groups [0], downlinks [1]
14:30:01:setup_element:INFO:	Writing SMX Elink masks for group 0, downlink 1
14:30:01:uplink:INFO:	Enabling uplinks [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15]
|_________________________________________________________________________|
_addr_|_upli_|_dwnli_|_grp_|_uplinks_|_#uplinks_|_uplinks_map_
 0   | [0]  |   1   |  0  |   [1]   |    2    | [(0, 1), (1, 0)]
 1   | [0]  |   1   |  0  |   [8]   |    2    | [(0, 8), (1, 9)]
 2   | [0]  |   1   |  0  |   [3]   |    2    | [(0, 3), (1, 2)]
 3   | [0]  |   1   |  0  |  [10]   |    2    | [(0, 10), (1, 11)]
 4   | [0]  |   1   |  0  |   [5]   |    2    | [(0, 5), (1, 4)]
 5   | [0]  |   1   |  0  |  [12]   |    1    | [(0, 12)]
 6   | [0]  |   1   |  0  |   [7]   |    2    | [(0, 7), (1, 6)]
 7   | [0]  |   1   |  0  |  [14]   |    2    | [(0, 14), (1, 15)]
|_________________________________________________________________________|
14:30:02:febtest:INFO:	Init all SMX (CSA): 30
14:30:21:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:30:21:febtest:INFO:	01-00 | XA-000-09-004-037-012-009-10 |  21.9 | 1206.9
14:30:21:febtest:INFO:	08-01 | XA-000-09-004-037-016-013-12 |  25.1 | 1201.0
14:30:21:febtest:INFO:	03-02 | XA-000-09-004-037-009-007-01 |  28.2 | 1189.2
14:30:22:febtest:INFO:	10-03 | XA-000-09-004-037-010-014-15 |  44.1 | 1130.0
14:30:22:febtest:INFO:	05-04 | XA-000-09-004-037-003-007-14 |  25.1 | 1212.7
14:30:22:febtest:INFO:	12-05 | XA-000-09-004-037-013-014-07 |  34.6 | 1171.5
14:30:22:febtest:INFO:	07-06 | XA-000-09-004-037-006-007-05 |  28.2 | 1195.1
14:30:22:febtest:INFO:	14-07 | XA-000-09-004-037-016-014-12 |  18.7 | 1224.5
14:30:23:febtest:INFO:	Set all CSA to ZERO
FEB type: A FEB_A: 1 FEB_B: 0
14:30:25:ST3_smx:INFO:	chip: 1-0 	 21.902970 C 	 1218.600960 mV
14:30:25:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:30:25:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:30:25:ST3_smx:INFO:		Electrons
14:30:25:ST3_smx:INFO:	# loops 0
14:30:27:ST3_smx:INFO:	# loops 1
14:30:29:ST3_smx:INFO:	# loops 2
14:30:30:ST3_smx:INFO:	Total # of broken channels: 0
14:30:30:ST3_smx:INFO:	List of broken channels: []
14:30:30:ST3_smx:INFO:	Total # of broken channels: 0
14:30:30:ST3_smx:INFO:	List of broken channels: []
14:30:32:ST3_smx:INFO:	chip: 8-1 	 25.062742 C 	 1212.728715 mV
14:30:32:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:30:32:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:30:32:ST3_smx:INFO:		Electrons
14:30:32:ST3_smx:INFO:	# loops 0
14:30:34:ST3_smx:INFO:	# loops 1
14:30:35:ST3_smx:INFO:	# loops 2
14:30:37:ST3_smx:INFO:	Total # of broken channels: 0
14:30:37:ST3_smx:INFO:	List of broken channels: []
14:30:37:ST3_smx:INFO:	Total # of broken channels: 0
14:30:37:ST3_smx:INFO:	List of broken channels: []
14:30:39:ST3_smx:INFO:	chip: 3-2 	 28.225000 C 	 1200.969315 mV
14:30:39:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:30:39:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:30:39:ST3_smx:INFO:		Electrons
14:30:39:ST3_smx:INFO:	# loops 0
14:30:40:ST3_smx:INFO:	# loops 1
14:30:42:ST3_smx:INFO:	# loops 2
14:30:44:ST3_smx:INFO:	Total # of broken channels: 0
14:30:44:ST3_smx:INFO:	List of broken channels: []
14:30:44:ST3_smx:INFO:	Total # of broken channels: 0
14:30:44:ST3_smx:INFO:	List of broken channels: []
14:30:45:ST3_smx:INFO:	chip: 10-3 	 47.250730 C 	 1141.874115 mV
14:30:45:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:30:45:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:30:45:ST3_smx:INFO:		Electrons
14:30:45:ST3_smx:INFO:	# loops 0
14:30:47:ST3_smx:INFO:	# loops 1
14:30:49:ST3_smx:INFO:	# loops 2
14:30:50:ST3_smx:INFO:	Total # of broken channels: 0
14:30:50:ST3_smx:INFO:	List of broken channels: []
14:30:50:ST3_smx:INFO:	Total # of broken channels: 0
14:30:50:ST3_smx:INFO:	List of broken channels: []
14:30:52:ST3_smx:INFO:	chip: 5-4 	 25.062742 C 	 1218.600960 mV
14:30:52:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:30:52:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:30:52:ST3_smx:INFO:		Electrons
14:30:52:ST3_smx:INFO:	# loops 0
14:30:53:ST3_smx:INFO:	# loops 1
14:30:55:ST3_smx:INFO:	# loops 2
14:30:57:ST3_smx:INFO:	Total # of broken channels: 0
14:30:57:ST3_smx:INFO:	List of broken channels: []
14:30:57:ST3_smx:INFO:	Total # of broken channels: 0
14:30:57:ST3_smx:INFO:	List of broken channels: []
14:30:58:ST3_smx:INFO:	chip: 12-5 	 37.726682 C 	 1183.292940 mV
14:30:58:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:30:58:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:30:58:ST3_smx:INFO:		Electrons
14:30:58:ST3_smx:INFO:	# loops 0
14:31:00:ST3_smx:INFO:	# loops 1
14:31:01:ST3_smx:INFO:	# loops 2
14:31:03:ST3_smx:INFO:	Total # of broken channels: 0
14:31:03:ST3_smx:INFO:	List of broken channels: []
14:31:03:ST3_smx:INFO:	Total # of broken channels: 0
14:31:03:ST3_smx:INFO:	List of broken channels: []
14:31:04:ST3_smx:INFO:	chip: 7-6 	 31.389742 C 	 1206.851500 mV
14:31:04:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:31:04:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:31:04:ST3_smx:INFO:		Electrons
14:31:04:ST3_smx:INFO:	# loops 0
14:31:06:ST3_smx:INFO:	# loops 1
14:31:07:ST3_smx:INFO:	# loops 2
14:31:09:ST3_smx:INFO:	Total # of broken channels: 0
14:31:09:ST3_smx:INFO:	List of broken channels: []
14:31:09:ST3_smx:INFO:	Total # of broken channels: 0
14:31:09:ST3_smx:INFO:	List of broken channels: []
14:31:11:ST3_smx:INFO:	chip: 14-7 	 21.902970 C 	 1236.187875 mV
14:31:11:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:31:11:ST3_discr_histo:WARNING:	Not enough entries for fit!!!
14:31:11:ST3_smx:INFO:		Electrons
14:31:11:ST3_smx:INFO:	# loops 0
14:31:12:ST3_smx:INFO:	# loops 1
14:31:14:ST3_smx:INFO:	# loops 2
14:31:16:ST3_smx:INFO:	Total # of broken channels: 0
14:31:16:ST3_smx:INFO:	List of broken channels: []
14:31:16:ST3_smx:INFO:	Total # of broken channels: 0
14:31:16:ST3_smx:INFO:	List of broken channels: []
14:31:16:febtest:INFO:	_Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
14:31:16:febtest:INFO:	01-00 | XA-000-09-004-037-012-009-10 |  25.1 | 1242.0
14:31:16:febtest:INFO:	08-01 | XA-000-09-004-037-016-013-12 |  25.1 | 1236.2
14:31:17:febtest:INFO:	03-02 | XA-000-09-004-037-009-007-01 |  31.4 | 1218.6
14:31:17:febtest:INFO:	10-03 | XA-000-09-004-037-010-014-15 |  47.3 | 1165.6
14:31:17:febtest:INFO:	05-04 | XA-000-09-004-037-003-007-14 |  25.1 | 1242.0
14:31:17:febtest:INFO:	12-05 | XA-000-09-004-037-013-014-07 |  37.7 | 1206.9
14:31:18:febtest:INFO:	07-06 | XA-000-09-004-037-006-007-05 |  31.4 | 1224.5
14:31:18:febtest:INFO:	14-07 | XA-000-09-004-037-016-014-12 |  21.9 | 1253.7
############################################################
#                   S U M M A R Y                          #
############################################################
{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

{'CSA_FRONT': 31, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 31, 'AMP_CAL': 0, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 31, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================

############################################################
#                   S U M M A R Y                          #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 25_07_07-14_29_51
OPERATOR  : Benjamin; 
SITE : KIT | SETUP : KIT_TEST_SETUP_1
------------------------------------------------------------
| FEB_SN : 3194| FEB_TYPE : 8.2| FEB_UPLINKS : 2| FEB_A
------------------------------------------------------------
------------------------------------------------------------
VI_before_Init : ['2.450', '1.9990', '1.850', '2.3060', '0.000', '0.0000', '0.000', '0.0000']
VI_after__Init : ['2.450', '2.0640', '1.850', '2.4110', '0.000', '0.0000', '0.000', '0.0000']
VI_at__the_End : ['2.450', '1.9860', '1.850', '0.5236', '0.000', '0.0000', '0.000', '0.0000']
Comment