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FEB_4008 21.03.24 09:16:50
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09:16:50:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:16:50:ST3_Shared:INFO: FEB-ASIC
09:16:50:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
09:16:50:febtest:INFO: Testing FEB with SN 4008
09:16:53:smx_tester:INFO: Scanning setup
09:16:53:elinks:INFO: Disabling clock on downlink 0
09:16:53:elinks:INFO: Disabling clock on downlink 1
09:16:53:elinks:INFO: Disabling clock on downlink 2
09:16:53:elinks:INFO: Disabling clock on downlink 3
09:16:53:elinks:INFO: Disabling clock on downlink 4
09:16:53:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:16:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
09:16:53:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:16:53:elinks:INFO: Disabling clock on downlink 0
09:16:53:elinks:INFO: Disabling clock on downlink 1
09:16:53:elinks:INFO: Disabling clock on downlink 2
09:16:53:elinks:INFO: Disabling clock on downlink 3
09:16:53:elinks:INFO: Disabling clock on downlink 4
09:16:53:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:16:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
09:16:53:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:16:53:elinks:INFO: Disabling clock on downlink 0
09:16:53:elinks:INFO: Disabling clock on downlink 1
09:16:53:elinks:INFO: Disabling clock on downlink 2
09:16:53:elinks:INFO: Disabling clock on downlink 3
09:16:53:elinks:INFO: Disabling clock on downlink 4
09:16:53:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:16:53:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
09:16:53:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
09:16:53:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
09:16:53:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
09:16:53:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
09:16:53:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
09:16:53:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
09:16:53:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
09:16:53:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
09:16:53:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
09:16:53:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
09:16:53:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
09:16:53:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
09:16:53:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
09:16:53:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
09:16:53:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
09:16:53:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
09:16:54:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:16:54:elinks:INFO: Disabling clock on downlink 0
09:16:54:elinks:INFO: Disabling clock on downlink 1
09:16:54:elinks:INFO: Disabling clock on downlink 2
09:16:54:elinks:INFO: Disabling clock on downlink 3
09:16:54:elinks:INFO: Disabling clock on downlink 4
09:16:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:16:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
09:16:54:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:16:54:elinks:INFO: Disabling clock on downlink 0
09:16:54:elinks:INFO: Disabling clock on downlink 1
09:16:54:elinks:INFO: Disabling clock on downlink 2
09:16:54:elinks:INFO: Disabling clock on downlink 3
09:16:54:elinks:INFO: Disabling clock on downlink 4
09:16:54:setup_element:INFO: Checking SOS, encoding_mode: SOS
09:16:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
09:16:54:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
09:16:54:setup_element:INFO: Scanning clock phase
09:16:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
09:16:54:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:16:54:setup_element:INFO: Clock phase scan results for group 0, downlink 2
09:16:54:setup_element:INFO: Eye window for uplink 16: ___________________________________________________________________XXXXX________
Clock Delay: 29
09:16:54:setup_element:INFO: Eye window for uplink 17: ___________________________________________________________________XXXXX________
Clock Delay: 29
09:16:54:setup_element:INFO: Eye window for uplink 18: __________________________________________________________________XXXXX_________
Clock Delay: 28
09:16:54:setup_element:INFO: Eye window for uplink 19: __________________________________________________________________XXXXX_________
Clock Delay: 28
09:16:54:setup_element:INFO: Eye window for uplink 20: __________________________________________________________________XXXXX_________
Clock Delay: 28
09:16:54:setup_element:INFO: Eye window for uplink 21: __________________________________________________________________XXXXX_________
Clock Delay: 28
09:16:54:setup_element:INFO: Eye window for uplink 22: ____________________________________________________________________XXXXXX______
Clock Delay: 30
09:16:54:setup_element:INFO: Eye window for uplink 23: ____________________________________________________________________XXXXXX______
Clock Delay: 30
09:16:54:setup_element:INFO: Eye window for uplink 24: __________________________________________________________________XXXXX_________
Clock Delay: 28
09:16:54:setup_element:INFO: Eye window for uplink 25: __________________________________________________________________XXXXX_________
Clock Delay: 28
09:16:54:setup_element:INFO: Eye window for uplink 26: __________________________________________________________________XXXXXX________
Clock Delay: 28
09:16:54:setup_element:INFO: Eye window for uplink 27: __________________________________________________________________XXXXXX________
Clock Delay: 28
09:16:54:setup_element:INFO: Eye window for uplink 28: ________________________________________________________________________________
Clock Delay: 40
09:16:54:setup_element:INFO: Eye window for uplink 29: ________________________________________________________________________________
Clock Delay: 40
09:16:54:setup_element:INFO: Eye window for uplink 30: ___________________________________________________________________XXXX_________
Clock Delay: 28
09:16:54:setup_element:INFO: Eye window for uplink 31: ___________________________________________________________________XXXX_________
Clock Delay: 28
09:16:54:setup_element:INFO: Setting the clock phase to 29 for group 0, downlink 2
09:16:54:setup_element:INFO: Scanning data phases
09:16:54:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
09:16:54:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:16:59:setup_element:INFO: Data phase scan results for group 0, downlink 2
09:16:59:setup_element:INFO: Eye window for uplink 16: _________________________XXXXXX_________
Data delay found: 7
09:16:59:setup_element:INFO: Eye window for uplink 17: ______________________XXXXX_____________
Data delay found: 4
09:16:59:setup_element:INFO: Eye window for uplink 18: _______________________XXXXX____________
Data delay found: 5
09:16:59:setup_element:INFO: Eye window for uplink 19: ___________________XXXXXXX______________
Data delay found: 2
09:16:59:setup_element:INFO: Eye window for uplink 20: _________________________XXXXXX_________
Data delay found: 7
09:16:59:setup_element:INFO: Eye window for uplink 21: ________________________XXXXXX__________
Data delay found: 6
09:16:59:setup_element:INFO: Eye window for uplink 22: _____________________________XXXXX______
Data delay found: 11
09:16:59:setup_element:INFO: Eye window for uplink 23: _________________________XXXXXX_________
Data delay found: 7
09:16:59:setup_element:INFO: Eye window for uplink 24: X_______________________________XXXXXXXX
Data delay found: 16
09:16:59:setup_element:INFO: Eye window for uplink 25: XXXX_________________________________XXX
Data delay found: 20
09:16:59:setup_element:INFO: Eye window for uplink 26: XX_______________________________XXXXXXX
Data delay found: 17
09:16:59:setup_element:INFO: Eye window for uplink 27: XXXXXXX________________________________X
Data delay found: 22
09:16:59:setup_element:INFO: Eye window for uplink 28: __XXXXXXX_______________________________
Data delay found: 25
09:16:59:setup_element:INFO: Eye window for uplink 29: _____XXXXXXX____________________________
Data delay found: 28
09:16:59:setup_element:INFO: Eye window for uplink 30: X_XXXXXXXX______________________________
Data delay found: 24
09:16:59:setup_element:INFO: Eye window for uplink 31: ___XXXXXXX______________________________
Data delay found: 26
09:16:59:setup_element:INFO: Setting the data phase to 7 for uplink 16
09:16:59:setup_element:INFO: Setting the data phase to 4 for uplink 17
09:16:59:setup_element:INFO: Setting the data phase to 5 for uplink 18
09:16:59:setup_element:INFO: Setting the data phase to 2 for uplink 19
09:16:59:setup_element:INFO: Setting the data phase to 7 for uplink 20
09:16:59:setup_element:INFO: Setting the data phase to 6 for uplink 21
09:16:59:setup_element:INFO: Setting the data phase to 11 for uplink 22
09:16:59:setup_element:INFO: Setting the data phase to 7 for uplink 23
09:16:59:setup_element:INFO: Setting the data phase to 16 for uplink 24
09:16:59:setup_element:INFO: Setting the data phase to 20 for uplink 25
09:16:59:setup_element:INFO: Setting the data phase to 17 for uplink 26
09:16:59:setup_element:INFO: Setting the data phase to 22 for uplink 27
09:16:59:setup_element:INFO: Setting the data phase to 25 for uplink 28
09:16:59:setup_element:INFO: Setting the data phase to 28 for uplink 29
09:16:59:setup_element:INFO: Setting the data phase to 24 for uplink 30
09:16:59:setup_element:INFO: Setting the data phase to 26 for uplink 31
09:16:59:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 29
Window Length: 72
Eye Windows:
Uplink 16: ___________________________________________________________________XXXXX________
Uplink 17: ___________________________________________________________________XXXXX________
Uplink 18: __________________________________________________________________XXXXX_________
Uplink 19: __________________________________________________________________XXXXX_________
Uplink 20: __________________________________________________________________XXXXX_________
Uplink 21: __________________________________________________________________XXXXX_________
Uplink 22: ____________________________________________________________________XXXXXX______
Uplink 23: ____________________________________________________________________XXXXXX______
Uplink 24: __________________________________________________________________XXXXX_________
Uplink 25: __________________________________________________________________XXXXX_________
Uplink 26: __________________________________________________________________XXXXXX________
Uplink 27: __________________________________________________________________XXXXXX________
Uplink 28: ________________________________________________________________________________
Uplink 29: ________________________________________________________________________________
Uplink 30: ___________________________________________________________________XXXX_________
Uplink 31: ___________________________________________________________________XXXX_________
Data phase characteristics:
Uplink 16:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 17:
Optimal Phase: 4
Window Length: 35
Eye Window: ______________________XXXXX_____________
Uplink 18:
Optimal Phase: 5
Window Length: 35
Eye Window: _______________________XXXXX____________
Uplink 19:
Optimal Phase: 2
Window Length: 33
Eye Window: ___________________XXXXXXX______________
Uplink 20:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 21:
Optimal Phase: 6
Window Length: 34
Eye Window: ________________________XXXXXX__________
Uplink 22:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 23:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 24:
Optimal Phase: 16
Window Length: 31
Eye Window: X_______________________________XXXXXXXX
Uplink 25:
Optimal Phase: 20
Window Length: 33
Eye Window: XXXX_________________________________XXX
Uplink 26:
Optimal Phase: 17
Window Length: 31
Eye Window: XX_______________________________XXXXXXX
Uplink 27:
Optimal Phase: 22
Window Length: 32
Eye Window: XXXXXXX________________________________X
Uplink 28:
Optimal Phase: 25
Window Length: 33
Eye Window: __XXXXXXX_______________________________
Uplink 29:
Optimal Phase: 28
Window Length: 33
Eye Window: _____XXXXXXX____________________________
Uplink 30:
Optimal Phase: 24
Window Length: 30
Eye Window: X_XXXXXXXX______________________________
Uplink 31:
Optimal Phase: 26
Window Length: 33
Eye Window: ___XXXXXXX______________________________
]
09:16:59:setup_element:INFO: Beginning SMX ASICs map scan
09:16:59:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
09:16:59:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:16:59:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
09:17:00:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
09:17:00:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
09:17:00:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
09:17:00:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
09:17:00:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
09:17:00:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
09:17:00:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
09:17:00:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
09:17:00:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
09:17:00:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
09:17:00:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
09:17:00:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
09:17:00:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
09:17:00:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
09:17:01:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
09:17:01:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
09:17:01:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
09:17:01:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
09:17:02:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 29
Window Length: 72
Eye Windows:
Uplink 16: ___________________________________________________________________XXXXX________
Uplink 17: ___________________________________________________________________XXXXX________
Uplink 18: __________________________________________________________________XXXXX_________
Uplink 19: __________________________________________________________________XXXXX_________
Uplink 20: __________________________________________________________________XXXXX_________
Uplink 21: __________________________________________________________________XXXXX_________
Uplink 22: ____________________________________________________________________XXXXXX______
Uplink 23: ____________________________________________________________________XXXXXX______
Uplink 24: __________________________________________________________________XXXXX_________
Uplink 25: __________________________________________________________________XXXXX_________
Uplink 26: __________________________________________________________________XXXXXX________
Uplink 27: __________________________________________________________________XXXXXX________
Uplink 28: ________________________________________________________________________________
Uplink 29: ________________________________________________________________________________
Uplink 30: ___________________________________________________________________XXXX_________
Uplink 31: ___________________________________________________________________XXXX_________
Data phase characteristics:
Uplink 16:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 17:
Optimal Phase: 4
Window Length: 35
Eye Window: ______________________XXXXX_____________
Uplink 18:
Optimal Phase: 5
Window Length: 35
Eye Window: _______________________XXXXX____________
Uplink 19:
Optimal Phase: 2
Window Length: 33
Eye Window: ___________________XXXXXXX______________
Uplink 20:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 21:
Optimal Phase: 6
Window Length: 34
Eye Window: ________________________XXXXXX__________
Uplink 22:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 23:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 24:
Optimal Phase: 16
Window Length: 31
Eye Window: X_______________________________XXXXXXXX
Uplink 25:
Optimal Phase: 20
Window Length: 33
Eye Window: XXXX_________________________________XXX
Uplink 26:
Optimal Phase: 17
Window Length: 31
Eye Window: XX_______________________________XXXXXXX
Uplink 27:
Optimal Phase: 22
Window Length: 32
Eye Window: XXXXXXX________________________________X
Uplink 28:
Optimal Phase: 25
Window Length: 33
Eye Window: __XXXXXXX_______________________________
Uplink 29:
Optimal Phase: 28
Window Length: 33
Eye Window: _____XXXXXXX____________________________
Uplink 30:
Optimal Phase: 24
Window Length: 30
Eye Window: X_XXXXXXXX______________________________
Uplink 31:
Optimal Phase: 26
Window Length: 33
Eye Window: ___XXXXXXX______________________________
09:17:02:setup_element:INFO: Performing Elink synchronization
09:17:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
09:17:02:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
09:17:02:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
09:17:02:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
09:17:02:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
09:17:02:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
09:17:02:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
FEB type: B FEB_A: 0 FEB_B: 1
09:17:04:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:17:04:febtest:INFO: 23-00 | XA-000-08-003-000-001-046-07 | -126.8 | 1578.5
09:17:04:febtest:INFO: 30-01 | XA-000-08-003-000-001-048-00 | -114.7 | 1578.5
09:17:04:febtest:INFO: 21-02 | XA-000-08-003-000-001-041-07 | -123.8 | 1578.5
09:17:04:febtest:INFO: 28-03 | XA-000-08-003-000-001-061-00 | -108.6 | 1578.5
09:17:05:febtest:INFO: 19-04 | XA-000-08-003-000-001-034-07 | -90.2 | 1578.5
09:17:05:febtest:INFO: 26-05 | XA-000-08-003-000-001-054-00 | -114.7 | 1578.5
09:17:05:febtest:INFO: 17-06 | XA-000-08-003-000-001-033-07 | -84.1 | 1578.5
09:17:05:febtest:INFO: 24-07 | XA-000-08-003-000-001-059-00 | -96.3 | 1578.5
09:17:05:ST3_smx:INFO: Configuring SMX FAST
09:17:08:ST3_smx:INFO: chip: 23-0 -99.389858 C 1578.532875 mV
09:17:08:ST3_smx:INFO: Electrons
09:17:08:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
09:17:10:ST3_smx:INFO: ----> Checking Analog response
09:17:10:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:17:10:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:17:10:ST3_smx:INFO: Total # broken ch: 256
09:17:10:ST3_smx:INFO: List FAST: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127]
09:17:10:ST3_smx:INFO: List SLOW: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127]
09:17:10:ST3_smx:INFO: Holes
09:17:10:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
09:17:13:ST3_smx:INFO: ----> Checking Analog response
09:17:13:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:17:13:ST3_discr_histo:WARNING: Not enough entries for fit!!!
09:17:13:ST3_smx:INFO: Total # broken ch: 256
09:17:13:ST3_smx:INFO: List FAST: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127]
09:17:13:ST3_smx:INFO: List SLOW: [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107, 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119, 120, 121, 122, 123, 124, 125, 126, 127]
09:17:13:ST3_smx:INFO: Configuring SMX FAST
09:17:16:ST3_smx:INFO: chip: 30-1 21.902970 C 1265.400000 mV
09:17:16:ST3_smx:INFO: Electrons
09:17:16:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
09:17:19:ST3_smx:INFO: ----> Checking Analog response
09:17:19:ST3_smx:INFO: ----> Checking broken channels
09:17:19:ST3_smx:INFO: Total # broken ch: 4
09:17:19:ST3_smx:INFO: List FAST: [13, 44, 61, 117]
09:17:19:ST3_smx:INFO: List SLOW: []
09:17:19:ST3_smx:INFO: Holes
09:17:19:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
09:17:22:ST3_smx:INFO: ----> Checking Analog response
09:17:22:ST3_smx:INFO: ----> Checking broken channels
09:17:22:ST3_smx:INFO: Total # broken ch: 4
09:17:22:ST3_smx:INFO: List FAST: [13, 44, 61, 117]
09:17:22:ST3_smx:INFO: List SLOW: []
09:17:23:ST3_smx:INFO: Configuring SMX FAST
09:17:25:ST3_smx:INFO: chip: 21-2 9.288730 C 1311.880960 mV
09:17:25:ST3_smx:INFO: Electrons
09:17:25:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
09:17:28:ST3_smx:INFO: ----> Checking Analog response
09:17:28:ST3_smx:INFO: ----> Checking broken channels
09:17:28:ST3_smx:INFO: Total # broken ch: 7
09:17:28:ST3_smx:INFO: List FAST: [4, 16, 40, 65, 75, 92, 93]
09:17:28:ST3_smx:INFO: List SLOW: []
09:17:28:ST3_smx:INFO: Holes
09:17:28:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
09:17:30:ST3_smx:INFO: ----> Checking Analog response
09:17:30:ST3_smx:INFO: ----> Checking broken channels
09:17:31:ST3_smx:INFO: Total # broken ch: 7
09:17:31:ST3_smx:INFO: List FAST: [4, 16, 40, 65, 75, 92, 93]
09:17:31:ST3_smx:INFO: List SLOW: []
09:17:31:ST3_smx:INFO: Configuring SMX FAST
09:17:34:ST3_smx:INFO: chip: 28-3 28.225000 C 1242.040240 mV
09:17:34:ST3_smx:INFO: Electrons
09:17:34:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
09:17:37:ST3_smx:INFO: ----> Checking Analog response
09:17:37:ST3_smx:INFO: ----> Checking broken channels
09:17:37:ST3_smx:INFO: Total # broken ch: 0
09:17:37:ST3_smx:INFO: List FAST: []
09:17:37:ST3_smx:INFO: List SLOW: []
09:17:37:ST3_smx:INFO: Holes
09:17:37:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
09:17:39:ST3_smx:INFO: ----> Checking Analog response
09:17:39:ST3_smx:INFO: ----> Checking broken channels
09:17:40:ST3_smx:INFO: Total # broken ch: 0
09:17:40:ST3_smx:INFO: List FAST: []
09:17:40:ST3_smx:INFO: List SLOW: []
09:17:40:ST3_smx:INFO: Configuring SMX FAST
09:17:43:ST3_smx:INFO: chip: 19-4 37.726682 C 1224.468235 mV
09:17:43:ST3_smx:INFO: Electrons
09:17:43:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
09:17:45:ST3_smx:INFO: ----> Checking Analog response
09:17:45:ST3_smx:INFO: ----> Checking broken channels
09:17:46:ST3_smx:INFO: Total # broken ch: 4
09:17:46:ST3_smx:INFO: List FAST: [8, 101, 117, 124]
09:17:46:ST3_smx:INFO: List SLOW: []
09:17:46:ST3_smx:INFO: Holes
09:17:46:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
09:17:48:ST3_smx:INFO: ----> Checking Analog response
09:17:48:ST3_smx:INFO: ----> Checking broken channels
09:17:49:ST3_smx:INFO: Total # broken ch: 4
09:17:49:ST3_smx:INFO: List FAST: [8, 101, 117, 124]
09:17:49:ST3_smx:INFO: List SLOW: []
09:17:49:ST3_smx:INFO: Configuring SMX FAST
09:17:52:ST3_smx:INFO: chip: 26-5 31.389742 C 1230.330540 mV
09:17:52:ST3_smx:INFO: Electrons
09:17:52:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
09:17:54:ST3_smx:INFO: ----> Checking Analog response
09:17:54:ST3_smx:INFO: ----> Checking broken channels
09:17:55:ST3_smx:INFO: Total # broken ch: 2
09:17:55:ST3_smx:INFO: List FAST: [42, 111]
09:17:55:ST3_smx:INFO: List SLOW: []
09:17:55:ST3_smx:INFO: Holes
09:17:55:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
09:17:57:ST3_smx:INFO: ----> Checking Analog response
09:17:57:ST3_smx:INFO: ----> Checking broken channels
09:17:58:ST3_smx:INFO: Total # broken ch: 2
09:17:58:ST3_smx:INFO: List FAST: [42, 111]
09:17:58:ST3_smx:INFO: List SLOW: []
09:17:58:ST3_smx:INFO: Configuring SMX FAST
09:18:00:ST3_smx:INFO: chip: 17-6 34.556970 C 1230.330540 mV
09:18:00:ST3_smx:INFO: Electrons
09:18:00:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
09:18:03:ST3_smx:INFO: ----> Checking Analog response
09:18:03:ST3_smx:INFO: ----> Checking broken channels
09:18:03:ST3_smx:INFO: Total # broken ch: 1
09:18:03:ST3_smx:INFO: List FAST: [101]
09:18:03:ST3_smx:INFO: List SLOW: []
09:18:03:ST3_smx:INFO: Holes
09:18:03:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
09:18:06:ST3_smx:INFO: ----> Checking Analog response
09:18:06:ST3_smx:INFO: ----> Checking broken channels
09:18:06:ST3_smx:INFO: Total # broken ch: 1
09:18:06:ST3_smx:INFO: List FAST: [101]
09:18:06:ST3_smx:INFO: List SLOW: []
09:18:07:ST3_smx:INFO: Configuring SMX FAST
09:18:09:ST3_smx:INFO: chip: 24-7 34.556970 C 1230.330540 mV
09:18:09:ST3_smx:INFO: Electrons
09:18:09:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
09:18:12:ST3_smx:INFO: ----> Checking Analog response
09:18:12:ST3_smx:INFO: ----> Checking broken channels
09:18:12:ST3_smx:INFO: Total # broken ch: 3
09:18:12:ST3_smx:INFO: List FAST: [99, 102, 106]
09:18:12:ST3_smx:INFO: List SLOW: []
09:18:12:ST3_smx:INFO: Holes
09:18:12:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
09:18:15:ST3_smx:INFO: ----> Checking Analog response
09:18:15:ST3_smx:INFO: ----> Checking broken channels
09:18:15:ST3_smx:INFO: Total # broken ch: 3
09:18:15:ST3_smx:INFO: List FAST: [99, 102, 106]
09:18:15:ST3_smx:INFO: List SLOW: []
09:18:16:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
09:18:16:febtest:INFO: 23-00 | XA-000-08-003-000-001-046-07 | 12.4 | 1288.7
09:18:16:febtest:INFO: 30-01 | XA-000-08-003-000-001-048-00 | 21.9 | 1277.1
09:18:16:febtest:INFO: 21-02 | XA-000-08-003-000-001-041-07 | 9.3 | 1311.9
09:18:17:febtest:INFO: 28-03 | XA-000-08-003-000-001-061-00 | 28.2 | 1242.0
09:18:17:febtest:INFO: 19-04 | XA-000-08-003-000-001-034-07 | 37.7 | 1224.5
09:18:17:febtest:INFO: 26-05 | XA-000-08-003-000-001-054-00 | 34.6 | 1224.5
09:18:17:febtest:INFO: 17-06 | XA-000-08-003-000-001-033-07 | 34.6 | 1224.5
09:18:17:febtest:INFO: 24-07 | XA-000-08-003-000-001-059-00 | 34.6 | 1224.5
############################################################
# S U M M A R Y #
############################################################
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 24_03_21-09_16_50
OPERATOR : Henrik;
SITE : KIT
SETUP : KIT_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME :
FEB_SN : 4008
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 0
FEB_B : 1
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.202', '2.1570', '2.800', '1.7910']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.200', '1.8010', '2.800', '0.3342']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.200', '1.8010', '2.800', '0.3258']