Go Back
FEB_4015 23.04.24 10:49:57
TextEdit.txt
10:49:57:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:49:57:ST3_Shared:INFO: FEB-ASIC
10:49:57:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
10:49:57:febtest:INFO: Testing FEB with SN 4015
10:50:00:smx_tester:INFO: Scanning setup
10:50:00:elinks:INFO: Disabling clock on downlink 0
10:50:00:elinks:INFO: Disabling clock on downlink 1
10:50:00:elinks:INFO: Disabling clock on downlink 2
10:50:00:elinks:INFO: Disabling clock on downlink 3
10:50:00:elinks:INFO: Disabling clock on downlink 4
10:50:00:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:50:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
10:50:00:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:50:00:elinks:INFO: Disabling clock on downlink 0
10:50:00:elinks:INFO: Disabling clock on downlink 1
10:50:00:elinks:INFO: Disabling clock on downlink 2
10:50:00:elinks:INFO: Disabling clock on downlink 3
10:50:00:elinks:INFO: Disabling clock on downlink 4
10:50:00:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:50:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
10:50:00:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:50:00:elinks:INFO: Disabling clock on downlink 0
10:50:00:elinks:INFO: Disabling clock on downlink 1
10:50:00:elinks:INFO: Disabling clock on downlink 2
10:50:00:elinks:INFO: Disabling clock on downlink 3
10:50:00:elinks:INFO: Disabling clock on downlink 4
10:50:00:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:50:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:50:00:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 16
10:50:00:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 17
10:50:00:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 18
10:50:00:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 19
10:50:00:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 20
10:50:00:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 21
10:50:00:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 22
10:50:00:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 23
10:50:00:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
10:50:00:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
10:50:00:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
10:50:00:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
10:50:00:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
10:50:00:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
10:50:00:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
10:50:00:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
10:50:00:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:50:00:elinks:INFO: Disabling clock on downlink 0
10:50:00:elinks:INFO: Disabling clock on downlink 1
10:50:00:elinks:INFO: Disabling clock on downlink 2
10:50:00:elinks:INFO: Disabling clock on downlink 3
10:50:00:elinks:INFO: Disabling clock on downlink 4
10:50:00:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:50:00:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
10:50:00:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:50:00:elinks:INFO: Disabling clock on downlink 0
10:50:01:elinks:INFO: Disabling clock on downlink 1
10:50:01:elinks:INFO: Disabling clock on downlink 2
10:50:01:elinks:INFO: Disabling clock on downlink 3
10:50:01:elinks:INFO: Disabling clock on downlink 4
10:50:01:setup_element:INFO: Checking SOS, encoding_mode: SOS
10:50:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
10:50:01:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
10:50:01:setup_element:INFO: Scanning clock phase
10:50:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:50:01:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:50:01:setup_element:INFO: Clock phase scan results for group 0, downlink 2
10:50:01:setup_element:INFO: Eye window for uplink 16: ______________________________________________________________________XXXXX_____
Clock Delay: 32
10:50:01:setup_element:INFO: Eye window for uplink 17: ______________________________________________________________________XXXXX_____
Clock Delay: 32
10:50:01:setup_element:INFO: Eye window for uplink 18: ______________________________________________________________________XXXXX_____
Clock Delay: 32
10:50:01:setup_element:INFO: Eye window for uplink 19: ______________________________________________________________________XXXXX_____
Clock Delay: 32
10:50:01:setup_element:INFO: Eye window for uplink 20: ______________________________________________________________________XXXXX_____
Clock Delay: 32
10:50:01:setup_element:INFO: Eye window for uplink 21: ______________________________________________________________________XXXXX_____
Clock Delay: 32
10:50:01:setup_element:INFO: Eye window for uplink 22: ________________________________________________________________________XXXXX___
Clock Delay: 34
10:50:01:setup_element:INFO: Eye window for uplink 23: ________________________________________________________________________XXXXX___
Clock Delay: 34
10:50:01:setup_element:INFO: Eye window for uplink 24: _______________________________________________________________________XXXX_____
Clock Delay: 32
10:50:01:setup_element:INFO: Eye window for uplink 25: _______________________________________________________________________XXXX_____
Clock Delay: 32
10:50:01:setup_element:INFO: Eye window for uplink 26: ______________________________________________________________________XXXXX_____
Clock Delay: 32
10:50:01:setup_element:INFO: Eye window for uplink 27: ______________________________________________________________________XXXXX_____
Clock Delay: 32
10:50:01:setup_element:INFO: Eye window for uplink 28: _______________________________________________________________________XXXXX____
Clock Delay: 33
10:50:01:setup_element:INFO: Eye window for uplink 29: _______________________________________________________________________XXXXX____
Clock Delay: 33
10:50:01:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________________XXXXXX___
Clock Delay: 33
10:50:01:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________________XXXXXX___
Clock Delay: 33
10:50:01:setup_element:INFO: Setting the clock phase to 33 for group 0, downlink 2
10:50:01:setup_element:INFO: Scanning data phases
10:50:01:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:50:01:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:50:06:setup_element:INFO: Data phase scan results for group 0, downlink 2
10:50:06:setup_element:INFO: Eye window for uplink 16: ______________________________XXXXX_____
Data delay found: 12
10:50:06:setup_element:INFO: Eye window for uplink 17: ___________________________XXXX_________
Data delay found: 8
10:50:06:setup_element:INFO: Eye window for uplink 18: _____________________________XXXXX______
Data delay found: 11
10:50:06:setup_element:INFO: Eye window for uplink 19: _________________________XXXXXX_________
Data delay found: 7
10:50:06:setup_element:INFO: Eye window for uplink 20: _____________________________XXXXX______
Data delay found: 11
10:50:06:setup_element:INFO: Eye window for uplink 21: ____________________________XXXXX_______
Data delay found: 10
10:50:06:setup_element:INFO: Eye window for uplink 22: __________________________________XXXX__
Data delay found: 15
10:50:06:setup_element:INFO: Eye window for uplink 23: ______________________________XXXX______
Data delay found: 11
10:50:06:setup_element:INFO: Eye window for uplink 24: XXXXX________________________________XXX
Data delay found: 20
10:50:06:setup_element:INFO: Eye window for uplink 25: __XXXXXX________________________________
Data delay found: 24
10:50:06:setup_element:INFO: Eye window for uplink 26: XXXXX_________________________________XX
Data delay found: 21
10:50:06:setup_element:INFO: Eye window for uplink 27: ___XXXXXXX______________________________
Data delay found: 26
10:50:06:setup_element:INFO: Eye window for uplink 28: ________XXXX____________________________
Data delay found: 29
10:50:06:setup_element:INFO: Eye window for uplink 29: __________XXXXX_________________________
Data delay found: 32
10:50:06:setup_element:INFO: Eye window for uplink 30: _______XXXXXXX__________________________
Data delay found: 30
10:50:06:setup_element:INFO: Eye window for uplink 31: ________XXXXX___________________________
Data delay found: 30
10:50:06:setup_element:INFO: Setting the data phase to 12 for uplink 16
10:50:06:setup_element:INFO: Setting the data phase to 8 for uplink 17
10:50:06:setup_element:INFO: Setting the data phase to 11 for uplink 18
10:50:06:setup_element:INFO: Setting the data phase to 7 for uplink 19
10:50:06:setup_element:INFO: Setting the data phase to 11 for uplink 20
10:50:06:setup_element:INFO: Setting the data phase to 10 for uplink 21
10:50:06:setup_element:INFO: Setting the data phase to 15 for uplink 22
10:50:06:setup_element:INFO: Setting the data phase to 11 for uplink 23
10:50:06:setup_element:INFO: Setting the data phase to 20 for uplink 24
10:50:06:setup_element:INFO: Setting the data phase to 24 for uplink 25
10:50:06:setup_element:INFO: Setting the data phase to 21 for uplink 26
10:50:06:setup_element:INFO: Setting the data phase to 26 for uplink 27
10:50:06:setup_element:INFO: Setting the data phase to 29 for uplink 28
10:50:06:setup_element:INFO: Setting the data phase to 32 for uplink 29
10:50:06:setup_element:INFO: Setting the data phase to 30 for uplink 30
10:50:06:setup_element:INFO: Setting the data phase to 30 for uplink 31
10:50:06:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 73
Eye Windows:
Uplink 16: ______________________________________________________________________XXXXX_____
Uplink 17: ______________________________________________________________________XXXXX_____
Uplink 18: ______________________________________________________________________XXXXX_____
Uplink 19: ______________________________________________________________________XXXXX_____
Uplink 20: ______________________________________________________________________XXXXX_____
Uplink 21: ______________________________________________________________________XXXXX_____
Uplink 22: ________________________________________________________________________XXXXX___
Uplink 23: ________________________________________________________________________XXXXX___
Uplink 24: _______________________________________________________________________XXXX_____
Uplink 25: _______________________________________________________________________XXXX_____
Uplink 26: ______________________________________________________________________XXXXX_____
Uplink 27: ______________________________________________________________________XXXXX_____
Uplink 28: _______________________________________________________________________XXXXX____
Uplink 29: _______________________________________________________________________XXXXX____
Uplink 30: _______________________________________________________________________XXXXXX___
Uplink 31: _______________________________________________________________________XXXXXX___
Data phase characteristics:
Uplink 16:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 17:
Optimal Phase: 8
Window Length: 36
Eye Window: ___________________________XXXX_________
Uplink 18:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 19:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 20:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 21:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 11
Window Length: 36
Eye Window: ______________________________XXXX______
Uplink 24:
Optimal Phase: 20
Window Length: 32
Eye Window: XXXXX________________________________XXX
Uplink 25:
Optimal Phase: 24
Window Length: 34
Eye Window: __XXXXXX________________________________
Uplink 26:
Optimal Phase: 21
Window Length: 33
Eye Window: XXXXX_________________________________XX
Uplink 27:
Optimal Phase: 26
Window Length: 33
Eye Window: ___XXXXXXX______________________________
Uplink 28:
Optimal Phase: 29
Window Length: 36
Eye Window: ________XXXX____________________________
Uplink 29:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 30:
Optimal Phase: 30
Window Length: 33
Eye Window: _______XXXXXXX__________________________
Uplink 31:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
]
10:50:06:setup_element:INFO: Beginning SMX ASICs map scan
10:50:06:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:50:06:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:50:06:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
10:50:06:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
10:50:06:uplink:INFO: Setting uplinks mask [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
10:50:06:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 0, uplink 23
10:50:06:setup_element:INFO: Adding ASIC 0x0, ASIC uplink 1, uplink 22
10:50:07:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
10:50:07:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
10:50:07:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 0, uplink 21
10:50:07:setup_element:INFO: Adding ASIC 0x2, ASIC uplink 1, uplink 20
10:50:07:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
10:50:07:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
10:50:07:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 0, uplink 19
10:50:07:setup_element:INFO: Adding ASIC 0x4, ASIC uplink 1, uplink 18
10:50:07:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
10:50:07:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
10:50:08:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 0, uplink 17
10:50:08:setup_element:INFO: Adding ASIC 0x6, ASIC uplink 1, uplink 16
10:50:08:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
10:50:08:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
10:50:09:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x0: (ASIC uplink, uplink): (0, 23), (1, 22)
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x2: (ASIC uplink, uplink): (0, 21), (1, 20)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x4: (ASIC uplink, uplink): (0, 19), (1, 18)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x6: (ASIC uplink, uplink): (0, 17), (1, 16)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 33
Window Length: 73
Eye Windows:
Uplink 16: ______________________________________________________________________XXXXX_____
Uplink 17: ______________________________________________________________________XXXXX_____
Uplink 18: ______________________________________________________________________XXXXX_____
Uplink 19: ______________________________________________________________________XXXXX_____
Uplink 20: ______________________________________________________________________XXXXX_____
Uplink 21: ______________________________________________________________________XXXXX_____
Uplink 22: ________________________________________________________________________XXXXX___
Uplink 23: ________________________________________________________________________XXXXX___
Uplink 24: _______________________________________________________________________XXXX_____
Uplink 25: _______________________________________________________________________XXXX_____
Uplink 26: ______________________________________________________________________XXXXX_____
Uplink 27: ______________________________________________________________________XXXXX_____
Uplink 28: _______________________________________________________________________XXXXX____
Uplink 29: _______________________________________________________________________XXXXX____
Uplink 30: _______________________________________________________________________XXXXXX___
Uplink 31: _______________________________________________________________________XXXXXX___
Data phase characteristics:
Uplink 16:
Optimal Phase: 12
Window Length: 35
Eye Window: ______________________________XXXXX_____
Uplink 17:
Optimal Phase: 8
Window Length: 36
Eye Window: ___________________________XXXX_________
Uplink 18:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 19:
Optimal Phase: 7
Window Length: 34
Eye Window: _________________________XXXXXX_________
Uplink 20:
Optimal Phase: 11
Window Length: 35
Eye Window: _____________________________XXXXX______
Uplink 21:
Optimal Phase: 10
Window Length: 35
Eye Window: ____________________________XXXXX_______
Uplink 22:
Optimal Phase: 15
Window Length: 36
Eye Window: __________________________________XXXX__
Uplink 23:
Optimal Phase: 11
Window Length: 36
Eye Window: ______________________________XXXX______
Uplink 24:
Optimal Phase: 20
Window Length: 32
Eye Window: XXXXX________________________________XXX
Uplink 25:
Optimal Phase: 24
Window Length: 34
Eye Window: __XXXXXX________________________________
Uplink 26:
Optimal Phase: 21
Window Length: 33
Eye Window: XXXXX_________________________________XX
Uplink 27:
Optimal Phase: 26
Window Length: 33
Eye Window: ___XXXXXXX______________________________
Uplink 28:
Optimal Phase: 29
Window Length: 36
Eye Window: ________XXXX____________________________
Uplink 29:
Optimal Phase: 32
Window Length: 35
Eye Window: __________XXXXX_________________________
Uplink 30:
Optimal Phase: 30
Window Length: 33
Eye Window: _______XXXXXXX__________________________
Uplink 31:
Optimal Phase: 30
Window Length: 35
Eye Window: ________XXXXX___________________________
10:50:09:setup_element:INFO: Performing Elink synchronization
10:50:09:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
10:50:09:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
10:50:09:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
10:50:09:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
10:50:09:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
10:50:09:uplink:INFO: Enabling uplinks [16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31]
10:50:09:ST3_emu:INFO: Number of chips: 8
addr | upli | dwnli | grp | uplinks | uplinks_map
0 | [0] | 2 | 0 | [23] | [(0, 23), (1, 22)]
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
2 | [0] | 2 | 0 | [21] | [(0, 21), (1, 20)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
4 | [0] | 2 | 0 | [19] | [(0, 19), (1, 18)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
6 | [0] | 2 | 0 | [17] | [(0, 17), (1, 16)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
FEB type: B FEB_A: 0 FEB_B: 1
10:50:10:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:50:11:febtest:INFO: 23-00 | XA-000-08-003-000-001-222-01 | 28.2 | 1253.7
10:50:11:febtest:INFO: 30-01 | XA-000-08-003-000-001-214-01 | 28.2 | 1247.9
10:50:11:febtest:INFO: 21-02 | XA-000-08-003-000-001-223-01 | 9.3 | 1311.9
10:50:11:febtest:INFO: 28-03 | XA-000-08-003-000-001-215-01 | 18.7 | 1282.9
10:50:11:febtest:INFO: 19-04 | XA-000-08-003-000-001-224-08 | 12.4 | 1311.9
10:50:12:febtest:INFO: 26-05 | XA-000-08-003-000-001-217-01 | 18.7 | 1277.1
10:50:12:febtest:INFO: 17-06 | XA-000-08-003-000-001-226-08 | 12.4 | 1294.5
10:50:12:febtest:INFO: 24-07 | XA-000-08-003-000-001-220-01 | 15.6 | 1294.5
10:50:12:ST3_smx:INFO: Configuring SMX FAST
10:50:15:ST3_smx:INFO: chip: 23-0 34.556970 C 1230.330540 mV
10:50:15:ST3_smx:INFO: Electrons
10:50:15:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:50:17:ST3_smx:INFO: ----> Checking Analog response
10:50:17:ST3_smx:INFO: ----> Checking broken channels
10:50:17:ST3_smx:INFO: Total # broken ch: 5
10:50:17:ST3_smx:INFO: List FAST: [36, 73, 82, 125, 126]
10:50:17:ST3_smx:INFO: List SLOW: []
10:50:17:ST3_smx:INFO: Holes
10:50:17:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:50:20:ST3_smx:INFO: ----> Checking Analog response
10:50:20:ST3_smx:INFO: ----> Checking broken channels
10:50:20:ST3_smx:INFO: Total # broken ch: 5
10:50:20:ST3_smx:INFO: List FAST: [36, 73, 82, 125, 126]
10:50:20:ST3_smx:INFO: List SLOW: []
10:50:21:ST3_smx:INFO: Configuring SMX FAST
10:50:23:ST3_smx:INFO: chip: 30-1 21.902970 C 1271.227515 mV
10:50:23:ST3_smx:INFO: Electrons
10:50:23:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:50:26:ST3_smx:INFO: ----> Checking Analog response
10:50:26:ST3_smx:INFO: ----> Checking broken channels
10:50:26:ST3_smx:INFO: Total # broken ch: 3
10:50:26:ST3_smx:INFO: List FAST: [72, 93, 109]
10:50:26:ST3_smx:INFO: List SLOW: []
10:50:26:ST3_smx:INFO: Holes
10:50:26:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:50:29:ST3_smx:INFO: ----> Checking Analog response
10:50:29:ST3_smx:INFO: ----> Checking broken channels
10:50:29:ST3_smx:INFO: Total # broken ch: 3
10:50:29:ST3_smx:INFO: List FAST: [72, 93, 109]
10:50:29:ST3_smx:INFO: List SLOW: []
10:50:30:ST3_smx:INFO: Configuring SMX FAST
10:50:32:ST3_smx:INFO: chip: 21-2 15.590880 C 1300.290540 mV
10:50:32:ST3_smx:INFO: Electrons
10:50:32:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:50:35:ST3_smx:INFO: ----> Checking Analog response
10:50:35:ST3_smx:INFO: ----> Checking broken channels
10:50:35:ST3_smx:INFO: Total # broken ch: 1
10:50:35:ST3_smx:INFO: List FAST: [64]
10:50:35:ST3_smx:INFO: List SLOW: []
10:50:35:ST3_smx:INFO: Holes
10:50:35:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:50:38:ST3_smx:INFO: ----> Checking Analog response
10:50:38:ST3_smx:INFO: ----> Checking broken channels
10:50:38:ST3_smx:INFO: Total # broken ch: 1
10:50:38:ST3_smx:INFO: List FAST: [64]
10:50:38:ST3_smx:INFO: List SLOW: []
10:50:39:ST3_smx:INFO: Configuring SMX FAST
10:50:41:ST3_smx:INFO: chip: 28-3 18.745682 C 1282.867635 mV
10:50:41:ST3_smx:INFO: Electrons
10:50:41:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:50:44:ST3_smx:INFO: ----> Checking Analog response
10:50:44:ST3_smx:INFO: ----> Checking broken channels
10:50:44:ST3_smx:INFO: Total # broken ch: 2
10:50:44:ST3_smx:INFO: List FAST: [56, 102]
10:50:44:ST3_smx:INFO: List SLOW: []
10:50:44:ST3_smx:INFO: Holes
10:50:44:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:50:47:ST3_smx:INFO: ----> Checking Analog response
10:50:47:ST3_smx:INFO: ----> Checking broken channels
10:50:47:ST3_smx:INFO: Total # broken ch: 2
10:50:47:ST3_smx:INFO: List FAST: [56, 102]
10:50:47:ST3_smx:INFO: List SLOW: []
10:50:48:ST3_smx:INFO: Configuring SMX FAST
10:50:50:ST3_smx:INFO: chip: 19-4 12.438562 C 1317.668715 mV
10:50:50:ST3_smx:INFO: Electrons
10:50:50:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:50:53:ST3_smx:INFO: ----> Checking Analog response
10:50:53:ST3_smx:INFO: ----> Checking broken channels
10:50:53:ST3_smx:INFO: Total # broken ch: 6
10:50:53:ST3_smx:INFO: List FAST: [13, 19, 36, 50, 114, 126]
10:50:53:ST3_smx:INFO: List SLOW: []
10:50:53:ST3_smx:INFO: Holes
10:50:53:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:50:56:ST3_smx:INFO: ----> Checking Analog response
10:50:56:ST3_smx:INFO: ----> Checking broken channels
10:50:56:ST3_smx:INFO: Total # broken ch: 6
10:50:56:ST3_smx:INFO: List FAST: [13, 19, 36, 50, 114, 126]
10:50:56:ST3_smx:INFO: List SLOW: []
10:50:56:ST3_smx:INFO: Configuring SMX FAST
10:50:59:ST3_smx:INFO: chip: 26-5 25.062742 C 1259.567515 mV
10:50:59:ST3_smx:INFO: Electrons
10:50:59:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:51:01:ST3_smx:INFO: ----> Checking Analog response
10:51:01:ST3_smx:INFO: ----> Checking broken channels
10:51:01:ST3_smx:INFO: Total # broken ch: 0
10:51:01:ST3_smx:INFO: List FAST: []
10:51:01:ST3_smx:INFO: List SLOW: []
10:51:01:ST3_smx:INFO: Holes
10:51:01:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:51:04:ST3_smx:INFO: ----> Checking Analog response
10:51:04:ST3_smx:INFO: ----> Checking broken channels
10:51:04:ST3_smx:INFO: Total # broken ch: 0
10:51:04:ST3_smx:INFO: List FAST: []
10:51:04:ST3_smx:INFO: List SLOW: []
10:51:05:ST3_smx:INFO: Configuring SMX FAST
10:51:07:ST3_smx:INFO: chip: 17-6 12.438562 C 1311.880960 mV
10:51:07:ST3_smx:INFO: Electrons
10:51:07:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:51:09:ST3_smx:INFO: ----> Checking Analog response
10:51:09:ST3_smx:INFO: ----> Checking broken channels
10:51:10:ST3_smx:INFO: Total # broken ch: 3
10:51:10:ST3_smx:INFO: List FAST: [23, 75]
10:51:10:ST3_smx:INFO: List SLOW: [75]
10:51:10:ST3_smx:INFO: Holes
10:51:10:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:51:12:ST3_smx:INFO: ----> Checking Analog response
10:51:12:ST3_smx:INFO: ----> Checking broken channels
10:51:12:ST3_smx:INFO: Total # broken ch: 3
10:51:12:ST3_smx:INFO: List FAST: [23, 75]
10:51:12:ST3_smx:INFO: List SLOW: [75]
10:51:13:ST3_smx:INFO: Configuring SMX FAST
10:51:15:ST3_smx:INFO: chip: 24-7 15.590880 C 1300.290540 mV
10:51:15:ST3_smx:INFO: Electrons
10:51:15:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:51:18:ST3_smx:INFO: ----> Checking Analog response
10:51:18:ST3_smx:INFO: ----> Checking broken channels
10:51:18:ST3_smx:INFO: Total # broken ch: 4
10:51:18:ST3_smx:INFO: List FAST: [2, 24, 80, 125]
10:51:18:ST3_smx:INFO: List SLOW: []
10:51:18:ST3_smx:INFO: Holes
10:51:18:ST3_smx:INFO: Injected pulses: 150LSB, amp_cal 8.400000 fC
10:51:20:ST3_smx:INFO: ----> Checking Analog response
10:51:20:ST3_smx:INFO: ----> Checking broken channels
10:51:21:ST3_smx:INFO: Total # broken ch: 4
10:51:21:ST3_smx:INFO: List FAST: [2, 24, 80, 125]
10:51:21:ST3_smx:INFO: List SLOW: []
10:51:21:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
10:51:21:febtest:INFO: 23-00 | XA-000-08-003-000-001-222-01 | 37.7 | 1230.3
10:51:22:febtest:INFO: 30-01 | XA-000-08-003-000-001-214-01 | 25.1 | 1265.4
10:51:22:febtest:INFO: 21-02 | XA-000-08-003-000-001-223-01 | 18.7 | 1294.5
10:51:22:febtest:INFO: 28-03 | XA-000-08-003-000-001-215-01 | 18.7 | 1277.1
10:51:22:febtest:INFO: 19-04 | XA-000-08-003-000-001-224-08 | 12.4 | 1317.7
10:51:22:febtest:INFO: 26-05 | XA-000-08-003-000-001-217-01 | 25.1 | 1253.7
10:51:23:febtest:INFO: 17-06 | XA-000-08-003-000-001-226-08 | 12.4 | 1306.1
10:51:23:febtest:INFO: 24-07 | XA-000-08-003-000-001-220-01 | 15.6 | 1294.5
############################################################
# S U M M A R Y #
############################################################
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
{'CSA_FRONT': 30, 'IFED': 31, 'PSC_BIAS': 131, 'SH_BIAS': 15, 'AMP_CAL': 150, 'SH_SLOW': 0, 'IREF_FAST': 32, 'THR2_GLB': 30, 'ADC_VREF_N': 30, 'ADC_VREF_P': 58, 'ADC_VREF_T': 128, 'CAL_STROBE': 64, 'IN_CSAP': 30, 'CSA_BACK': 30, 'CSA_CAS_BUF': 27, 'SH_CAS_BUF': 27, 'CSA_BIAS': 91, 'DAC_THR1': 0, 'ADC_VREF_TR': 122, 'DIAG_IBIAS': 31}
===============================
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-ASIC
TEST_DATE : 24_04_23-10_49_57
OPERATOR : Benjamin;
SITE : KIT
SETUP : KIT_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME :
FEB_SN : 4015
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 0
FEB_B : 1
---------------------------------------
MODULE_NAME
---------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.201', '1.5210', '2.800', '1.6780']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.200', '1.7880', '2.800', '0.3465']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.200', '1.7870', '2.800', '0.3210']