FEB_4041 21.06.24 12:50:59
Info
12:50:59:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:50:59:ST3_Shared:INFO: FEB-Microcable
12:50:59:ST3_Shared:INFO: oooooooooooooooooooooooooooooooooooooooooooooooooooooooooooo
12:50:59:febtest:INFO: Testing FEB with SN 4041
12:51:02:smx_tester:INFO: Scanning setup
12:51:02:elinks:INFO: Disabling clock on downlink 0
12:51:02:elinks:INFO: Disabling clock on downlink 1
12:51:02:elinks:INFO: Disabling clock on downlink 2
12:51:02:elinks:INFO: Disabling clock on downlink 3
12:51:02:elinks:INFO: Disabling clock on downlink 4
12:51:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:51:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [0]
12:51:02:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:51:02:elinks:INFO: Disabling clock on downlink 0
12:51:02:elinks:INFO: Disabling clock on downlink 1
12:51:02:elinks:INFO: Disabling clock on downlink 2
12:51:02:elinks:INFO: Disabling clock on downlink 3
12:51:02:elinks:INFO: Disabling clock on downlink 4
12:51:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:51:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [1]
12:51:02:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:51:02:elinks:INFO: Disabling clock on downlink 0
12:51:02:elinks:INFO: Disabling clock on downlink 1
12:51:02:elinks:INFO: Disabling clock on downlink 2
12:51:02:elinks:INFO: Disabling clock on downlink 3
12:51:02:elinks:INFO: Disabling clock on downlink 4
12:51:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:51:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:51:02:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 24
12:51:02:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 25
12:51:02:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 26
12:51:02:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 27
12:51:02:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 28
12:51:02:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 29
12:51:02:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 30
12:51:02:setup_element:INFO: SOS detected for group 0, downlink 2, uplink 31
12:51:02:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:51:02:elinks:INFO: Disabling clock on downlink 0
12:51:02:elinks:INFO: Disabling clock on downlink 1
12:51:02:elinks:INFO: Disabling clock on downlink 2
12:51:02:elinks:INFO: Disabling clock on downlink 3
12:51:02:elinks:INFO: Disabling clock on downlink 4
12:51:02:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:51:02:master:INFO: Setting encoding mode SOS for groups [0], downlinks [3]
12:51:03:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:51:03:elinks:INFO: Disabling clock on downlink 0
12:51:03:elinks:INFO: Disabling clock on downlink 1
12:51:03:elinks:INFO: Disabling clock on downlink 2
12:51:03:elinks:INFO: Disabling clock on downlink 3
12:51:03:elinks:INFO: Disabling clock on downlink 4
12:51:03:setup_element:INFO: Checking SOS, encoding_mode: SOS
12:51:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [4]
12:51:03:setup_element:INFO: Reassigning uplinks to uplinks which passed SOS detection
12:51:03:setup_element:INFO: Scanning clock phase
12:51:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:51:03:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:51:03:setup_element:INFO: Clock phase scan results for group 0, downlink 2
12:51:03:setup_element:INFO: Eye window for uplink 24: _____________________________________________________________________XXXXXX_____
Clock Delay: 31
12:51:03:setup_element:INFO: Eye window for uplink 25: _____________________________________________________________________XXXXXX_____
Clock Delay: 31
12:51:03:setup_element:INFO: Eye window for uplink 26: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
12:51:03:setup_element:INFO: Eye window for uplink 27: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
12:51:03:setup_element:INFO: Eye window for uplink 28: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
12:51:03:setup_element:INFO: Eye window for uplink 29: _____________________________________________________________________XXXXXXX____
Clock Delay: 32
12:51:03:setup_element:INFO: Eye window for uplink 30: _______________________________________________________________________XXXXXX___
Clock Delay: 33
12:51:03:setup_element:INFO: Eye window for uplink 31: _______________________________________________________________________XXXXXX___
Clock Delay: 33
12:51:03:setup_element:INFO: Setting the clock phase to 32 for group 0, downlink 2
12:51:03:setup_element:INFO: Scanning data phases
12:51:03:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:51:03:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:51:08:setup_element:INFO: Data phase scan results for group 0, downlink 2
12:51:08:setup_element:INFO: Eye window for uplink 24: XXXXXX______________________________XXXX
Data delay found: 20
12:51:08:setup_element:INFO: Eye window for uplink 25: _XXXXXXXX_______________________________
Data delay found: 24
12:51:08:setup_element:INFO: Eye window for uplink 26: XXXXXXX________________________________X
Data delay found: 22
12:51:08:setup_element:INFO: Eye window for uplink 27: _____XXXXXXXX___________________________
Data delay found: 28
12:51:08:setup_element:INFO: Eye window for uplink 28: _____XXXXXX_____________________________
Data delay found: 27
12:51:08:setup_element:INFO: Eye window for uplink 29: _______XXXXXXXX_________________________
Data delay found: 30
12:51:08:setup_element:INFO: Eye window for uplink 30: ____XXXXXXXXXXXXX_______________________
Data delay found: 30
12:51:08:setup_element:INFO: Eye window for uplink 31: _____XXXXXXXXXXX________________________
Data delay found: 30
12:51:08:setup_element:INFO: Setting the data phase to 20 for uplink 24
12:51:08:setup_element:INFO: Setting the data phase to 24 for uplink 25
12:51:08:setup_element:INFO: Setting the data phase to 22 for uplink 26
12:51:08:setup_element:INFO: Setting the data phase to 28 for uplink 27
12:51:08:setup_element:INFO: Setting the data phase to 27 for uplink 28
12:51:08:setup_element:INFO: Setting the data phase to 30 for uplink 29
12:51:08:setup_element:INFO: Setting the data phase to 30 for uplink 30
12:51:08:setup_element:INFO: Setting the data phase to 30 for uplink 31
12:51:08:ST3_emu:ERROR: [
Setup Element:
Group: 0
Downlink: 2
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map: None
Clock Phase Characteristic:
Optimal Phase: 32
Window Length: 72
Eye Windows:
Uplink 24: _____________________________________________________________________XXXXXX_____
Uplink 25: _____________________________________________________________________XXXXXX_____
Uplink 26: _____________________________________________________________________XXXXXXX____
Uplink 27: _____________________________________________________________________XXXXXXX____
Uplink 28: _____________________________________________________________________XXXXXXX____
Uplink 29: _____________________________________________________________________XXXXXXX____
Uplink 30: _______________________________________________________________________XXXXXX___
Uplink 31: _______________________________________________________________________XXXXXX___
Data phase characteristics:
Uplink 24:
Optimal Phase: 20
Window Length: 30
Eye Window: XXXXXX______________________________XXXX
Uplink 25:
Optimal Phase: 24
Window Length: 32
Eye Window: _XXXXXXXX_______________________________
Uplink 26:
Optimal Phase: 22
Window Length: 32
Eye Window: XXXXXXX________________________________X
Uplink 27:
Optimal Phase: 28
Window Length: 32
Eye Window: _____XXXXXXXX___________________________
Uplink 28:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 29:
Optimal Phase: 30
Window Length: 32
Eye Window: _______XXXXXXXX_________________________
Uplink 30:
Optimal Phase: 30
Window Length: 27
Eye Window: ____XXXXXXXXXXXXX_______________________
Uplink 31:
Optimal Phase: 30
Window Length: 29
Eye Window: _____XXXXXXXXXXX________________________
]
12:51:08:setup_element:INFO: Beginning SMX ASICs map scan
12:51:08:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:51:08:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:51:08:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
12:51:08:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
12:51:08:uplink:INFO: Setting uplinks mask [24, 25, 26, 27, 28, 29, 30, 31]
12:51:08:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 0, uplink 30
12:51:08:setup_element:INFO: Adding ASIC 0x1, ASIC uplink 1, uplink 31
12:51:09:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 0, uplink 28
12:51:09:setup_element:INFO: Adding ASIC 0x3, ASIC uplink 1, uplink 29
12:51:09:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 0, uplink 26
12:51:09:setup_element:INFO: Adding ASIC 0x5, ASIC uplink 1, uplink 27
12:51:09:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 0, uplink 24
12:51:09:setup_element:INFO: Adding ASIC 0x7, ASIC uplink 1, uplink 25
12:51:11:ST3_emu:ERROR:
Setup Element:
Group: 0
Downlink: 2
Uplinks: [24, 25, 26, 27, 28, 29, 30, 31]
ASICs Map:
ASIC address 0x1: (ASIC uplink, uplink): (0, 30), (1, 31)
ASIC address 0x3: (ASIC uplink, uplink): (0, 28), (1, 29)
ASIC address 0x5: (ASIC uplink, uplink): (0, 26), (1, 27)
ASIC address 0x7: (ASIC uplink, uplink): (0, 24), (1, 25)
Clock Phase Characteristic:
Optimal Phase: 32
Window Length: 72
Eye Windows:
Uplink 24: _____________________________________________________________________XXXXXX_____
Uplink 25: _____________________________________________________________________XXXXXX_____
Uplink 26: _____________________________________________________________________XXXXXXX____
Uplink 27: _____________________________________________________________________XXXXXXX____
Uplink 28: _____________________________________________________________________XXXXXXX____
Uplink 29: _____________________________________________________________________XXXXXXX____
Uplink 30: _______________________________________________________________________XXXXXX___
Uplink 31: _______________________________________________________________________XXXXXX___
Data phase characteristics:
Uplink 24:
Optimal Phase: 20
Window Length: 30
Eye Window: XXXXXX______________________________XXXX
Uplink 25:
Optimal Phase: 24
Window Length: 32
Eye Window: _XXXXXXXX_______________________________
Uplink 26:
Optimal Phase: 22
Window Length: 32
Eye Window: XXXXXXX________________________________X
Uplink 27:
Optimal Phase: 28
Window Length: 32
Eye Window: _____XXXXXXXX___________________________
Uplink 28:
Optimal Phase: 27
Window Length: 34
Eye Window: _____XXXXXX_____________________________
Uplink 29:
Optimal Phase: 30
Window Length: 32
Eye Window: _______XXXXXXXX_________________________
Uplink 30:
Optimal Phase: 30
Window Length: 27
Eye Window: ____XXXXXXXXXXXXX_______________________
Uplink 31:
Optimal Phase: 30
Window Length: 29
Eye Window: _____XXXXXXXXXXX________________________
12:51:11:setup_element:INFO: Performing Elink synchronization
12:51:11:master:INFO: Setting encoding mode SOS for groups [0], downlinks [2]
12:51:11:master:INFO: Setting encoding mode K.28.1 for groups [0], downlinks [2]
12:51:11:master:INFO: Setting encoding mode EOS for groups [0], downlinks [2]
12:51:11:master:INFO: Setting encoding mode FRAME for groups [0], downlinks [2]
12:51:11:setup_element:INFO: Writing SMX Elink masks for group 0, downlink 2
12:51:11:uplink:INFO: Enabling uplinks [24, 25, 26, 27, 28, 29, 30, 31]
12:51:11:ST3_emu:INFO: Number of chips: 4
addr | upli | dwnli | grp | uplinks | uplinks_map
1 | [0] | 2 | 0 | [30] | [(0, 30), (1, 31)]
3 | [0] | 2 | 0 | [28] | [(0, 28), (1, 29)]
5 | [0] | 2 | 0 | [26] | [(0, 26), (1, 27)]
7 | [0] | 2 | 0 | [24] | [(0, 24), (1, 25)]
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_5_26 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_5_26 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_B__addr_5__upli_26
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_h_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_h_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_h_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_h_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_h_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_h_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_front_e_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: h2D_back_e_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_fastD_e_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_front_e_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hDist_back_e_7_24 (Potential memory leak).
TROOT::Append:0: RuntimeWarning: Replacing existing TH1: hBroken_e_7_24 (Potential memory leak).
TCanvas::Constructor:0: RuntimeWarning: Deleting canvas with same name: cDist_FEB_B__addr_7__upli_24
FEB type: B FEB_A: 0 FEB_B: 1
12:51:12:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
12:51:12:febtest:INFO: 30-01 | XA-000-08-003-000-002-158-10 | 18.7 | 1253.7
12:51:12:febtest:INFO: 28-03 | XA-000-08-003-000-002-157-10 | 44.1 | 1165.6
12:51:12:febtest:INFO: 26-05 | XA-000-08-003-000-002-154-10 | 34.6 | 1206.9
12:51:13:febtest:INFO: 24-07 | XA-000-08-003-000-002-141-13 | 25.1 | 1224.5
12:51:13:ST3_smx:INFO: Configuring SMX FAST
12:51:15:ST3_smx:INFO: chip: 30-1 28.225000 C 1212.728715 mV
12:51:15:ST3_smx:INFO: Electrons
12:51:15:ST3_smx:INFO: # loops 0
12:51:16:ST3_smx:INFO: # loops 1
12:51:18:ST3_smx:INFO: # loops 2
12:51:19:ST3_smx:INFO: Total # of broken channels: 0
12:51:19:ST3_smx:INFO: List of broken channels: []
12:51:19:ST3_smx:INFO: Total # of broken channels: 0
12:51:19:ST3_smx:INFO: List of broken channels: []
12:51:20:ST3_smx:INFO: Configuring SMX FAST
12:51:22:ST3_smx:INFO: chip: 28-3 50.430383 C 1147.806000 mV
12:51:22:ST3_smx:INFO: Electrons
12:51:22:ST3_smx:INFO: # loops 0
12:51:24:ST3_smx:INFO: # loops 1
12:51:25:ST3_smx:INFO: # loops 2
12:51:27:ST3_smx:INFO: Total # of broken channels: 0
12:51:27:ST3_smx:INFO: List of broken channels: []
12:51:27:ST3_smx:INFO: Total # of broken channels: 0
12:51:27:ST3_smx:INFO: List of broken channels: []
12:51:28:ST3_smx:INFO: Configuring SMX FAST
12:51:30:ST3_smx:INFO: chip: 26-5 34.556970 C 1200.969315 mV
12:51:30:ST3_smx:INFO: Electrons
12:51:30:ST3_smx:INFO: # loops 0
12:51:31:ST3_smx:INFO: # loops 1
12:51:33:ST3_smx:INFO: # loops 2
12:51:35:ST3_smx:INFO: Total # of broken channels: 0
12:51:35:ST3_smx:INFO: List of broken channels: []
12:51:35:ST3_smx:INFO: Total # of broken channels: 0
12:51:35:ST3_smx:INFO: List of broken channels: []
12:51:35:ST3_smx:INFO: Configuring SMX FAST
12:51:37:ST3_smx:INFO: chip: 24-7 40.898880 C 1183.292940 mV
12:51:37:ST3_smx:INFO: Electrons
12:51:37:ST3_smx:INFO: # loops 0
12:51:39:ST3_smx:INFO: # loops 1
12:51:41:ST3_smx:INFO: # loops 2
12:51:43:ST3_smx:INFO: Total # of broken channels: 0
12:51:43:ST3_smx:INFO: List of broken channels: []
12:51:43:ST3_smx:INFO: Total # of broken channels: 0
12:51:43:ST3_smx:INFO: List of broken channels: []
12:51:44:febtest:INFO: _Addr_|___________ASIC-ID_____________|_T_[C]_|_Vddm_[mV]_
12:51:44:febtest:INFO: 30-01 | XA-000-08-003-000-002-158-10 | 28.2 | 1218.6
12:51:44:febtest:INFO: 28-03 | XA-000-08-003-000-002-157-10 | 50.4 | 1147.8
12:51:44:febtest:INFO: 26-05 | XA-000-08-003-000-002-154-10 | 34.6 | 1201.0
12:51:44:febtest:INFO: 24-07 | XA-000-08-003-000-002-141-13 | 40.9 | 1183.3
############################################################
# S U M M A R Y #
############################################################
TEST_NAME : FEB-Microcable
TEST_DATE : 24_06_21-12_50_59
OPERATOR : Benjamin;
SITE : KIT
SETUP : KIT_TEST_SETUP_1
Set-ID :
---------------------------------------
MODULE_NAME : L6UL201035 M6UL2B4010354A2 124 C
FEB_SN : 4041
FEB_TYPE : 8.2
FEB_UPLINKS : 2
FEB_A : 0
FEB_B : 1
---------------------------------------
---------------------------------------
VI_before_Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '0.7151', '1.850', '1.5040']
VI_after__Init : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0080', '1.850', '0.1634']
VI_at__the_End : ['0.000', '0.0000', '0.000', '0.0000', '2.450', '1.0070', '1.850', '0.1633']